Menu
▾
▴
HP6xx getting rid of PIO
|
From: Kristoffer E. <kri...@ho...> - 2007-03-15 22:31:07
|
Greetings, In order to get a more proper enviroment I started removing the PIO stuff from io.c and adding correct adresses into hd64461.h. Im still getting exactly same error though. Some please take a look at this diff and tell me what im doing wrong. --- ../linux-2.6/include/asm-sh/hd64461.h 2006-09-27 19:23:52.000000000 +0000 +++ include/asm-sh/hd64461.h 2007-03-15 23:27:03.000000000 +0000 @@ -18,8 +18,9 @@ #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) #define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) -#define HD64461_STBCR 0x10000 -#define HD64461_STBCR_CKIO_STBY 0x2000 +/* if PORT < 0xf000 then ADDR = 0xa0000000 + PORT */ +#define HD64461_STBCR (CONFIG_HD64461_IOBASE + 0x10000 - 0x10000) +#define HD64461_STBCR_CKIO_STBY 0x2000 #define HD64461_STBCR_SAFECKE_IST 0x1000 #define HD64461_STBCR_SLCKE_IST 0x0800 #define HD64461_STBCR_SAFECKE_OST 0x0400 @@ -31,15 +32,18 @@ #define HD64461_STBCR_SAFEST 0x0010 #define HD64461_STBCR_STM0ST 0x0008 #define HD64461_STBCR_STM1ST 0x0004 -#define HD64461_STBCR_SIRST 0x0002 +#define HD64461_STBCR_SIRST 0x0002 #define HD64461_STBCR_SURTST 0x0001 -#define HD64461_SYSCR 0x10002 -#define HD64461_SCPUCR 0x10004 +/* if PORT < 0x20000 then ADDR = CONFIG_HD64461_IOBASE + PORT - 0x10000 */ +#define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x10002 - 0x10000) +#define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x10004 - 0x10000) +#define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x11000 - 0x10000) +#define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x11002 - 0x10000) +#define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x11004 - 0x10000) -#define HD64461_LCDCBAR 0x11000 -#define HD64461_LCDCLOR 0x11002 -#define HD64461_LCDCCR 0x11004 + +/* if PORT < 0xf000 then ADDR = 0xa0000000 + PORT */ #define HD64461_LCDCCR_STBACK 0x0400 #define HD64461_LCDCCR_STREQ 0x0100 #define HD64461_LCDCCR_MOFF 0x0080 @@ -47,142 +51,150 @@ #define HD64461_LCDCCR_EPON 0x0020 #define HD64461_LCDCCR_SPON 0x0010 -#define HD64461_LDR1 0x11010 +/* if PORT < 0x20000 then ADDR = CONFIG_HD64461_IOBASE + PORT - 0x10000 */ +#define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x11010 - 0x10000) + +/* if PORT < 0xf000 then ADDR = 0xa0000000 + PORT */ #define HD64461_LDR1_DON 0x01 #define HD64461_LDR1_DINV 0x80 -#define HD64461_LDR2 0x11012 -#define HD64461_LDHNCR 0x11014 -#define HD64461_LDHNSR 0x11016 -#define HD64461_LDVNTR 0x11018 -#define HD64461_LDVNDR 0x1101a -#define HD64461_LDVSPR 0x1101c -#define HD64461_LDR3 0x1101e - -#define HD64461_CPTWAR 0x11030 -#define HD64461_CPTWDR 0x11032 -#define HD64461_CPTRAR 0x11034 -#define HD64461_CPTRDR 0x11036 - -#define HD64461_GRDOR 0x11040 -#define HD64461_GRSCR 0x11042 -#define HD64461_GRCFGR 0x11044 +/* if PORT < 0x20000 then ADDR = CONFIG_HD64461_IOBASE + PORT - 0x10000 */ +#define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x11012 - 0x10000) +#define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x11014 - 0x10000) +#define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x11016 - 0x10000) +#define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x11018 - 0x10000) +#define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x1101a - 0x10000) +#define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x1101c - 0x10000) +#define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x1101e - 0x10000) + +#define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x11030 - 0x10000) +#define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x11032 - 0x10000) +#define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x11034 - 0x10000) +#define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x11036 - 0x10000) + +#define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x11040 - 0x10000) +#define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x11042 - 0x10000) +#define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x11044 - 0x10000) + #define HD64461_GRCFGR_ACCSTATUS 0x10 #define HD64461_GRCFGR_ACCRESET 0x08 -#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 -#define HD64461_GRCFGR_ACCSTART_LINE 0x04 +#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 +#define HD64461_GRCFGR_ACCSTART_LINE 0x04 #define HD64461_GRCFGR_COLORDEPTH16 0x01 -#define HD64461_LNSARH 0x11046 -#define HD64461_LNSARL 0x11048 -#define HD64461_LNAXLR 0x1104a -#define HD64461_LNDGR 0x1104c -#define HD64461_LNAXR 0x1104e -#define HD64461_LNERTR 0x11050 -#define HD64461_LNMDR 0x11052 -#define HD64461_BBTSSARH 0x11054 -#define HD64461_BBTSSARL 0x11056 -#define HD64461_BBTDSARH 0x11058 -#define HD64461_BBTDSARL 0x1105a -#define HD64461_BBTDWR 0x1105c -#define HD64461_BBTDHR 0x1105e -#define HD64461_BBTPARH 0x11060 -#define HD64461_BBTPARL 0x11062 -#define HD64461_BBTMARH 0x11064 -#define HD64461_BBTMARL 0x11066 -#define HD64461_BBTROPR 0x11068 -#define HD64461_BBTMDR 0x1106a +/* if PORT < 0x20000 then CONFIG_HD64461_IOBASE + PORT - 0x10000 */ +#define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x11046 - 0x10000) +#define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x11048 - 0x10000) +#define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x1104a - 0x10000) +#define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x1104c - 0x10000) +#define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x1104e - 0x10000) +#define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x11050 - 0x10000) +#define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x11052 - 0x10000) +#define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x11054 - 0x10000) +#define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x11056 - 0x10000) +#define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x11058 - 0x10000) +#define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x1105a - 0x10000) +#define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x1105c - 0x10000) +#define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x1105e - 0x10000) +#define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x11060 - 0x10000) +#define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x11062 - 0x10000) +#define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x11064 - 0x10000) +#define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x11066 - 0x10000) +#define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x11068 - 0x10000) +#define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x1106a - 0x10000) +/* These must be like this, otherwise the Jornada will not boot! */ /* PC Card Controller Registers */ -#define HD64461_PCC0ISR 0x12000 /* socket 0 interface status */ -#define HD64461_PCC0GCR 0x12002 /* socket 0 general control */ -#define HD64461_PCC0CSCR 0x12004 /* socket 0 card status change */ -#define HD64461_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */ -#define HD64461_PCC0SCR 0x12008 /* socket 0 software control */ -#define HD64461_PCC1ISR 0x12010 /* socket 1 interface status */ -#define HD64461_PCC1GCR 0x12012 /* socket 1 general control */ -#define HD64461_PCC1CSCR 0x12014 /* socket 1 card status change */ -#define HD64461_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */ -#define HD64461_PCC1SCR 0x12018 /* socket 1 software control */ +#define HD64461_PCC0ISR (0xb8000000 + 0x12000 - 0x10000) /* socket 0 interface status */ +#define HD64461_PCC0GCR (0xb8000000 + 0x12002 - 0x10000) /* socket 0 general control */ +#define HD64461_PCC0CSCR (0xb8000000 + 0x12004 - 0x10000) /* socket 0 card status change */ +#define HD64461_PCC0CSCIER (0xb8000000 + 0x12006 - 0x10000) /* socket 0 card status change interrupt enable */ +#define HD64461_PCC0SCR (0xb8000000 + 0x12008 - 0x10000) /* socket 0 software control */ +#define HD64461_PCC1ISR (0xb4000000 + 0x12010 - 0x10000) /* socket 1 interface status */ +#define HD64461_PCC1GCR (0xb4000000 + 0x12012 - 0x10000) /* socket 1 general control */ +#define HD64461_PCC1CSCR (0xb4000000 + 0x12014 - 0x10000) /* socket 1 card status change */ +#define HD64461_PCC1CSCIER (0xb4000000 + 0x12016 - 0x10000) /* socket 1 card status change interrupt enable */ +#define HD64461_PCC1SCR (0xb4000000 + 0x12018 - 0x10000) /* socket 1 software control */ /* PCC Interface Status Register */ -#define HD64461_PCCISR_READY 0x80 /* card ready */ -#define HD64461_PCCISR_MWP 0x40 /* card write-protected */ -#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ -#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ -#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ -#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ -#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ -#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ - -#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ -#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ -#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ -#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ -#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ -#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ +#define HD64461_PCCISR_READY 0x80 /* card ready */ +#define HD64461_PCCISR_MWP 0x40 /* card write-protected */ +#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ +#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ +#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ +#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ +#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ +#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ + +#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ +#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ +#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ +#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ +#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ +#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ /* PCC General Control Register */ -#define HD64461_PCCGCR_DRVE 0x80 /* output drive */ -#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ -#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ -#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ -#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ -#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ -#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ -#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ +#define HD64461_PCCGCR_DRVE 0x80 /* output drive */ +#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ +#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ +#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ +#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ +#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ +#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ +#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ /* PCC Card Status Change Register */ -#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ -#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ -#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ -#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ -#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ -#define HD64461_PCCCSCR_RC 0x04 /* READY change */ -#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ -#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ +#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ +#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ +#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ +#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ +#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ +#define HD64461_PCCCSCR_RC 0x04 /* READY change */ +#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ +#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ /* PCC Card Status Change Interrupt Enable Register */ -#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ -#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ -#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ -#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ -#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ -#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ - -#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ -#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ -#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ -#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ -#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ +#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ +#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ +#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ +#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ +#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ +#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ + +#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ +#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ +#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ +#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ +#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ /* PCC Software Control Register */ -#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ -#define HD64461_PCCSCR_SWP 0x01 /* write protect */ - -#define HD64461_P0OCR 0x1202a -#define HD64461_P1OCR 0x1202c -#define HD64461_PGCR 0x1202e - -#define HD64461_GPACR 0x14000 -#define HD64461_GPBCR 0x14002 -#define HD64461_GPCCR 0x14004 -#define HD64461_GPDCR 0x14006 -#define HD64461_GPADR 0x14010 -#define HD64461_GPBDR 0x14012 -#define HD64461_GPCDR 0x14014 -#define HD64461_GPDDR 0x14016 -#define HD64461_GPAICR 0x14020 -#define HD64461_GPBICR 0x14022 -#define HD64461_GPCICR 0x14024 -#define HD64461_GPDICR 0x14026 -#define HD64461_GPAISR 0x14040 -#define HD64461_GPBISR 0x14042 -#define HD64461_GPCISR 0x14044 -#define HD64461_GPDISR 0x14046 +#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ +#define HD64461_PCCSCR_SWP 0x01 /* write protect */ -#define HD64461_NIRR 0x15000 -#define HD64461_NIMR 0x15002 +#define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x1202a - 0x10000) +#define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x1202c - 0x10000) +#define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x1202e - 0x10000) + +#define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x14000 - 0x10000) +#define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x14002 - 0x10000) +#define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x14004 - 0x10000) +#define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x14006 - 0x10000) +#define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x14010 - 0x10000) +#define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x14012 - 0x10000) +#define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x14014 - 0x10000) +#define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x14016 - 0x10000) +#define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x14020 - 0x10000) +#define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x14022 - 0x10000) +#define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x14024 - 0x10000) +#define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x14026 - 0x10000) +#define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x14040 - 0x10000) +#define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x14042 - 0x10000) +#define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x14044 - 0x10000) +#define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x14046 - 0x10000) + +/* if PORT < 20000 then ADDR = CONFIG_HD64461_IOBASE + 0x15000 - 0x10000 */ +#define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x15000 - 0x10000) +#define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x15002 - 0x10000) #define HD64461_IRQBASE OFFCHIP_IRQ_BASE #define HD64461_IRQ_NUM 16 _________________________________________________________________ Don't just search. Find. Check out the new MSN Search! http://search.msn.com/ |
