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From: Kristoffer E. <kri...@gm...> - 2007-05-17 20:42:39
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Greetings, Paul, is this patch okey or should it be done with CONFIG_IO_BASE + value? So everything can be altered through the menuconfig? I havent seen any other boards using hd64461 though. Best wishes Kristoffer Ericson Patch text: This patch fixes the problem that arose after port2addr was removed. port2addr took a abstract port value and returned the corresponding real *addr. Since chipset hd64461 no longer uses port2addr we need to supply it with proper real values. These values have been extracted from both the old port2addr function and hd64461 hardware manual reference. Comments have been added to better document functions. signed-off-by: Kristoffer Ericson <kri...@gm...> diff --git a/include/asm-sh/hd64461.h b/include/asm-sh/hd64461.h index 27e5c34..f004c9b 100644 --- a/include/asm-sh/hd64461.h +++ b/include/asm-sh/hd64461.h @@ -1,200 +1,241 @@ #ifndef __ASM_SH_HD64461 #define __ASM_SH_HD64461 /* - * $Id: hd64461.h,v 1.5 2004/03/16 00:07:51 lethal Exp $ + * Copyright (C) 2007 Kristoffer Ericson + * Copyright (C) 2004 Paul Mundt * Copyright (C) 2000 YAEGASHI Takeshi - * Hitachi HD64461 companion chip support + * + * Hitachi HD64461 companion chip support + * (please note manual reference 0x10000000 = 0xb0000000) */ /* Constants for PCMCIA mappings */ -#define HD64461_PCC_WINDOW 0x01000000 - -#define HD64461_PCC0_BASE 0xb8000000 /* area 6 */ -#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) -#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) -#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) - -#define HD64461_PCC1_BASE 0xb4000000 /* area 5 */ -#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) -#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) - -#define HD64461_STBCR 0x10000 -#define HD64461_STBCR_CKIO_STBY 0x2000 -#define HD64461_STBCR_SAFECKE_IST 0x1000 -#define HD64461_STBCR_SLCKE_IST 0x0800 -#define HD64461_STBCR_SAFECKE_OST 0x0400 -#define HD64461_STBCR_SLCKE_OST 0x0200 -#define HD64461_STBCR_SMIAST 0x0100 -#define HD64461_STBCR_SLCDST 0x0080 -#define HD64461_STBCR_SPC0ST 0x0040 -#define HD64461_STBCR_SPC1ST 0x0020 -#define HD64461_STBCR_SAFEST 0x0010 -#define HD64461_STBCR_STM0ST 0x0008 -#define HD64461_STBCR_STM1ST 0x0004 -#define HD64461_STBCR_SIRST 0x0002 -#define HD64461_STBCR_SURTST 0x0001 - -#define HD64461_SYSCR 0x10002 -#define HD64461_SCPUCR 0x10004 - -#define HD64461_LCDCBAR 0x11000 -#define HD64461_LCDCLOR 0x11002 -#define HD64461_LCDCCR 0x11004 -#define HD64461_LCDCCR_STBACK 0x0400 -#define HD64461_LCDCCR_STREQ 0x0100 -#define HD64461_LCDCCR_MOFF 0x0080 -#define HD64461_LCDCCR_REFSEL 0x0040 -#define HD64461_LCDCCR_EPON 0x0020 -#define HD64461_LCDCCR_SPON 0x0010 - -#define HD64461_LDR1 0x11010 -#define HD64461_LDR1_DON 0x01 -#define HD64461_LDR1_DINV 0x80 - -#define HD64461_LDR2 0x11012 -#define HD64461_LDHNCR 0x11014 -#define HD64461_LDHNSR 0x11016 -#define HD64461_LDVNTR 0x11018 -#define HD64461_LDVNDR 0x1101a -#define HD64461_LDVSPR 0x1101c -#define HD64461_LDR3 0x1101e - -#define HD64461_CPTWAR 0x11030 -#define HD64461_CPTWDR 0x11032 -#define HD64461_CPTRAR 0x11034 -#define HD64461_CPTRDR 0x11036 - -#define HD64461_GRDOR 0x11040 -#define HD64461_GRSCR 0x11042 -#define HD64461_GRCFGR 0x11044 -#define HD64461_GRCFGR_ACCSTATUS 0x10 -#define HD64461_GRCFGR_ACCRESET 0x08 -#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 -#define HD64461_GRCFGR_ACCSTART_LINE 0x04 -#define HD64461_GRCFGR_COLORDEPTH16 0x01 - -#define HD64461_LNSARH 0x11046 -#define HD64461_LNSARL 0x11048 -#define HD64461_LNAXLR 0x1104a -#define HD64461_LNDGR 0x1104c -#define HD64461_LNAXR 0x1104e -#define HD64461_LNERTR 0x11050 -#define HD64461_LNMDR 0x11052 -#define HD64461_BBTSSARH 0x11054 -#define HD64461_BBTSSARL 0x11056 -#define HD64461_BBTDSARH 0x11058 -#define HD64461_BBTDSARL 0x1105a -#define HD64461_BBTDWR 0x1105c -#define HD64461_BBTDHR 0x1105e -#define HD64461_BBTPARH 0x11060 -#define HD64461_BBTPARL 0x11062 -#define HD64461_BBTMARH 0x11064 -#define HD64461_BBTMARL 0x11066 -#define HD64461_BBTROPR 0x11068 -#define HD64461_BBTMDR 0x1106a +#define HD64461_PCC_WINDOW 0x01000000 + +/* Area 6 - Slot 0 - memory and/or IO card */ +#define HD64461_PCC0_BASE 0xb8000000 +#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */ +#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */ +#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */ + +/* Area 5 - Slot 1 - memory card only */ +#define HD64461_PCC1_BASE 0xb4000000 +#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */ +#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */ + +/* Standby Control Register for HD64461 */ +#define HD64461_STBCR 0xb0000000 +#define HD64461_STBCR_CKIO_STBY 0x2000 +#define HD64461_STBCR_SAFECKE_IST 0x1000 +#define HD64461_STBCR_SLCKE_IST 0x0800 +#define HD64461_STBCR_SAFECKE_OST 0x0400 +#define HD64461_STBCR_SLCKE_OST 0x0200 +#define HD64461_STBCR_SMIAST 0x0100 +#define HD64461_STBCR_SLCDST 0x0080 +#define HD64461_STBCR_SPC0ST 0x0040 +#define HD64461_STBCR_SPC1ST 0x0020 +#define HD64461_STBCR_SAFEST 0x0010 +#define HD64461_STBCR_STM0ST 0x0008 +#define HD64461_STBCR_STM1ST 0x0004 +#define HD64461_STBCR_SIRST 0x0002 +#define HD64461_STBCR_SURTST 0x0001 + +/* System Configuration Register */ +#define HD64461_SYSCR 0xb0000002 + +/* CPU Data Bus Control Register */ +#define HD64461_SCPUCR 0xb0000004 + +/* Base Adress Register */ +#define HD64461_LCDCBAR 0xb0001000 + +/* Line increment adress */ +#define HD64461_LCDCLOR 0xb0001002 + +/* Controls LCD controller */ +#define HD64461_LCDCCR 0xb0001004 + +/* LCCDR control bits */ +#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */ +#define HD64461_LCDCCR_STREQ 0x0100 /* Standby Request */ +#define HD64461_LCDCCR_MOFF 0x0080 /* Memory Off */ +#define HD64461_LCDCCR_REFSEL 0x0040 /* Refresh Select */ +#define HD64461_LCDCCR_EPON 0x0020 /* End Power On */ +#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */ + +/* Controls LCD (1) */ +#define HD64461_LDR1 0xb0001010 +#define HD64461_LDR1_DON 0x01 /* Display On */ +#define HD64461_LDR1_DINV 0x80 /* Display Invert */ + +/* Controls LCD (2) */ +#define HD64461_LDR2 0xb0001012 +#define HD64461_LDHNCR 0xb0001014 /* Number of horizontal characters */ +#define HD64461_LDHNSR 0xb0001016 /* Specify output start position + width of CL1 */ +#define HD64461_LDVNTR 0xb0001018 /* Specify total vertical lines */ +#define HD64461_LDVNDR 0xb000101a /* specify number of display vertical lines */ +#define HD64461_LDVSPR 0xb000101c /* specify vertical synchronization pos and AC nr */ + +/* Controls LCD (3) */ +#define HD64461_LDR3 0xb000101e + +/* Palette Registers */ +#define HD64461_CPTWAR 0xb0001030 /* Color Palette Write Adress Register */ +#define HD64461_CPTWDR 0xb0001032 /* Color Palette Write Data Register */ +#define HD64461_CPTRAR 0xb0001034 /* Color Palette Read Adress Register */ +#define HD64461_CPTRDR 0xb0001036 /* Color Palette Read Data Register */ + +#define HD64461_GRDOR 0xb0001040 /* Display Resolution Offset Register */ +#define HD64461_GRSCR 0xb0001042 /* Solid Color Register */ +#define HD64461_GRCFGR 0xb0001044 /* Accelerator Configuration Register */ + +#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */ +#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */ +#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */ +#define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */ +#define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */ +#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */ + +/* Line Drawing Registers */ +#define HD64461_LNSARH 0xb0001046 /* Line Start Adress Register (H) */ +#define HD64461_LNSARL 0xb0001048 /* Line Start Adress Register (L) */ +#define HD64461_LNAXLR 0xb000104a /* Axis Pixel Length Register */ +#define HD64461_LNDGR 0xb000104c /* Diagonal Register */ +#define HD64461_LNAXR 0xb000104e /* Axial Register */ +#define HD64461_LNERTR 0xb0001050 /* Start Error Term Register */ +#define HD64461_LNMDR 0xb0001052 /* Line Mode Register */ + +/* BitBLT Registers */ +#define HD64461_BBTSSARH 0xb0001054 /* Source Start Adress Register (H) */ +#define HD64461_BBTSSARL 0xb0001056 /* Source Start Adress Register (L) */ +#define HD64461_BBTDSARH 0xb0001058 /* Destination Start Adress Register (H) */ +#define HD64461_BBTDSARL 0xb000105a /* Destination Start Adress Register (L) */ +#define HD64461_BBTDWR 0xb000105c /* Destination Block Width Register */ +#define HD64461_BBTDHR 0xb000105e /* Destination Block Height Register */ +#define HD64461_BBTPARH 0xb0001060 /* Pattern Start Adress Register (H) */ +#define HD64461_BBTPARL 0xb0001062 /* Pattern Start Adress Register (L) */ +#define HD64461_BBTMARH 0xb0001064 /* Mask Start Adress Register (H) */ +#define HD64461_BBTMARL 0xb0001066 /* Mask Start Adress Register (L) */ +#define HD64461_BBTROPR 0xb0001068 /* ROP Register */ +#define HD64461_BBTMDR 0xb000106a /* BitBLT Mode Register */ /* PC Card Controller Registers */ -#define HD64461_PCC0ISR 0x12000 /* socket 0 interface status */ -#define HD64461_PCC0GCR 0x12002 /* socket 0 general control */ -#define HD64461_PCC0CSCR 0x12004 /* socket 0 card status change */ -#define HD64461_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */ -#define HD64461_PCC0SCR 0x12008 /* socket 0 software control */ -#define HD64461_PCC1ISR 0x12010 /* socket 1 interface status */ -#define HD64461_PCC1GCR 0x12012 /* socket 1 general control */ -#define HD64461_PCC1CSCR 0x12014 /* socket 1 card status change */ -#define HD64461_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */ -#define HD64461_PCC1SCR 0x12018 /* socket 1 software control */ +/* Maps to Physical Area 6 */ +#define HD64461_PCC0ISR 0xb0002000 /* socket 0 interface status */ +#define HD64461_PCC0GCR 0xb0002002 /* socket 0 general control */ +#define HD64461_PCC0CSCR 0xb0002004 /* socket 0 card status change */ +#define HD64461_PCC0CSCIER 0xb0002006 /* socket 0 card status change interrupt enable */ +#define HD64461_PCC0SCR 0xb0002008 /* socket 0 software control */ +/* Maps to Physical Area 5 */ +#define HD64461_PCC1ISR 0xb0002010 /* socket 1 interface status */ +#define HD64461_PCC1GCR 0xb0002012 /* socket 1 general control */ +#define HD64461_PCC1CSCR 0xb0002014 /* socket 1 card status change */ +#define HD64461_PCC1CSCIER 0xb0002016 /* socket 1 card status change interrupt enable */ +#define HD64461_PCC1SCR 0xb0002018 /* socket 1 software control */ /* PCC Interface Status Register */ -#define HD64461_PCCISR_READY 0x80 /* card ready */ -#define HD64461_PCCISR_MWP 0x40 /* card write-protected */ -#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ -#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ -#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ -#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ -#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ -#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ - -#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ -#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ -#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ -#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ -#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ -#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ +#define HD64461_PCCISR_READY 0x80 /* card ready */ +#define HD64461_PCCISR_MWP 0x40 /* card write-protected */ +#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ +#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ +#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ +#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ +#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ +#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ + +#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ +#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ +#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ +#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ +#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ +#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ /* PCC General Control Register */ -#define HD64461_PCCGCR_DRVE 0x80 /* output drive */ -#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ -#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ -#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ -#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ -#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ -#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ -#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ +#define HD64461_PCCGCR_DRVE 0x80 /* output drive */ +#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ +#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ +#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ +#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ +#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ +#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ +#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ /* PCC Card Status Change Register */ -#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ -#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ -#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ -#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ -#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ -#define HD64461_PCCCSCR_RC 0x04 /* READY change */ -#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ -#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ +#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ +#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ +#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ +#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ +#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ +#define HD64461_PCCCSCR_RC 0x04 /* READY change */ +#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ +#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ /* PCC Card Status Change Interrupt Enable Register */ -#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ -#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ -#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ -#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ -#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ -#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ - -#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ -#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ -#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ -#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ -#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ +#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ +#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ +#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ +#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ +#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ +#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ + +#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ +#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ +#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ +#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ +#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ /* PCC Software Control Register */ -#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ -#define HD64461_PCCSCR_SWP 0x01 /* write protect */ - -#define HD64461_P0OCR 0x1202a -#define HD64461_P1OCR 0x1202c -#define HD64461_PGCR 0x1202e - -#define HD64461_GPACR 0x14000 -#define HD64461_GPBCR 0x14002 -#define HD64461_GPCCR 0x14004 -#define HD64461_GPDCR 0x14006 -#define HD64461_GPADR 0x14010 -#define HD64461_GPBDR 0x14012 -#define HD64461_GPCDR 0x14014 -#define HD64461_GPDDR 0x14016 -#define HD64461_GPAICR 0x14020 -#define HD64461_GPBICR 0x14022 -#define HD64461_GPCICR 0x14024 -#define HD64461_GPDICR 0x14026 -#define HD64461_GPAISR 0x14040 -#define HD64461_GPBISR 0x14042 -#define HD64461_GPCISR 0x14044 -#define HD64461_GPDISR 0x14046 - -#define HD64461_NIRR 0x15000 -#define HD64461_NIMR 0x15002 - -#define HD64461_IRQBASE OFFCHIP_IRQ_BASE -#define HD64461_IRQ_NUM 16 - -#define HD64461_IRQ_UART (HD64461_IRQBASE+5) -#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6) -#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9) -#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10) -#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11) -#define HD64461_IRQ_AFE (HD64461_IRQBASE+12) -#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13) -#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14) +#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ +#define HD64461_PCCSCR_SWP 0x01 /* write protect */ + +/* PCC0 Output Pins Control Register */ +#define HD64461_P0OCR 0xb000202a + +/* PCC1 Output Pins Control Register */ +#define HD64461_P1OCR 0xb000202c + +/* PC Card General Control Register */ +#define HD64461_PGCR 0xb000202e + +/* Port Control Registers */ +#define HD64461_GPACR 0xb0004000 /* Port A - Handles IRDA/TIMER */ +#define HD64461_GPBCR 0xb0004002 /* Port B - Handles UART */ +#define HD64461_GPCCR 0xb0004004 /* Port C - Handles PCMCIA 1 */ +#define HD64461_GPDCR 0xb0004006 /* Port D - Handles PCMCIA 1 */ + +/* Port Control Data Registers */ +#define HD64461_GPADR 0xb0004010 /* A */ +#define HD64461_GPBDR 0xb0004012 /* B */ +#define HD64461_GPCDR 0xb0004014 /* C */ +#define HD64461_GPDDR 0xb0004016 /* D */ + +/* Interrupt Control Registers */ +#define HD64461_GPAICR 0xb0004020 /* A */ +#define HD64461_GPBICR 0xb0004022 /* B */ +#define HD64461_GPCICR 0xb0004024 /* C */ +#define HD64461_GPDICR 0xb0004026 /* D */ + +/* Interrupt Status Registers */ +#define HD64461_GPAISR 0xb0004040 /* A */ +#define HD64461_GPBISR 0xb0004042 /* B */ +#define HD64461_GPCISR 0xb0004044 /* C */ +#define HD64461_GPDISR 0xb0004046 /* D */ + +/* Interrupt Request Register & Interrupt Mask Register */ +#define HD64461_NIRR 0xb0005000 +#define HD64461_NIMR 0xb0005002 + +#define HD64461_IRQBASE OFFCHIP_IRQ_BASE +#define HD64461_IRQ_NUM 16 + +#define HD64461_IRQ_UART (HD64461_IRQBASE+5) +#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6) +#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9) +#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10) +#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11) +#define HD64461_IRQ_AFE (HD64461_IRQBASE+12) +#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13) +#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14) #define __IO_PREFIX hd64461 #include <asm/io_generic.h> |
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From: Paul M. <le...@li...> - 2007-05-18 02:16:54
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On Thu, May 17, 2007 at 10:42:52PM -0700, Kristoffer Ericson wrote: > Paul, is this patch okey or should it be done with CONFIG_IO_BASE + > value? So everything can be altered through the menuconfig? I havent > seen any other boards using hd64461 though. > It's best to leave it as iobase + regoffset. The fundamental problem here is just the way that the hd64461 is hooked up. Ideally this should be done as an mfd driver, hp6xx can submit platform devices for the peripherals it cares about (relative to hd64461), and the rest just goes away. The I/O wrapping stuff for trapping peripheral access is crap, and the remnants of that is what seems to still be causing some issues. We simply don't want _any_ of this stuff to be stuck in the I/O routines. With platform devices it's less of a problem these days anyways, since there aren't many hardcoded assumptions regarding ISA ports, which much of this was modelled after. Really all of arch/sh/cchips/ needs to migrate to drivers/mfd/ anyways, and that should clean up most of the remaining I/O routine abuse. As you've pointed out, presently there are no hd64465 users, and only 1 hd64461 user. Simple mfd drivers for both will not be too much work, but it's arguable whether there's any point in bothering with hd64465 or not. The boards that were depending on it have been long removed already, and certainly no one is using this part in any new designs. |
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