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From: Kristoffer E. <kri...@ho...> - 2007-03-09 09:40:04
|
Still getting those unaligned access issues. I've setup the setup.c to have the proper cf_ide IO values but getting same error. Just want to get an idea where to look further since Im sure I've done correct. As soon as I get it working, I plan on start removing the PIO mapping so we can get rid of io.c as Paul suggested. Best wishes Kristoffer _________________________________________________________________ FREE pop-up blocking with the new MSN Toolbar - get it now! http://toolbar.msn.click-url.com/go/onm00200415ave/direct/01/ |
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From: Paul M. <le...@li...> - 2007-03-09 10:09:37
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On Fri, Mar 09, 2007 at 09:39:54AM +0000, Kristoffer Ericson wrote: > Still getting those unaligned access issues. I've setup the setup.c to have > the proper cf_ide IO values but getting same error. > Current git should work for this case now that the PG_dcache_dirty bits have been reverted. It is quite interesting that you hit this on SH-3 though, this suggests that it's not actually a fault with the lazy write-back itself, but simply a missing write-back somewhere else that PG_mapped happens to paper over. > As soon as I get it working, I plan on start removing the PIO mapping so we > can get rid of io.c as Paul suggested. > You should be able to do that from the beginning. As long as pata_platform is capable of detecting the device and you're able to mount it, you're in reasonable shape as far as the I/O mappings are concerned. The only potential issue would be the access width, we've seen the ioread8() cause bus locks on early R7780RP-1 boards where it really does need to be a 16-bit access with the 8-bits masked. Looking at the hd64461 code, this should not be a problem. |
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From: Kristoffer E. <kri...@ho...> - 2007-03-12 20:49:15
|
Greetings,
I've synced the changes I had with git and it now compiles without any
issues. At bootup though I receive a kernel panic and "not syncing:
Attempted to kill init!". Im unable to create a bootlog since I have no
serial cable for my jornada.
The only part of the Kernel panic I can see is just the data dump, which
doesnt help you much. (adresses running from 1c80: -> 1fe0).
I believe its somehow related to the PATA driver, but hard to be sure.
My patches for git are these:
diff --git a/arch/sh/boards/hp6xx/setup.c b/arch/sh/boards/hp6xx/setup.c
index b5a9664..abec0e0 100644
--- a/arch/sh/boards/hp6xx/setup.c
+++ b/arch/sh/boards/hp6xx/setup.c
@@ -15,15 +15,52 @@ #include <asm/io.h>
#include <asm/irq.h>
#include <asm/hp6xx.h>
#include <asm/cpu/dac.h>
+#include <linux/platform_device.h>
#define SCPCR 0xa4000116
#define SCPDR 0xa4000136
+static struct resource cf_ide_resources[] = {
+ [0] = {
+ .start = 0x1f0,
+ .end = 0x1f0 + 8,
+ .flags = IORESOURCE_IO,
+ },
+ [1] = {
+ .start = 0x3f6,
+ .end = 0x3f7,
+ .flags = IORESOURCE_IO,
+ },
+ [2] = {
+ .start = 93,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device cf_ide_device = {
+ .name = "pata_platform",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(cf_ide_resources),
+ .resource = cf_ide_resources,
+};
+
+static struct platform_device *hp6xx_devices[] __initdata = {
+
+ &cf_ide_device,
+};
+
+static int __init hp6xx_devices_setup(void)
+{
+ return platform_add_devices(hp6xx_devices,ARRAY_SIZE(hp6xx_devices));
+}
+
static void __init hp6xx_setup(char **cmdline_p)
{
u8 v8;
u16 v;
+ device_initcall(hp6xx_devices_setup);
+
v = inw(HD64461_STBCR);
v |= HD64461_STBCR_SURTST | HD64461_STBCR_SIRST |
HD64461_STBCR_STM1ST | HD64461_STBCR_STM0ST |
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index 06ed060..b56fab8 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -19,6 +19,13 @@ #include <asm/dma.h>
#include <asm/io.h>
#include "dma-sh.h"
+#ifdef CONFIG_CPU_SUBTYPE_SH7709
+ #define DMTE0_IRQ 48
+ #define DMTE1_IRQ 49
+ #define DMTE2_IRQ 50
+ #define DMTE3_IRQ 51
+#endif
+
static int dmte_irq_map[] = {
DMTE0_IRQ,
DMTE1_IRQ,
diff --git a/include/asm-sh/hp6xx.h b/include/asm-sh/hp6xx.h
index f35134c..f628be7 100644
--- a/include/asm-sh/hp6xx.h
+++ b/include/asm-sh/hp6xx.h
@@ -14,6 +14,8 @@ #define HP680_BTN_IRQ IRQ0_IRQ
#define HP680_TS_IRQ IRQ3_IRQ
#define HP680_HD64461_IRQ IRQ4_IRQ
+#define IRQ3_IRQ 35
+
#define DAC_LCD_BRIGHTNESS 0
#define DAC_SPEAKER_VOLUME 1
diff --git a/include/asm-sh/hp6xx.h b/include/asm-sh/hp6xx.h
index f628be7..17787a6 100644
--- a/include/asm-sh/hp6xx.h
+++ b/include/asm-sh/hp6xx.h
@@ -47,6 +47,8 @@ #define ADC_CHANNEL_CHARGE 5
#define HD64461_GPADR_SPEAKER 0x01
#define HD64461_GPADR_PCMCIA0 (0x02|0x08)
+#define TIMER1_IRQ 16
+
#define HD64461_GPBDR_LCDOFF 0x01
#define HD64461_GPBDR_LCD_CONTRAST_MASK 0x78
#define HD64461_GPBDR_LED_RED 0x80
diff --git a/drivers/input/touchscreen/hp680_ts_input.c
b/drivers/input/touchscreen/hp680_ts_input.c
index 2490874..61c1502 100644
--- a/drivers/input/touchscreen/hp680_ts_input.c
+++ b/drivers/input/touchscreen/hp680_ts_input.c
@@ -21,7 +21,7 @@ #define SCPDR 0xa4000136
static void do_softint(void *data);
static struct input_dev *hp680_ts_dev;
-static DECLARE_WORK(work, do_softint, 0);
+static DECLARE_WORK(work, do_softint);
static void do_softint(void *data)
{
diff --git a/drivers/video/backlight/hp680_bl.c
b/drivers/video/backlight/hp680_bl.c
index 0899fcc..b2faf82 100644
--- a/drivers/video/backlight/hp680_bl.c
+++ b/drivers/video/backlight/hp680_bl.c
@@ -125,8 +125,7 @@ static int hp680bl_remove(struct platfor
{
struct backlight_device *bd = platform_get_drvdata(pdev);
+// hp680bl_data.brightness = 0;
+// hp680bl_data.power = 0;
hp680bl_send_intensity(bd);
backlight_device_unregister(bd);
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7709.c
b/arch/sh/kernel/cpu/sh3/setup-sh7709.c
index dc9b211..013e87f 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7709.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7709.c
@@ -55,6 +55,8 @@ __initcall(sh7709_devices_setup);
#define IPRx(A,N) .addr=A, .shift=0*N*-1
#define IPRA(N) IPRx(0xfffffee2UL,N)
#define IPRB(N) IPRx(0xfffffee4UL,N)
+#define IPRC(N) IPRx(0xa0000016UL,N)
+#define IPRD(N) IPRx(0xa0000018UL,N)
#define IPRE(N) IPRx(0xa400001aUL,N)
static struct ipr_data sh7709_ipr_map[] = {
@@ -63,6 +65,12 @@ static struct ipr_data sh7709_ipr_map[]
[22] = { IPRA(3-0), 2 }, /* RTC CUI */
[23 ... 26] = { IPRB(7-4), 3 }, /* SCI */
[27] = { IPRB(15-12), 2 }, /* WDT ITI */
+ [32] = { IPRC(0), 1 }, /* IRQ 0 */
+ [33] = { IPRC(1), 1 }, /* IRQ 1 */
+ [34] = { IPRC(2), 1 }, /* IRQ 2 APM */
+ [35] = { IPRC(3), 1 }, /* IRQ 3 TOUCHSCREEN */
+ [36] = { IPRD(0), 1 }, /* IRQ 4 */
+ [37] = { IPRD(1), 1 }, /* IRQ 5 */
[48 ... 51] = { IPRE(15-12), 7 }, /* DMA */
[52 ... 55] = { IPRE(11-8), 3 }, /* IRDA */
[56 ... 59] = { IPRE(7-4), 3 }, /* SCIF */
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index 29d4fb9..eaf77fe 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -190,7 +190,7 @@ static inline int generic_irq_demux(int
#define irq_canonicalize(irq) (irq)
#define irq_demux(irq) sh_mv.mv_irq_demux(irq)
-
+#define __irq_demux(irq) (irq)
#ifdef CONFIG_4KSTACKS
extern void irq_ctx_init(int cpu);
extern void irq_ctx_exit(int cpu);
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index 8ccf7ae..29d4fb9 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -23,6 +23,40 @@ #elif defined(CONFIG_CPU_SUBTYPE_SH7709)
defined(CONFIG_CPU_SUBTYPE_SH7705)
# define ONCHIP_NR_IRQS 64 // Actually 61
# define PINT_NR_IRQS 16
+
+ #define INTC_IRR0 0xa4000004UL
+ #define INTC_IRR1 0xa4000006UL
+ #define INTC_IRR2 0xa4000008UL
+
+ #define INTC_IPRA 0xfffffee2UL
+ #define INTC_IPRB 0xfffffee4UL
+ #define INTC_IPRD 0xa4000018UL
+
+ #define INTC_INTER 0xa4000014UL
+
+ #define INTC_ICR0 0xfffffee0UL
+ #define INTC_ICR1 0xa4000010UL
+ #define INTC_ICR2 0xa4000012UL
+
+ #define PORT_PACR 0xa4000100UL
+ #define PORT_PBCR 0xa4000102UL
+ #define PORT_PCCR 0xa4000104UL
+ #define PORT_PFCR 0xa400010aUL
+
+ #define PORT_PADR 0xa4000120UL
+ #define PORT_PBDR 0xa4000122UL
+ #define PORT_PCDR 0xa4000124UL
+ #define PORT_PFDR 0xa400012aUL
+
+ #define PINT0_IRQ 40
+ #define PINT8_IRQ 41
+ #define PINT0_IPR_ADDR INTC_IPRD
+ #define PINT8_IPR_ADDR INTC_IPRD
+ #define PINT0_IPR_POS 3
+ #define PINT8_IPR_POS 2
+ #define PINT0_PRIORITY 2
+ #define PINT8_PRIORITY 2
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
# define ONCHIP_NR_IRQS 104
#elif defined(CONFIG_CPU_SUBTYPE_SH7750)
diff --git a/sound/oss/sh_dac_audio.c b/sound/oss/sh_dac_audio.c
index 7ea9acc..b493660 100644
--- a/sound/oss/sh_dac_audio.c
+++ b/sound/oss/sh_dac_audio.c
@@ -104,7 +104,7 @@ static void dac_audio_set_rate(void)
unsigned long interval;
struct clk *clk;
- clk = clk_get("module_clk");
+ clk = clk_get(NULL, "module_clk");
interval = (clk_get_rate(clk) / 4) / rate;
clk_put(clk);
ctrl_outl(interval, TMU1_TCOR);
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From: Kristoffer E. <kri...@ho...> - 2007-03-12 21:31:11
|
Greetings,
Managed to get someone to send me a bootlog, looks like it really is the
PATA causing the issue.
1.
DMA: Registering DMA API.
2.
DMA: Registering sh_dmac handler (4 channels).
3.
NET: Registered protocol family 2
4.
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
5.
TCP established hash table entries: 1024 (order: 1, 8192 bytes)
6.
TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
7.
TCP: Hash tables configured (established 1024 bind 1024)
8.
TCP reno registered
9.
HD64461 configured at 0xb0000000 on irq 36(mapped into 80 to 95)
10.
HD64461: enabling PCMCIA devices
11.
io scheduler noop registered
12.
io scheduler anticipatory registered (default)
13.
io scheduler deadline registered
14.
io scheduler cfq registered
15.
Console: switching to colour frame buffer device 80x30
16.
fb0: Hitachi HD64461 frame buffer device
17.
SuperH SCI(F) driver initialized
18.
sh-sci: ttySC0 at MMIO 0xfffffe80 (irq = 25) is a sci
19.
sh-sci: ttySC1 at MMIO 0xa4000150 (irq = 59) is a scif
20.
loop: loaded (max 8 devices)
21.
SCSI Media Changer driver v0.25
22.
ata1: PATA max PIO0 cmd 0x000001f0 ctl 0x000003f6 bmdma 0x00000000 irq
93
23.
Unable to handle kernel NULL pointer dereference at virtual address
000003f6
24.
pc = 8d006bb2
25.
*pde = 00000000
26.
Oops: 0001 [#1]
27.
Modules linked in:
28.
29.
Pid : 1, Comm: swapper
30.
PC is at generic_writeb+0x2/0x10
31.
PC : 8d006bb2 SP : 8d2c5c30 SR : 400001f0 TEA : 000003f6 Not
tainted
32.
R0 : 0000000a R1 : 8d006bb0 R2 : 8d3b82f4 R3 : 00000001
33.
R4 : 0000000a R5 : 000003f6 R6 : ffffffff R7 : 000000f0
34.
R8 : 8d3b82c8 R9 : 8d2c5c38 R10 : 8d3b8308 R11 : 00000000
35.
R12 : 8d3aff1c R13 : 8d2c5c8c R14 : 8d22aa64
36.
MACH: 00000060 MACL: 00000000 GBR : 00000000 PR : 8d12fcf2
37.
38.
Call trace:
39.
[<8d1301c4>] __ata_port_freeze+0x34/0x70
40.
[<8d1305c2>] ata_eh_freeze_port+0x32/0x70
41.
[<8d12b658>] ata_device_add+0x1f8/0x4a0
42.
[<8d10c286>] devres_alloc+0x16/0x50
43.
[<8d132e4c>] pata_platform_probe+0x15c/0x280
44.
[<8d0db230>] devm_ioport_map+0x0/0x70
45.
[<8d10ab2e>] platform_drv_probe+0xe/0x20
46.
[<8d108714>] really_probe+0xd4/0x190
47.
[<8d108886>] driver_probe_device+0x96/0xe0
48.
[<8d108ac6>] __driver_attach+0xf6/0x160
49.
[<8d1076d8>] bus_for_each_dev+0x48/0x90
50.
[<8d1089d0>] __driver_attach+0x0/0x160
51.
[<8d107660>] next_device+0x0/0x30
52.
[<8d107e5c>] bus_add_driver+0x4c/0x1a0
53.
[<8d240a04>] init+0x64/0x1e0
54.
[<8d003004>] kernel_thread_helper+0x4/0x10
55.
[<8d2409a0>] init+0x0/0x1e0
56.
[<8d003000>] kernel_thread_helper+0x0/0x10
57.
58.
59.
Process: swapper (pid: 1, stack limit = 8d2c4001)
60.
Stack: (0x8d2c5c30 to 0x8d2c6000)
61.
62.
5c20: 8d1301c4 8d3b82c8 8d1305c2
00000000
63.
5c40: 8d12b658 8d3b82c8 00000000 0000005d 8d2c5e88 8d2c5e48 00000001
00000050
64.
5c60: 8d10c286 8d3aff40 8d3aff1c 8d132e4c 00000000 00000000 8d22aa64
8d22aa5c
65.
5c80: 8d22abd8 8d2c5ccc 8d0db230 8d2c5c8c 8d2c5c8c 8d22aa64 8d235838
8d23579c
66.
67.
5ca0: 000001f0 000001f0 000001f1 000001f1 000001f2 000001f3 000001f4
000001f5
68.
5cc0: 000001f6 000001f7 000001f7 000003f6 000003f6 00000000 00000000
00000000
69.
5ce0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000
70.
5d00: 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000
71.
5d20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000
72.
5d40: 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000
73.
5d60: 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000
74.
75.
5d80: 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000
76.
5da0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000
77.
5dc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000
78.
5de0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000
79.
80.
5e00: 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000
81.
5e20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000
82.
5e40: 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000
83.
5e60: 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000
84.
85.
5e80: 00000001 00000000 00000001 00000000 00000000 0000005d 00000000
00000000
86.
5ea0: 00000011 00000000 00000000 00000000 00000000 8d10ab2e 8d25ded8
00000000
87.
5ec0: 8d235700 8d3a19a0 8d22aa64 8d22ab20 8d108714 8d108886 8d24e4b4
00000000
88.
5ee0: 00000000 8d22aa64 8d3a19a0 8d23577c 8d108ac6 00000000 8d235700
8d235700
89.
90.
5f00: 8d22aaa4 8d22aa64 8d1076d8 8d1089d0 8d107660 00000000 8d233a78
8d233a78
91.
5f20: 8d22aaac 8d107e5c 8d233978 8d235714 8d235700 00000000 8d240a04
00000000
92.
5f40: 8d24e4b4 00000000 8d24c864 00000000 8d24e454 8d2c4000 b7b5172f
6b0efe54
93.
5f60: 811bf03b b7da224d 9cbe7a22 65638d08 54bd1cdd ce0970c4 b45f0458
43f881df
94.
5f80: 00000001 8d003004 00000000 00000000 00000000 00000000 00000000
00000000
95.
5fa0: 00000000 00000000 00000000 00000000 00000000 8d2409a0 00000000
00000000
96.
5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000
8d2c5fa0
97.
98.
5fe0: 8d003000 00000000 40000000 00000000 00000000 00000000 00000000
059c02bf
99.
Kernel panic - not syncing: Attempted to kill init!
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From: Paul M. <le...@li...> - 2007-03-12 23:40:01
|
On Mon, Mar 12, 2007 at 08:49:00PM +0000, Kristoffer Ericson wrote:
> The only part of the Kernel panic I can see is just the data dump, which
> doesnt help you much. (adresses running from 1c80: -> 1fe0).
>
> I believe its somehow related to the PATA driver, but hard to be sure.
>
Yes, you should be using the MMIO address, the problem is that you're
using the PIO address and it's completely unhandled by your I/O routines.
> +static struct resource cf_ide_resources[] = {
> + [0] = {
> + .start = 0x1f0,
> + .end = 0x1f0 + 8,
> + .flags = IORESOURCE_IO,
> + },
> + [1] = {
> + .start = 0x3f6,
> + .end = 0x3f7,
> + .flags = IORESOURCE_IO,
> + },
So change these to the MMIO address, and switch to IORESOURCE_MEM.
> +static int __init hp6xx_devices_setup(void)
> +{
> + return platform_add_devices(hp6xx_devices,ARRAY_SIZE(hp6xx_devices));
> +}
> +
> static void __init hp6xx_setup(char **cmdline_p)
> {
> u8 v8;
> u16 v;
>
> + device_initcall(hp6xx_devices_setup);
> +
Move this after hp6xx_devices_setup().
> diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
> index 29d4fb9..eaf77fe 100644
> --- a/include/asm-sh/irq.h
> +++ b/include/asm-sh/irq.h
> @@ -190,7 +190,7 @@ static inline int generic_irq_demux(int
>
> #define irq_canonicalize(irq) (irq)
> #define irq_demux(irq) sh_mv.mv_irq_demux(irq)
> -
> +#define __irq_demux(irq) (irq)
> #ifdef CONFIG_4KSTACKS
> extern void irq_ctx_init(int cpu);
> extern void irq_ctx_exit(int cpu);
>
What is using this?
|
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From: Kristoffer E. <kri...@ho...> - 2007-03-13 20:47:57
|
Greetings,
I've changed the code to use MMIO instead.
.start 0xb5000000 + 0x1f0
.end 0xb5000000 + 0x1f7
and
.start 0xb50001fe
.end 0xb50001ff
with MEM instead of IO.
It now detects the ATA1 properly, but goes into an endles loop with :
ata1: soft resetting port
ata1.00 : configured for PIO <--- ???
ata1 : EH complete
ata1.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x2 frozen
ata1.00: cmd 20/00:08:00:00:00/00:00:00:00:00/e0 tag 0 cdb 0x0 data 4096 in
res 40/00:00:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout)
ata1: soft resetting port
Suggestions?
Best wishes
Kristoffer
>From: Paul Mundt <le...@li...>
>To: Kristoffer Ericson <kri...@ho...>
>CC: lin...@li...
>Subject: Re: HP6xx kernel panic at bootup
>Date: Tue, 13 Mar 2007 08:37:07 +0900
>
>On Mon, Mar 12, 2007 at 08:49:00PM +0000, Kristoffer Ericson wrote:
> > The only part of the Kernel panic I can see is just the data dump, which
> > doesnt help you much. (adresses running from 1c80: -> 1fe0).
> >
> > I believe its somehow related to the PATA driver, but hard to be sure.
> >
>Yes, you should be using the MMIO address, the problem is that you're
>using the PIO address and it's completely unhandled by your I/O routines.
>
> > +static struct resource cf_ide_resources[] = {
> > + [0] = {
> > + .start = 0x1f0,
> > + .end = 0x1f0 + 8,
> > + .flags = IORESOURCE_IO,
> > + },
> > + [1] = {
> > + .start = 0x3f6,
> > + .end = 0x3f7,
> > + .flags = IORESOURCE_IO,
> > + },
>
>So change these to the MMIO address, and switch to IORESOURCE_MEM.
>
> > +static int __init hp6xx_devices_setup(void)
> > +{
> > + return platform_add_devices(hp6xx_devices,ARRAY_SIZE(hp6xx_devices));
> > +}
> > +
> > static void __init hp6xx_setup(char **cmdline_p)
> > {
> > u8 v8;
> > u16 v;
> >
> > + device_initcall(hp6xx_devices_setup);
> > +
>
>Move this after hp6xx_devices_setup().
>
> > diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
> > index 29d4fb9..eaf77fe 100644
> > --- a/include/asm-sh/irq.h
> > +++ b/include/asm-sh/irq.h
> > @@ -190,7 +190,7 @@ static inline int generic_irq_demux(int
> >
> > #define irq_canonicalize(irq) (irq)
> > #define irq_demux(irq) sh_mv.mv_irq_demux(irq)
> > -
> > +#define __irq_demux(irq) (irq)
> > #ifdef CONFIG_4KSTACKS
> > extern void irq_ctx_init(int cpu);
> > extern void irq_ctx_exit(int cpu);
> >
>What is using this?
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From: Kristoffer E. <kri...@ho...> - 2007-03-15 22:31:07
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Greetings, In order to get a more proper enviroment I started removing the PIO stuff from io.c and adding correct adresses into hd64461.h. Im still getting exactly same error though. Some please take a look at this diff and tell me what im doing wrong. --- ../linux-2.6/include/asm-sh/hd64461.h 2006-09-27 19:23:52.000000000 +0000 +++ include/asm-sh/hd64461.h 2007-03-15 23:27:03.000000000 +0000 @@ -18,8 +18,9 @@ #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) #define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) -#define HD64461_STBCR 0x10000 -#define HD64461_STBCR_CKIO_STBY 0x2000 +/* if PORT < 0xf000 then ADDR = 0xa0000000 + PORT */ +#define HD64461_STBCR (CONFIG_HD64461_IOBASE + 0x10000 - 0x10000) +#define HD64461_STBCR_CKIO_STBY 0x2000 #define HD64461_STBCR_SAFECKE_IST 0x1000 #define HD64461_STBCR_SLCKE_IST 0x0800 #define HD64461_STBCR_SAFECKE_OST 0x0400 @@ -31,15 +32,18 @@ #define HD64461_STBCR_SAFEST 0x0010 #define HD64461_STBCR_STM0ST 0x0008 #define HD64461_STBCR_STM1ST 0x0004 -#define HD64461_STBCR_SIRST 0x0002 +#define HD64461_STBCR_SIRST 0x0002 #define HD64461_STBCR_SURTST 0x0001 -#define HD64461_SYSCR 0x10002 -#define HD64461_SCPUCR 0x10004 +/* if PORT < 0x20000 then ADDR = CONFIG_HD64461_IOBASE + PORT - 0x10000 */ +#define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x10002 - 0x10000) +#define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x10004 - 0x10000) +#define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x11000 - 0x10000) +#define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x11002 - 0x10000) +#define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x11004 - 0x10000) -#define HD64461_LCDCBAR 0x11000 -#define HD64461_LCDCLOR 0x11002 -#define HD64461_LCDCCR 0x11004 + +/* if PORT < 0xf000 then ADDR = 0xa0000000 + PORT */ #define HD64461_LCDCCR_STBACK 0x0400 #define HD64461_LCDCCR_STREQ 0x0100 #define HD64461_LCDCCR_MOFF 0x0080 @@ -47,142 +51,150 @@ #define HD64461_LCDCCR_EPON 0x0020 #define HD64461_LCDCCR_SPON 0x0010 -#define HD64461_LDR1 0x11010 +/* if PORT < 0x20000 then ADDR = CONFIG_HD64461_IOBASE + PORT - 0x10000 */ +#define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x11010 - 0x10000) + +/* if PORT < 0xf000 then ADDR = 0xa0000000 + PORT */ #define HD64461_LDR1_DON 0x01 #define HD64461_LDR1_DINV 0x80 -#define HD64461_LDR2 0x11012 -#define HD64461_LDHNCR 0x11014 -#define HD64461_LDHNSR 0x11016 -#define HD64461_LDVNTR 0x11018 -#define HD64461_LDVNDR 0x1101a -#define HD64461_LDVSPR 0x1101c -#define HD64461_LDR3 0x1101e - -#define HD64461_CPTWAR 0x11030 -#define HD64461_CPTWDR 0x11032 -#define HD64461_CPTRAR 0x11034 -#define HD64461_CPTRDR 0x11036 - -#define HD64461_GRDOR 0x11040 -#define HD64461_GRSCR 0x11042 -#define HD64461_GRCFGR 0x11044 +/* if PORT < 0x20000 then ADDR = CONFIG_HD64461_IOBASE + PORT - 0x10000 */ +#define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x11012 - 0x10000) +#define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x11014 - 0x10000) +#define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x11016 - 0x10000) +#define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x11018 - 0x10000) +#define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x1101a - 0x10000) +#define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x1101c - 0x10000) +#define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x1101e - 0x10000) + +#define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x11030 - 0x10000) +#define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x11032 - 0x10000) +#define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x11034 - 0x10000) +#define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x11036 - 0x10000) + +#define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x11040 - 0x10000) +#define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x11042 - 0x10000) +#define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x11044 - 0x10000) + #define HD64461_GRCFGR_ACCSTATUS 0x10 #define HD64461_GRCFGR_ACCRESET 0x08 -#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 -#define HD64461_GRCFGR_ACCSTART_LINE 0x04 +#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 +#define HD64461_GRCFGR_ACCSTART_LINE 0x04 #define HD64461_GRCFGR_COLORDEPTH16 0x01 -#define HD64461_LNSARH 0x11046 -#define HD64461_LNSARL 0x11048 -#define HD64461_LNAXLR 0x1104a -#define HD64461_LNDGR 0x1104c -#define HD64461_LNAXR 0x1104e -#define HD64461_LNERTR 0x11050 -#define HD64461_LNMDR 0x11052 -#define HD64461_BBTSSARH 0x11054 -#define HD64461_BBTSSARL 0x11056 -#define HD64461_BBTDSARH 0x11058 -#define HD64461_BBTDSARL 0x1105a -#define HD64461_BBTDWR 0x1105c -#define HD64461_BBTDHR 0x1105e -#define HD64461_BBTPARH 0x11060 -#define HD64461_BBTPARL 0x11062 -#define HD64461_BBTMARH 0x11064 -#define HD64461_BBTMARL 0x11066 -#define HD64461_BBTROPR 0x11068 -#define HD64461_BBTMDR 0x1106a +/* if PORT < 0x20000 then CONFIG_HD64461_IOBASE + PORT - 0x10000 */ +#define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x11046 - 0x10000) +#define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x11048 - 0x10000) +#define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x1104a - 0x10000) +#define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x1104c - 0x10000) +#define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x1104e - 0x10000) +#define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x11050 - 0x10000) +#define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x11052 - 0x10000) +#define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x11054 - 0x10000) +#define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x11056 - 0x10000) +#define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x11058 - 0x10000) +#define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x1105a - 0x10000) +#define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x1105c - 0x10000) +#define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x1105e - 0x10000) +#define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x11060 - 0x10000) +#define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x11062 - 0x10000) +#define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x11064 - 0x10000) +#define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x11066 - 0x10000) +#define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x11068 - 0x10000) +#define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x1106a - 0x10000) +/* These must be like this, otherwise the Jornada will not boot! */ /* PC Card Controller Registers */ -#define HD64461_PCC0ISR 0x12000 /* socket 0 interface status */ -#define HD64461_PCC0GCR 0x12002 /* socket 0 general control */ -#define HD64461_PCC0CSCR 0x12004 /* socket 0 card status change */ -#define HD64461_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */ -#define HD64461_PCC0SCR 0x12008 /* socket 0 software control */ -#define HD64461_PCC1ISR 0x12010 /* socket 1 interface status */ -#define HD64461_PCC1GCR 0x12012 /* socket 1 general control */ -#define HD64461_PCC1CSCR 0x12014 /* socket 1 card status change */ -#define HD64461_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */ -#define HD64461_PCC1SCR 0x12018 /* socket 1 software control */ +#define HD64461_PCC0ISR (0xb8000000 + 0x12000 - 0x10000) /* socket 0 interface status */ +#define HD64461_PCC0GCR (0xb8000000 + 0x12002 - 0x10000) /* socket 0 general control */ +#define HD64461_PCC0CSCR (0xb8000000 + 0x12004 - 0x10000) /* socket 0 card status change */ +#define HD64461_PCC0CSCIER (0xb8000000 + 0x12006 - 0x10000) /* socket 0 card status change interrupt enable */ +#define HD64461_PCC0SCR (0xb8000000 + 0x12008 - 0x10000) /* socket 0 software control */ +#define HD64461_PCC1ISR (0xb4000000 + 0x12010 - 0x10000) /* socket 1 interface status */ +#define HD64461_PCC1GCR (0xb4000000 + 0x12012 - 0x10000) /* socket 1 general control */ +#define HD64461_PCC1CSCR (0xb4000000 + 0x12014 - 0x10000) /* socket 1 card status change */ +#define HD64461_PCC1CSCIER (0xb4000000 + 0x12016 - 0x10000) /* socket 1 card status change interrupt enable */ +#define HD64461_PCC1SCR (0xb4000000 + 0x12018 - 0x10000) /* socket 1 software control */ /* PCC Interface Status Register */ -#define HD64461_PCCISR_READY 0x80 /* card ready */ -#define HD64461_PCCISR_MWP 0x40 /* card write-protected */ -#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ -#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ -#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ -#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ -#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ -#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ - -#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ -#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ -#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ -#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ -#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ -#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ +#define HD64461_PCCISR_READY 0x80 /* card ready */ +#define HD64461_PCCISR_MWP 0x40 /* card write-protected */ +#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ +#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ +#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ +#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ +#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ +#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ + +#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ +#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ +#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ +#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ +#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ +#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ /* PCC General Control Register */ -#define HD64461_PCCGCR_DRVE 0x80 /* output drive */ -#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ -#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ -#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ -#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ -#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ -#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ -#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ +#define HD64461_PCCGCR_DRVE 0x80 /* output drive */ +#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ +#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ +#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ +#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ +#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ +#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ +#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ /* PCC Card Status Change Register */ -#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ -#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ -#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ -#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ -#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ -#define HD64461_PCCCSCR_RC 0x04 /* READY change */ -#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ -#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ +#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ +#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ +#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ +#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ +#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ +#define HD64461_PCCCSCR_RC 0x04 /* READY change */ +#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ +#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ /* PCC Card Status Change Interrupt Enable Register */ -#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ -#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ -#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ -#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ -#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ -#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ - -#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ -#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ -#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ -#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ -#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ +#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ +#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ +#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ +#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ +#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ +#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ + +#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ +#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ +#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ +#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ +#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ /* PCC Software Control Register */ -#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ -#define HD64461_PCCSCR_SWP 0x01 /* write protect */ - -#define HD64461_P0OCR 0x1202a -#define HD64461_P1OCR 0x1202c -#define HD64461_PGCR 0x1202e - -#define HD64461_GPACR 0x14000 -#define HD64461_GPBCR 0x14002 -#define HD64461_GPCCR 0x14004 -#define HD64461_GPDCR 0x14006 -#define HD64461_GPADR 0x14010 -#define HD64461_GPBDR 0x14012 -#define HD64461_GPCDR 0x14014 -#define HD64461_GPDDR 0x14016 -#define HD64461_GPAICR 0x14020 -#define HD64461_GPBICR 0x14022 -#define HD64461_GPCICR 0x14024 -#define HD64461_GPDICR 0x14026 -#define HD64461_GPAISR 0x14040 -#define HD64461_GPBISR 0x14042 -#define HD64461_GPCISR 0x14044 -#define HD64461_GPDISR 0x14046 +#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ +#define HD64461_PCCSCR_SWP 0x01 /* write protect */ -#define HD64461_NIRR 0x15000 -#define HD64461_NIMR 0x15002 +#define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x1202a - 0x10000) +#define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x1202c - 0x10000) +#define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x1202e - 0x10000) + +#define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x14000 - 0x10000) +#define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x14002 - 0x10000) +#define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x14004 - 0x10000) +#define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x14006 - 0x10000) +#define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x14010 - 0x10000) +#define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x14012 - 0x10000) +#define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x14014 - 0x10000) +#define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x14016 - 0x10000) +#define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x14020 - 0x10000) +#define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x14022 - 0x10000) +#define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x14024 - 0x10000) +#define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x14026 - 0x10000) +#define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x14040 - 0x10000) +#define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x14042 - 0x10000) +#define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x14044 - 0x10000) +#define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x14046 - 0x10000) + +/* if PORT < 20000 then ADDR = CONFIG_HD64461_IOBASE + 0x15000 - 0x10000 */ +#define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x15000 - 0x10000) +#define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x15002 - 0x10000) #define HD64461_IRQBASE OFFCHIP_IRQ_BASE #define HD64461_IRQ_NUM 16 _________________________________________________________________ Don't just search. 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From: Kristoffer E. <kri...@ho...> - 2007-03-19 20:01:46
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Any thoughts paul? I've rewritten the PIO->MMIO stuff which makes io.c more or less obselete, but still get exactly same error at bootup. It fails to detect the partitions on the SDA card (although its detected properly) and gives frozen/timeout errors. _________________________________________________________________ Express yourself instantly with MSN Messenger! Download today it's FREE! http://messenger.msn.click-url.com/go/onm00200471ave/direct/01/ |
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From: Kristoffer E. <kri...@ho...> - 2007-03-21 22:33:28
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Greetings,
I've made io.c more or less obselete. And just using the generic mv_ it
works like it did before. No luck booting from CF card though, still getting
frozen/timeouts. It feels like its unable to communicate with the CF card
aside from obtaining id,size information. The first error states that its
unable to detect partitions.
Getting this when __irq_demux isnt defined in irq.h
arch/sh/cchips/hd6446x/hd64461/built-in.o(.text+0x22c): In function
`hd64461_irq_demux':
: undefined reference to `__irq_demux'
At compile I get this message
arch/sh/cchips/hd6446x/hd64461/setup.c: In function `hd64461_irq_demux':
arch/sh/cchips/hd6446x/hd64461/setup.c:125: warning: implicit declaration of
function `__irq_demux'
which in turn comes from this line.
return __irq_demux(irq);
Replacing with hd64461_irq_demux(irq) works just fine.
Best wishes
Kristoffer
>From: Paul Mundt <le...@li...>
>To: Kristoffer Ericson <kri...@ho...>
>CC: lin...@li...
>Subject: Re: HP6xx kernel panic at bootup
>Date: Tue, 13 Mar 2007 08:37:07 +0900
>
>On Mon, Mar 12, 2007 at 08:49:00PM +0000, Kristoffer Ericson wrote:
> > The only part of the Kernel panic I can see is just the data dump, which
> > doesnt help you much. (adresses running from 1c80: -> 1fe0).
> >
> > I believe its somehow related to the PATA driver, but hard to be sure.
> >
>Yes, you should be using the MMIO address, the problem is that you're
>using the PIO address and it's completely unhandled by your I/O routines.
>
> > +static struct resource cf_ide_resources[] = {
> > + [0] = {
> > + .start = 0x1f0,
> > + .end = 0x1f0 + 8,
> > + .flags = IORESOURCE_IO,
> > + },
> > + [1] = {
> > + .start = 0x3f6,
> > + .end = 0x3f7,
> > + .flags = IORESOURCE_IO,
> > + },
>
>So change these to the MMIO address, and switch to IORESOURCE_MEM.
>
> > +static int __init hp6xx_devices_setup(void)
> > +{
> > + return platform_add_devices(hp6xx_devices,ARRAY_SIZE(hp6xx_devices));
> > +}
> > +
> > static void __init hp6xx_setup(char **cmdline_p)
> > {
> > u8 v8;
> > u16 v;
> >
> > + device_initcall(hp6xx_devices_setup);
> > +
>
>Move this after hp6xx_devices_setup().
>
> > diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
> > index 29d4fb9..eaf77fe 100644
> > --- a/include/asm-sh/irq.h
> > +++ b/include/asm-sh/irq.h
> > @@ -190,7 +190,7 @@ static inline int generic_irq_demux(int
> >
> > #define irq_canonicalize(irq) (irq)
> > #define irq_demux(irq) sh_mv.mv_irq_demux(irq)
> > -
> > +#define __irq_demux(irq) (irq)
> > #ifdef CONFIG_4KSTACKS
> > extern void irq_ctx_init(int cpu);
> > extern void irq_ctx_exit(int cpu);
> >
>What is using this?
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From: Kristoffer E. <kri...@ho...> - 2007-03-22 22:32:22
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Greetings, After Pauls suggestion to look for IRQ problems I finally found the error. I had put in the wrong IPRC/IPRD codes. Instead of 0xa400.... I had 0xa000... That caused the strange errors. It boots fine now. Although it works perfectly fine on the hp680/hp690 now, Users with hp620 are having strange issues. Before the move to Pata platform they had "Lost interrupt" errors, now they instead have: <rafa> a kernel panic again. The output about ata is: <rafa> scsi0 : pata_platform <rafa> ata1.00: qc timeout (cmd 0x91) <rafa> ata1.00: failed to IDENTIFY (INIT_DEV_PARAMS failed, err_mask=0x4) <Kristoffer> Oki, so it doesnt show any partitions <rafa> again the last 2 messages <rafa> no <rafa> after that. ata1.00: limiting speed to UDMA7:PIO5 <rafa> again the timeout error .. and after that the booting continues. Finally <rafa> no i think :( <rafa> the first message about ata was: <rafa> ata1: PATA max PIO0 cmd 0xb50001f0 ctl 0xb50001fe bmdma 0x00000000 irq 93 <Kristoffer> looks correct <rafa> tree time outs, and a "limiting speed" message <rafa> after that any thing appears about the CF <rafa> onle keyboard, net <rafa> kernel panic with a unknown-block(0,0) <rafa> onle=only Best wishes Kristoffer _________________________________________________________________ FREE pop-up blocking with the new MSN Toolbar - get it now! http://toolbar.msn.click-url.com/go/onm00200415ave/direct/01/ |
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