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From: kogiidena <kog...@eg...> - 2007-03-17 01:23:47
|
Hi Paul-san and All I made the patch of landisk. (1)The push_switch framework was used. (2)landisk_pwc.c was divided into psw.c and gio.c. (3)pata_platform was supported in USL-5P. (4)irq.c was rewritten. (5)io.c was replaced with io_generic.c. (6)The IO address of PCI was changed in relation to (5). (7)To avoid the build error, the RTC code was deleted from setup.c. The RS5C313 code of Iwamatsu-san can be used. (8)LED(heartbeat) code was deleted from setup.c. driver/leds is used. Please delete io.c rtc.c landisk_pwb.c in arch/sh/board/landisk. kogiidena ----------------------------------------------- diff -urpN OLD/arch/sh/boards/landisk/Makefile NEW/arch/sh/boards/landisk/Makefile --- OLD/arch/sh/boards/landisk/Makefile 2007-03-16 09:20:01.000000000 +0900 +++ NEW/arch/sh/boards/landisk/Makefile 2007-03-17 09:09:29.000000000 +0900 @@ -2,4 +2,4 @@ # Makefile for I-O DATA DEVICE, INC. "LANDISK Series" # -obj-y := setup.o io.o irq.o rtc.o landisk_pwb.o +obj-y := setup.o irq.o psw.o gio.o diff -urpN OLD/arch/sh/boards/landisk/gio.c NEW/arch/sh/boards/landisk/gio.c --- OLD/arch/sh/boards/landisk/gio.c 1970-01-01 09:00:00.000000000 +0900 +++ NEW/arch/sh/boards/landisk/gio.c 2007-03-17 09:09:29.000000000 +0900 @@ -0,0 +1,167 @@ +/* + * arch/sh/boards/landisk/gio.c - driver for landisk + * + * This driver will also support the I-O DATA Device, Inc. LANDISK Board. + * LANDISK and USL-5P Button, LED and GIO driver drive function. + * + * Copylight (C) 2006 kogiidena + * Copylight (C) 2002 Atom Create Engineering Co., Ltd. * + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ +#include <linux/module.h> +#include <linux/init.h> +#include <linux/kdev_t.h> +#include <linux/cdev.h> +#include <linux/fs.h> +#include <asm/io.h> +#include <asm/uaccess.h> +#include <asm/landisk/gio.h> +#include <asm/landisk/iodata_landisk.h> + +#define DEVCOUNT 4 +#define GIO_MINOR 2 /* GIO minor no. */ + +static dev_t dev; +static struct cdev *cdev_p; +static int openCnt; + +static int gio_open(struct inode *inode, struct file *filp) +{ + int minor; + + minor = MINOR(inode->i_rdev); + if (minor < DEVCOUNT) { + if (openCnt > 0) { + return -EALREADY; + } else { + openCnt++; + return 0; + } + } + return -ENOENT; +} + +static int gio_close(struct inode *inode, struct file *filp) +{ + int minor; + + minor = MINOR(inode->i_rdev); + if (minor < DEVCOUNT) { + openCnt--; + } + return 0; +} + +static int gio_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + unsigned int data; + static unsigned int addr = 0; + + if (cmd & 0x01) { /* write */ + if (copy_from_user(&data, (int *)arg, sizeof(int))) { + return -EFAULT; + } + } + + switch (cmd) { + case GIODRV_IOCSGIOSETADDR: /* addres set */ + addr = data; + break; + + case GIODRV_IOCSGIODATA1: /* write byte */ + ctrl_outb((unsigned char)(0x0ff & data), addr); + break; + + case GIODRV_IOCSGIODATA2: /* write word */ + if (addr & 0x01) { + return -EFAULT; + } + ctrl_outw((unsigned short int)(0x0ffff & data), addr); + break; + + case GIODRV_IOCSGIODATA4: /* write long */ + if (addr & 0x03) { + return -EFAULT; + } + ctrl_outl(data, addr); + break; + + case GIODRV_IOCGGIODATA1: /* read byte */ + data = ctrl_inb(addr); + break; + + case GIODRV_IOCGGIODATA2: /* read word */ + if (addr & 0x01) { + return -EFAULT; + } + data = ctrl_inw(addr); + break; + + case GIODRV_IOCGGIODATA4: /* read long */ + if (addr & 0x03) { + return -EFAULT; + } + data = ctrl_inl(addr); + break; + default: + return -EFAULT; + break; + } + + if ((cmd & 0x01) == 0) { /* read */ + if (copy_to_user((int *)arg, &data, sizeof(int))) { + return -EFAULT; + } + } + return 0; +} + +static struct file_operations gio_fops = { + .owner = THIS_MODULE, + .open = gio_open, /* open */ + .release = gio_close, /* release */ + .ioctl = gio_ioctl, /* ioctl */ +}; + +static int __init gio_init(void) +{ + int error; + + printk(KERN_INFO "gio: driver initialized\n"); + + openCnt = 0; + + if ((error = alloc_chrdev_region(&dev, 0, DEVCOUNT, "gio")) < 0) { + printk(KERN_ERR + "gio: Couldn't alloc_chrdev_region, error=%d\n", + error); + return 1; + } + + cdev_p = cdev_alloc(); + cdev_p->ops = &gio_fops; + error = cdev_add(cdev_p, dev, DEVCOUNT); + if (error) { + printk(KERN_ERR + "gio: Couldn't cdev_add, error=%d\n", error); + return 1; + } + + return 0; +} + +static void __exit gio_exit(void) +{ + cdev_del(cdev_p); + unregister_chrdev_region(dev, DEVCOUNT); +} + +module_init(gio_init); +module_exit(gio_exit); + +MODULE_LICENSE("GPL"); diff -urpN OLD/arch/sh/boards/landisk/irq.c NEW/arch/sh/boards/landisk/irq.c --- OLD/arch/sh/boards/landisk/irq.c 2007-03-16 09:20:01.000000000 +0900 +++ NEW/arch/sh/boards/landisk/irq.c 2007-03-17 09:09:29.000000000 +0900 @@ -1,18 +1,16 @@ /* * arch/sh/boards/landisk/irq.c * + * I-O DATA Device, Inc. LANDISK Support + * + * Copyright (C) 2005-2007 kogiidena + * * Copyright (C) 2001 Ian da Silva, Jeremy Siegel * Based largely on io_se.c. * - * I/O routine for I-O Data Device, Inc. LANDISK. - * - * Initial version only to support LAN access; some - * placeholder code from io_landisk.c left in with the - * expectation of later SuperIO and PCMCIA access. - */ -/* - * modified by kogiidena - * 2005.03.03 + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. */ #include <linux/init.h> #include <linux/irq.h> @@ -20,71 +18,27 @@ #include <linux/io.h> #include <asm/landisk/iodata_landisk.h> -static void enable_landisk_irq(unsigned int irq); -static void disable_landisk_irq(unsigned int irq); - -/* shutdown is same as "disable" */ -#define shutdown_landisk_irq disable_landisk_irq - -static void ack_landisk_irq(unsigned int irq); -static void end_landisk_irq(unsigned int irq); - -static unsigned int startup_landisk_irq(unsigned int irq) -{ - enable_landisk_irq(irq); - return 0; /* never anything pending */ -} - static void disable_landisk_irq(unsigned int irq) { - unsigned char val; unsigned char mask = 0xff ^ (0x01 << (irq - 5)); - /* Set the priority in IPR to 0 */ - val = ctrl_inb(PA_IMASK); - val &= mask; - ctrl_outb(val, PA_IMASK); + ctrl_outb(ctrl_inb(PA_IMASK) & mask, PA_IMASK); } static void enable_landisk_irq(unsigned int irq) { - unsigned char val; unsigned char value = (0x01 << (irq - 5)); - /* Set priority in IPR back to original value */ - val = ctrl_inb(PA_IMASK); - val |= value; - ctrl_outb(val, PA_IMASK); -} - -static void ack_landisk_irq(unsigned int irq) -{ - disable_landisk_irq(irq); -} - -static void end_landisk_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - enable_landisk_irq(irq); + ctrl_outb(ctrl_inb(PA_IMASK) | value, PA_IMASK); } -static struct hw_interrupt_type landisk_irq_type = { - .typename = "LANDISK IRQ", - .startup = startup_landisk_irq, - .shutdown = shutdown_landisk_irq, - .enable = enable_landisk_irq, - .disable = disable_landisk_irq, - .ack = ack_landisk_irq, - .end = end_landisk_irq +static struct irq_chip landisk_irq_chip __read_mostly = { + .name = "LANDISK", + .mask = disable_landisk_irq, + .unmask = enable_landisk_irq, + .mask_ack = disable_landisk_irq, }; -static void make_landisk_irq(unsigned int irq) -{ - disable_irq_nosync(irq); - irq_desc[irq].chip = &landisk_irq_type; - disable_landisk_irq(irq); -} - /* * Initialize IRQ setting */ @@ -92,6 +46,11 @@ void __init init_landisk_IRQ(void) { int i; - for (i = 5; i < 14; i++) - make_landisk_irq(i); + for (i = 5; i < 14; i++) { + disable_irq_nosync(i); + set_irq_chip_and_handler_name(i, &landisk_irq_chip, + handle_level_irq, "level"); + enable_landisk_irq(i); + } + ctrl_outb(0x00, PA_PWRINT_CLR); } diff -urpN OLD/arch/sh/boards/landisk/psw.c NEW/arch/sh/boards/landisk/psw.c --- OLD/arch/sh/boards/landisk/psw.c 1970-01-01 09:00:00.000000000 +0900 +++ NEW/arch/sh/boards/landisk/psw.c 2007-03-17 09:09:29.000000000 +0900 @@ -0,0 +1,145 @@ +/* + * arch/sh/boards/landisk/psw.c + * + * push switch support for LANDISK and USL-5P + * + * Copyright (C) 2006 Paul Mundt + * Copyright (C) 2007 Paul Mundt + * Copyright (C) 2007 kogiidena + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/io.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <asm/landisk/iodata_landisk.h> +#include <asm/push-switch.h> + +static irqreturn_t psw_irq_handler(int irq, void *arg) +{ + struct platform_device *pdev = arg; + struct push_switch *psw = platform_get_drvdata(pdev); + struct push_switch_platform_info *psw_info = pdev->dev.platform_data; + unsigned int sw_value; + int ret = 0; + + sw_value = (0x0ff & (~ctrl_inb(PA_STATUS))); + + /* Nothing to do if there's no state change */ + if (psw->state) { + ret = 1; + goto out; + } + + /* Figure out who raised it */ + if (sw_value & (1 << psw_info->bit)) { + psw->state = 1; + mod_timer(&psw->debounce, jiffies + 50); + ret = 1; + } + + out: + /* Clear the switch IRQs */ + ctrl_outb(0x00, PA_PWRINT_CLR); + + return IRQ_RETVAL(ret); +} + +static struct resource psw_power_resources[] = { + [0] = { + .start = IRQ_POWER, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource psw_usl5p_resources[] = { + [0] = { + .start = IRQ_BUTTON, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct push_switch_platform_info psw_power_platform_data = { + .name = "psw_power", + .bit = 4, + .irq_flags = IRQF_SHARED, + .irq_handler = psw_irq_handler, +}; + +static struct push_switch_platform_info psw1_platform_data = { + .name = "psw1", + .bit = 0, + .irq_flags = IRQF_SHARED, + .irq_handler = psw_irq_handler, +}; + +static struct push_switch_platform_info psw2_platform_data = { + .name = "psw2", + .bit = 2, + .irq_flags = IRQF_SHARED, + .irq_handler = psw_irq_handler, +}; + +static struct push_switch_platform_info psw3_platform_data = { + .name = "psw3", + .bit = 1, + .irq_flags = IRQF_SHARED, + .irq_handler = psw_irq_handler, +}; + +static struct platform_device psw_power_switch_device = { + .name = "push-switch", + .id = 0, + .num_resources = ARRAY_SIZE(psw_power_resources), + .resource = psw_power_resources, + .dev = { + .platform_data = &psw_power_platform_data, + }, +}; + +static struct platform_device psw1_switch_device = { + .name = "push-switch", + .id = 1, + .num_resources = ARRAY_SIZE(psw_usl5p_resources), + .resource = psw_usl5p_resources, + .dev = { + .platform_data = &psw1_platform_data, + }, +}; + +static struct platform_device psw2_switch_device = { + .name = "push-switch", + .id = 2, + .num_resources = ARRAY_SIZE(psw_usl5p_resources), + .resource = psw_usl5p_resources, + .dev = { + .platform_data = &psw2_platform_data, + }, +}; + +static struct platform_device psw3_switch_device = { + .name = "push-switch", + .id = 3, + .num_resources = ARRAY_SIZE(psw_usl5p_resources), + .resource = psw_usl5p_resources, + .dev = { + .platform_data = &psw3_platform_data, + }, +}; + +static struct platform_device *psw_devices[] = { + &psw_power_switch_device, + &psw1_switch_device, + &psw2_switch_device, + &psw3_switch_device, +}; + +static int __init psw_init(void) +{ + return platform_add_devices(psw_devices, ARRAY_SIZE(psw_devices)); +} + +module_init(psw_init); diff -urpN OLD/arch/sh/boards/landisk/setup.c NEW/arch/sh/boards/landisk/setup.c --- OLD/arch/sh/boards/landisk/setup.c 2007-03-16 09:20:01.000000000 +0900 +++ NEW/arch/sh/boards/landisk/setup.c 2007-03-17 09:09:29.000000000 +0900 @@ -1,144 +1,96 @@ /* * arch/sh/boards/landisk/setup.c * - * Copyright (C) 2000 Kazumoto Kojima - * Copyright (C) 2002 Paul Mundt - * * I-O DATA Device, Inc. LANDISK Support. * - * Modified for LANDISK by - * Atom Create Engineering Co., Ltd. 2002. - * - * modifed by kogiidena - * 2005.09.16 + * Copyright (C) 2000 Kazumoto Kojima + * Copyright (C) 2002 Paul Mundt + * Copylight (C) 2002 Atom Create Engineering Co., Ltd. + * Copyright (C) 2005-2007 kogiidena * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ #include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pata_platform.h> #include <linux/pm.h> #include <linux/mm.h> #include <asm/machvec.h> -#include <asm/rtc.h> #include <asm/landisk/iodata_landisk.h> #include <asm/io.h> -void landisk_time_init(void); void init_landisk_IRQ(void); -int landisk_ledparam; -int landisk_buzzerparam; -int landisk_arch; - -/* cycle the led's in the clasic knightrider/sun pattern */ -static void heartbeat_landisk(void) -{ - static unsigned int cnt = 0, blink = 0x00, period = 25; - volatile u8 *p = (volatile u8 *)PA_LED; - char data; - - if ((landisk_ledparam & 0x080) == 0) - return; - - cnt += 1; - - if (cnt < period) - return; - - cnt = 0; - blink++; - - data = (blink & 0x01) ? (landisk_ledparam >> 16) : 0; - data |= (blink & 0x02) ? (landisk_ledparam >> 8) : 0; - data |= landisk_ledparam; - - /* buzzer */ - if (landisk_buzzerparam & 0x1) { - data |= 0x80; - } else { - data &= 0x7f; - } - *p = data; - - if (((landisk_ledparam & 0x007f7f00) == 0) && - (landisk_buzzerparam == 0)) - landisk_ledparam &= (~0x0080); - - landisk_buzzerparam >>= 1; -} - static void landisk_power_off(void) { ctrl_outb(0x01, PA_SHUTDOWN); } -static void check_usl5p(void) -{ - volatile u8 *p = (volatile u8 *)PA_LED; - u8 tmp1, tmp2; +static struct resource cf_ide_resources[3]; - tmp1 = *p; - *p = 0x40; - tmp2 = *p; - *p = tmp1; - - landisk_arch = (tmp2 == 0x40); - if (landisk_arch == 1) { - /* arch == usl-5p */ - landisk_ledparam = 0x00000380; - landisk_ledparam |= (tmp1 & 0x07c); - } else { - /* arch == landisk */ - landisk_ledparam = 0x02000180; - landisk_ledparam |= 0x04; - } -} +static struct pata_platform_info pata_info = { + .ioport_shift = 1, +}; + +static struct platform_device cf_ide_device = { + .name = "pata_platform", + .id = -1, + .num_resources = ARRAY_SIZE(cf_ide_resources), + .resource = cf_ide_resources, + .dev = { + .platform_data = &pata_info, + }, +}; -void *area5_io_base; -void *area6_io_base; +static struct platform_device landisk_led_device = { + .name = "landisk-led", + .id = -1 +}; + +static struct platform_device *landisk_devices[] __initdata = { + &cf_ide_device, + &landisk_led_device, +}; -static int __init landisk_cf_init(void) +static int __init landisk_devices_setup(void) { pgprot_t prot; - unsigned long paddrbase, psize; + unsigned long paddrbase; + void *cf_ide_base; /* open I/O area window */ paddrbase = virt_to_phys((void *)PA_AREA5_IO); - psize = PAGE_SIZE; prot = PAGE_KERNEL_PCC(1, _PAGE_PCC_IO16); - area5_io_base = p3_ioremap(paddrbase, psize, prot.pgprot); - if (!area5_io_base) { + cf_ide_base = p3_ioremap(paddrbase, PAGE_SIZE, prot.pgprot); + if (!cf_ide_base) { printk("allocate_cf_area : can't open CF I/O window!\n"); return -ENOMEM; } - paddrbase = virt_to_phys((void *)PA_AREA6_IO); - psize = PAGE_SIZE; - prot = PAGE_KERNEL_PCC(0, _PAGE_PCC_IO16); - area6_io_base = p3_ioremap(paddrbase, psize, prot.pgprot); - if (!area6_io_base) { - printk("allocate_cf_area : can't open HDD I/O window!\n"); - return -ENOMEM; - } - - printk(KERN_INFO "Allocate Area5/6 success.\n"); - - /* XXX : do we need attribute and common-memory area also? */ + /* IDE cmd address : 0x1f0-0x1f7 and 0x3f6 */ + cf_ide_resources[0].start = (unsigned long)cf_ide_base + 0x40; + cf_ide_resources[0].end = (unsigned long)cf_ide_base + 0x40 + 0x0f; + cf_ide_resources[0].flags = IORESOURCE_IO; + cf_ide_resources[1].start = (unsigned long)cf_ide_base + 0x2c; + cf_ide_resources[1].end = (unsigned long)cf_ide_base + 0x2c + 0x03; + cf_ide_resources[1].flags = IORESOURCE_IO; + cf_ide_resources[2].start = IRQ_FATA; + cf_ide_resources[2].flags = IORESOURCE_IRQ; - return 0; + return platform_add_devices(landisk_devices, + ARRAY_SIZE(landisk_devices)); } +__initcall(landisk_devices_setup); + static void __init landisk_setup(char **cmdline_p) { - device_initcall(landisk_cf_init); - - landisk_buzzerparam = 0; - check_usl5p(); + /* LED ON */ + ctrl_outb(ctrl_inb(PA_LED) | 0x03, PA_LED); printk(KERN_INFO "I-O DATA DEVICE, INC. \"LANDISK Series\" support.\n"); - - board_time_init = landisk_time_init; pm_power_off = landisk_power_off; } @@ -148,29 +100,6 @@ static void __init landisk_setup(char ** struct sh_machine_vector mv_landisk __initmv = { .mv_name = "LANDISK", .mv_setup = landisk_setup, - .mv_nr_irqs = 72, - .mv_inb = landisk_inb, - .mv_inw = landisk_inw, - .mv_inl = landisk_inl, - .mv_outb = landisk_outb, - .mv_outw = landisk_outw, - .mv_outl = landisk_outl, - .mv_inb_p = landisk_inb_p, - .mv_inw_p = landisk_inw, - .mv_inl_p = landisk_inl, - .mv_outb_p = landisk_outb_p, - .mv_outw_p = landisk_outw, - .mv_outl_p = landisk_outl, - .mv_insb = landisk_insb, - .mv_insw = landisk_insw, - .mv_insl = landisk_insl, - .mv_outsb = landisk_outsb, - .mv_outsw = landisk_outsw, - .mv_outsl = landisk_outsl, - .mv_ioport_map = landisk_ioport_map, .mv_init_irq = init_landisk_IRQ, -#ifdef CONFIG_HEARTBEAT - .mv_heartbeat = heartbeat_landisk, -#endif }; ALIAS_MV(landisk) diff -urpN OLD/arch/sh/drivers/pci/ops-landisk.c NEW/arch/sh/drivers/pci/ops-landisk.c --- OLD/arch/sh/drivers/pci/ops-landisk.c 2007-03-16 09:20:01.000000000 +0900 +++ NEW/arch/sh/drivers/pci/ops-landisk.c 2007-03-17 09:09:29.000000000 +0900 @@ -17,8 +17,8 @@ static struct resource sh7751_io_resource = { .name = "SH7751 IO", - .start = 0x4000, - .end = 0x4000 + SH7751_PCI_IO_SIZE - 1, + .start = SH7751_PCI_IO_BASE, + .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1, .flags = IORESOURCE_IO }; |
From: Kristoffer E. <kri...@ho...> - 2007-03-15 22:31:07
|
Greetings, In order to get a more proper enviroment I started removing the PIO stuff from io.c and adding correct adresses into hd64461.h. Im still getting exactly same error though. Some please take a look at this diff and tell me what im doing wrong. --- ../linux-2.6/include/asm-sh/hd64461.h 2006-09-27 19:23:52.000000000 +0000 +++ include/asm-sh/hd64461.h 2007-03-15 23:27:03.000000000 +0000 @@ -18,8 +18,9 @@ #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) #define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) -#define HD64461_STBCR 0x10000 -#define HD64461_STBCR_CKIO_STBY 0x2000 +/* if PORT < 0xf000 then ADDR = 0xa0000000 + PORT */ +#define HD64461_STBCR (CONFIG_HD64461_IOBASE + 0x10000 - 0x10000) +#define HD64461_STBCR_CKIO_STBY 0x2000 #define HD64461_STBCR_SAFECKE_IST 0x1000 #define HD64461_STBCR_SLCKE_IST 0x0800 #define HD64461_STBCR_SAFECKE_OST 0x0400 @@ -31,15 +32,18 @@ #define HD64461_STBCR_SAFEST 0x0010 #define HD64461_STBCR_STM0ST 0x0008 #define HD64461_STBCR_STM1ST 0x0004 -#define HD64461_STBCR_SIRST 0x0002 +#define HD64461_STBCR_SIRST 0x0002 #define HD64461_STBCR_SURTST 0x0001 -#define HD64461_SYSCR 0x10002 -#define HD64461_SCPUCR 0x10004 +/* if PORT < 0x20000 then ADDR = CONFIG_HD64461_IOBASE + PORT - 0x10000 */ +#define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x10002 - 0x10000) +#define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x10004 - 0x10000) +#define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x11000 - 0x10000) +#define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x11002 - 0x10000) +#define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x11004 - 0x10000) -#define HD64461_LCDCBAR 0x11000 -#define HD64461_LCDCLOR 0x11002 -#define HD64461_LCDCCR 0x11004 + +/* if PORT < 0xf000 then ADDR = 0xa0000000 + PORT */ #define HD64461_LCDCCR_STBACK 0x0400 #define HD64461_LCDCCR_STREQ 0x0100 #define HD64461_LCDCCR_MOFF 0x0080 @@ -47,142 +51,150 @@ #define HD64461_LCDCCR_EPON 0x0020 #define HD64461_LCDCCR_SPON 0x0010 -#define HD64461_LDR1 0x11010 +/* if PORT < 0x20000 then ADDR = CONFIG_HD64461_IOBASE + PORT - 0x10000 */ +#define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x11010 - 0x10000) + +/* if PORT < 0xf000 then ADDR = 0xa0000000 + PORT */ #define HD64461_LDR1_DON 0x01 #define HD64461_LDR1_DINV 0x80 -#define HD64461_LDR2 0x11012 -#define HD64461_LDHNCR 0x11014 -#define HD64461_LDHNSR 0x11016 -#define HD64461_LDVNTR 0x11018 -#define HD64461_LDVNDR 0x1101a -#define HD64461_LDVSPR 0x1101c -#define HD64461_LDR3 0x1101e - -#define HD64461_CPTWAR 0x11030 -#define HD64461_CPTWDR 0x11032 -#define HD64461_CPTRAR 0x11034 -#define HD64461_CPTRDR 0x11036 - -#define HD64461_GRDOR 0x11040 -#define HD64461_GRSCR 0x11042 -#define HD64461_GRCFGR 0x11044 +/* if PORT < 0x20000 then ADDR = CONFIG_HD64461_IOBASE + PORT - 0x10000 */ +#define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x11012 - 0x10000) +#define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x11014 - 0x10000) +#define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x11016 - 0x10000) +#define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x11018 - 0x10000) +#define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x1101a - 0x10000) +#define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x1101c - 0x10000) +#define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x1101e - 0x10000) + +#define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x11030 - 0x10000) +#define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x11032 - 0x10000) +#define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x11034 - 0x10000) +#define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x11036 - 0x10000) + +#define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x11040 - 0x10000) +#define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x11042 - 0x10000) +#define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x11044 - 0x10000) + #define HD64461_GRCFGR_ACCSTATUS 0x10 #define HD64461_GRCFGR_ACCRESET 0x08 -#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 -#define HD64461_GRCFGR_ACCSTART_LINE 0x04 +#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 +#define HD64461_GRCFGR_ACCSTART_LINE 0x04 #define HD64461_GRCFGR_COLORDEPTH16 0x01 -#define HD64461_LNSARH 0x11046 -#define HD64461_LNSARL 0x11048 -#define HD64461_LNAXLR 0x1104a -#define HD64461_LNDGR 0x1104c -#define HD64461_LNAXR 0x1104e -#define HD64461_LNERTR 0x11050 -#define HD64461_LNMDR 0x11052 -#define HD64461_BBTSSARH 0x11054 -#define HD64461_BBTSSARL 0x11056 -#define HD64461_BBTDSARH 0x11058 -#define HD64461_BBTDSARL 0x1105a -#define HD64461_BBTDWR 0x1105c -#define HD64461_BBTDHR 0x1105e -#define HD64461_BBTPARH 0x11060 -#define HD64461_BBTPARL 0x11062 -#define HD64461_BBTMARH 0x11064 -#define HD64461_BBTMARL 0x11066 -#define HD64461_BBTROPR 0x11068 -#define HD64461_BBTMDR 0x1106a +/* if PORT < 0x20000 then CONFIG_HD64461_IOBASE + PORT - 0x10000 */ +#define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x11046 - 0x10000) +#define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x11048 - 0x10000) +#define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x1104a - 0x10000) +#define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x1104c - 0x10000) +#define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x1104e - 0x10000) +#define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x11050 - 0x10000) +#define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x11052 - 0x10000) +#define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x11054 - 0x10000) +#define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x11056 - 0x10000) +#define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x11058 - 0x10000) +#define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x1105a - 0x10000) +#define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x1105c - 0x10000) +#define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x1105e - 0x10000) +#define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x11060 - 0x10000) +#define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x11062 - 0x10000) +#define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x11064 - 0x10000) +#define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x11066 - 0x10000) +#define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x11068 - 0x10000) +#define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x1106a - 0x10000) +/* These must be like this, otherwise the Jornada will not boot! */ /* PC Card Controller Registers */ -#define HD64461_PCC0ISR 0x12000 /* socket 0 interface status */ -#define HD64461_PCC0GCR 0x12002 /* socket 0 general control */ -#define HD64461_PCC0CSCR 0x12004 /* socket 0 card status change */ -#define HD64461_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */ -#define HD64461_PCC0SCR 0x12008 /* socket 0 software control */ -#define HD64461_PCC1ISR 0x12010 /* socket 1 interface status */ -#define HD64461_PCC1GCR 0x12012 /* socket 1 general control */ -#define HD64461_PCC1CSCR 0x12014 /* socket 1 card status change */ -#define HD64461_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */ -#define HD64461_PCC1SCR 0x12018 /* socket 1 software control */ +#define HD64461_PCC0ISR (0xb8000000 + 0x12000 - 0x10000) /* socket 0 interface status */ +#define HD64461_PCC0GCR (0xb8000000 + 0x12002 - 0x10000) /* socket 0 general control */ +#define HD64461_PCC0CSCR (0xb8000000 + 0x12004 - 0x10000) /* socket 0 card status change */ +#define HD64461_PCC0CSCIER (0xb8000000 + 0x12006 - 0x10000) /* socket 0 card status change interrupt enable */ +#define HD64461_PCC0SCR (0xb8000000 + 0x12008 - 0x10000) /* socket 0 software control */ +#define HD64461_PCC1ISR (0xb4000000 + 0x12010 - 0x10000) /* socket 1 interface status */ +#define HD64461_PCC1GCR (0xb4000000 + 0x12012 - 0x10000) /* socket 1 general control */ +#define HD64461_PCC1CSCR (0xb4000000 + 0x12014 - 0x10000) /* socket 1 card status change */ +#define HD64461_PCC1CSCIER (0xb4000000 + 0x12016 - 0x10000) /* socket 1 card status change interrupt enable */ +#define HD64461_PCC1SCR (0xb4000000 + 0x12018 - 0x10000) /* socket 1 software control */ /* PCC Interface Status Register */ -#define HD64461_PCCISR_READY 0x80 /* card ready */ -#define HD64461_PCCISR_MWP 0x40 /* card write-protected */ -#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ -#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ -#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ -#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ -#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ -#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ - -#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ -#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ -#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ -#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ -#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ -#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ +#define HD64461_PCCISR_READY 0x80 /* card ready */ +#define HD64461_PCCISR_MWP 0x40 /* card write-protected */ +#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ +#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ +#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ +#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ +#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ +#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ + +#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ +#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ +#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ +#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ +#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ +#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ /* PCC General Control Register */ -#define HD64461_PCCGCR_DRVE 0x80 /* output drive */ -#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ -#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ -#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ -#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ -#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ -#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ -#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ +#define HD64461_PCCGCR_DRVE 0x80 /* output drive */ +#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ +#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ +#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ +#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ +#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ +#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ +#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ /* PCC Card Status Change Register */ -#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ -#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ -#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ -#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ -#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ -#define HD64461_PCCCSCR_RC 0x04 /* READY change */ -#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ -#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ +#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ +#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ +#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ +#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ +#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ +#define HD64461_PCCCSCR_RC 0x04 /* READY change */ +#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ +#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ /* PCC Card Status Change Interrupt Enable Register */ -#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ -#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ -#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ -#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ -#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ -#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ - -#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ -#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ -#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ -#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ -#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ +#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ +#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ +#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ +#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ +#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ +#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ + +#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ +#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ +#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ +#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ +#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ /* PCC Software Control Register */ -#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ -#define HD64461_PCCSCR_SWP 0x01 /* write protect */ - -#define HD64461_P0OCR 0x1202a -#define HD64461_P1OCR 0x1202c -#define HD64461_PGCR 0x1202e - -#define HD64461_GPACR 0x14000 -#define HD64461_GPBCR 0x14002 -#define HD64461_GPCCR 0x14004 -#define HD64461_GPDCR 0x14006 -#define HD64461_GPADR 0x14010 -#define HD64461_GPBDR 0x14012 -#define HD64461_GPCDR 0x14014 -#define HD64461_GPDDR 0x14016 -#define HD64461_GPAICR 0x14020 -#define HD64461_GPBICR 0x14022 -#define HD64461_GPCICR 0x14024 -#define HD64461_GPDICR 0x14026 -#define HD64461_GPAISR 0x14040 -#define HD64461_GPBISR 0x14042 -#define HD64461_GPCISR 0x14044 -#define HD64461_GPDISR 0x14046 +#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ +#define HD64461_PCCSCR_SWP 0x01 /* write protect */ -#define HD64461_NIRR 0x15000 -#define HD64461_NIMR 0x15002 +#define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x1202a - 0x10000) +#define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x1202c - 0x10000) +#define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x1202e - 0x10000) + +#define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x14000 - 0x10000) +#define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x14002 - 0x10000) +#define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x14004 - 0x10000) +#define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x14006 - 0x10000) +#define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x14010 - 0x10000) +#define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x14012 - 0x10000) +#define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x14014 - 0x10000) +#define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x14016 - 0x10000) +#define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x14020 - 0x10000) +#define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x14022 - 0x10000) +#define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x14024 - 0x10000) +#define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x14026 - 0x10000) +#define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x14040 - 0x10000) +#define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x14042 - 0x10000) +#define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x14044 - 0x10000) +#define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x14046 - 0x10000) + +/* if PORT < 20000 then ADDR = CONFIG_HD64461_IOBASE + 0x15000 - 0x10000 */ +#define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x15000 - 0x10000) +#define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x15002 - 0x10000) #define HD64461_IRQBASE OFFCHIP_IRQ_BASE #define HD64461_IRQ_NUM 16 _________________________________________________________________ Don't just search. Find. Check out the new MSN Search! http://search.msn.com/ |
From: Cmmn Ml <cm...@ya...> - 2007-03-14 09:45:32
|
=0A=0AHello,=0A=0A=0A =0A=0A=0AI'm a newbie to SuperH development. This may= be a very basic=0Asimple, but I couldn't find any answer from the mailing = list. So can you / one=0Aof you tell me how to do this?=0A=0A=0A =0A=0A=0AI= have a SH 7705 based development board with Flash and=0ASDRAM. My problem = is how to download the sh-boot to the Flash memory in my=0Aboard. =0A=0A=0A= =0A=0A=0AI have access to an E10A emulator, but I couldn't find an=0Aeasy = way to download a program to the flash using it. As I found there is a way= =0Ato do that through the emulator by manually initializing the SDRAM and= =0Aproviding a flash writing program separately. But I'm using the gcc as m= y=0Acompiler and I'm not sure how to do that using open source software too= l chain.=0A=0A=0A =0A=0A=0AThanks in advance.=0A=0A=0A =0A=0A=0A =0A=0A=0AC= mmn=0A=0A=0A=0A=0A=0A=0A =0A_______________________________________________= _____________________________________=0ASucker-punch spam with award-winnin= g protection. =0ATry the free Yahoo! Mail Beta.=0Ahttp://advision.webevents= .yahoo.com/mailbeta/features_spam.html |
From: Kristoffer E. <kri...@ho...> - 2007-03-13 20:47:57
|
Greetings, I've changed the code to use MMIO instead. .start 0xb5000000 + 0x1f0 .end 0xb5000000 + 0x1f7 and .start 0xb50001fe .end 0xb50001ff with MEM instead of IO. It now detects the ATA1 properly, but goes into an endles loop with : ata1: soft resetting port ata1.00 : configured for PIO <--- ??? ata1 : EH complete ata1.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x2 frozen ata1.00: cmd 20/00:08:00:00:00/00:00:00:00:00/e0 tag 0 cdb 0x0 data 4096 in res 40/00:00:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout) ata1: soft resetting port Suggestions? Best wishes Kristoffer >From: Paul Mundt <le...@li...> >To: Kristoffer Ericson <kri...@ho...> >CC: lin...@li... >Subject: Re: HP6xx kernel panic at bootup >Date: Tue, 13 Mar 2007 08:37:07 +0900 > >On Mon, Mar 12, 2007 at 08:49:00PM +0000, Kristoffer Ericson wrote: > > The only part of the Kernel panic I can see is just the data dump, which > > doesnt help you much. (adresses running from 1c80: -> 1fe0). > > > > I believe its somehow related to the PATA driver, but hard to be sure. > > >Yes, you should be using the MMIO address, the problem is that you're >using the PIO address and it's completely unhandled by your I/O routines. > > > +static struct resource cf_ide_resources[] = { > > + [0] = { > > + .start = 0x1f0, > > + .end = 0x1f0 + 8, > > + .flags = IORESOURCE_IO, > > + }, > > + [1] = { > > + .start = 0x3f6, > > + .end = 0x3f7, > > + .flags = IORESOURCE_IO, > > + }, > >So change these to the MMIO address, and switch to IORESOURCE_MEM. > > > +static int __init hp6xx_devices_setup(void) > > +{ > > + return platform_add_devices(hp6xx_devices,ARRAY_SIZE(hp6xx_devices)); > > +} > > + > > static void __init hp6xx_setup(char **cmdline_p) > > { > > u8 v8; > > u16 v; > > > > + device_initcall(hp6xx_devices_setup); > > + > >Move this after hp6xx_devices_setup(). > > > diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h > > index 29d4fb9..eaf77fe 100644 > > --- a/include/asm-sh/irq.h > > +++ b/include/asm-sh/irq.h > > @@ -190,7 +190,7 @@ static inline int generic_irq_demux(int > > > > #define irq_canonicalize(irq) (irq) > > #define irq_demux(irq) sh_mv.mv_irq_demux(irq) > > - > > +#define __irq_demux(irq) (irq) > > #ifdef CONFIG_4KSTACKS > > extern void irq_ctx_init(int cpu); > > extern void irq_ctx_exit(int cpu); > > >What is using this? _________________________________________________________________ Don't just search. Find. Check out the new MSN Search! http://search.msn.click-url.com/go/onm00200636ave/direct/01/ |
From: Bill T. <wm...@na...> - 2007-03-13 20:25:07
|
I've decided to pass along my SH hardware to someone who can put it to better use than I (which amounts to no use at all). I have the following for sale, which ideally, I'd like to sell in one shot as a package: SH3: 1 - Jornada 690 w/ Docking Cradle, Wireless Card, 32MB RAM 1 - Holux GPS Receiver w/ Jornada connector SH4: 3 x Dreamcasts 2 x Broad Band Adapters (HIT-0401) - the good ones 2 x Dreamcast Keyboards 2 x Coders Cable 1 x VGA Box 1 x VMU Other: 1 x "SuperH MicroComputers" by Yukiho Fujisawa 1 x Atmel AT91EB40A Evaluation Kit (ARM chip) Free Stuff with package: CD's to boot Dreamcast to Linux A bunch of Dreamcast games The whole package for $600 Canadian + shipping. Please email me off list if you're interested. Thanks Bill |
From: Paul M. <le...@li...> - 2007-03-12 23:40:52
|
On Mon, Mar 12, 2007 at 07:28:18PM +0000, Kristoffer Ericson wrote: > Not sure if you got these properly before Paul, so here goes again. Patches > are against current git. > > declare-work() and clk_get() have changed their desired number of > variables, therefore we need to adjust them. > Applied, thanks. |
From: Paul M. <le...@li...> - 2007-03-12 23:40:01
|
On Mon, Mar 12, 2007 at 08:49:00PM +0000, Kristoffer Ericson wrote: > The only part of the Kernel panic I can see is just the data dump, which > doesnt help you much. (adresses running from 1c80: -> 1fe0). > > I believe its somehow related to the PATA driver, but hard to be sure. > Yes, you should be using the MMIO address, the problem is that you're using the PIO address and it's completely unhandled by your I/O routines. > +static struct resource cf_ide_resources[] = { > + [0] = { > + .start = 0x1f0, > + .end = 0x1f0 + 8, > + .flags = IORESOURCE_IO, > + }, > + [1] = { > + .start = 0x3f6, > + .end = 0x3f7, > + .flags = IORESOURCE_IO, > + }, So change these to the MMIO address, and switch to IORESOURCE_MEM. > +static int __init hp6xx_devices_setup(void) > +{ > + return platform_add_devices(hp6xx_devices,ARRAY_SIZE(hp6xx_devices)); > +} > + > static void __init hp6xx_setup(char **cmdline_p) > { > u8 v8; > u16 v; > > + device_initcall(hp6xx_devices_setup); > + Move this after hp6xx_devices_setup(). > diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h > index 29d4fb9..eaf77fe 100644 > --- a/include/asm-sh/irq.h > +++ b/include/asm-sh/irq.h > @@ -190,7 +190,7 @@ static inline int generic_irq_demux(int > > #define irq_canonicalize(irq) (irq) > #define irq_demux(irq) sh_mv.mv_irq_demux(irq) > - > +#define __irq_demux(irq) (irq) > #ifdef CONFIG_4KSTACKS > extern void irq_ctx_init(int cpu); > extern void irq_ctx_exit(int cpu); > What is using this? |
From: Kristoffer E. <kri...@ho...> - 2007-03-12 21:31:11
|
Greetings, Managed to get someone to send me a bootlog, looks like it really is the PATA causing the issue. 1. DMA: Registering DMA API. 2. DMA: Registering sh_dmac handler (4 channels). 3. NET: Registered protocol family 2 4. IP route cache hash table entries: 1024 (order: 0, 4096 bytes) 5. TCP established hash table entries: 1024 (order: 1, 8192 bytes) 6. TCP bind hash table entries: 1024 (order: 0, 4096 bytes) 7. TCP: Hash tables configured (established 1024 bind 1024) 8. TCP reno registered 9. HD64461 configured at 0xb0000000 on irq 36(mapped into 80 to 95) 10. HD64461: enabling PCMCIA devices 11. io scheduler noop registered 12. io scheduler anticipatory registered (default) 13. io scheduler deadline registered 14. io scheduler cfq registered 15. Console: switching to colour frame buffer device 80x30 16. fb0: Hitachi HD64461 frame buffer device 17. SuperH SCI(F) driver initialized 18. sh-sci: ttySC0 at MMIO 0xfffffe80 (irq = 25) is a sci 19. sh-sci: ttySC1 at MMIO 0xa4000150 (irq = 59) is a scif 20. loop: loaded (max 8 devices) 21. SCSI Media Changer driver v0.25 22. ata1: PATA max PIO0 cmd 0x000001f0 ctl 0x000003f6 bmdma 0x00000000 irq 93 23. Unable to handle kernel NULL pointer dereference at virtual address 000003f6 24. pc = 8d006bb2 25. *pde = 00000000 26. Oops: 0001 [#1] 27. Modules linked in: 28. 29. Pid : 1, Comm: swapper 30. PC is at generic_writeb+0x2/0x10 31. PC : 8d006bb2 SP : 8d2c5c30 SR : 400001f0 TEA : 000003f6 Not tainted 32. R0 : 0000000a R1 : 8d006bb0 R2 : 8d3b82f4 R3 : 00000001 33. R4 : 0000000a R5 : 000003f6 R6 : ffffffff R7 : 000000f0 34. R8 : 8d3b82c8 R9 : 8d2c5c38 R10 : 8d3b8308 R11 : 00000000 35. R12 : 8d3aff1c R13 : 8d2c5c8c R14 : 8d22aa64 36. MACH: 00000060 MACL: 00000000 GBR : 00000000 PR : 8d12fcf2 37. 38. Call trace: 39. [<8d1301c4>] __ata_port_freeze+0x34/0x70 40. [<8d1305c2>] ata_eh_freeze_port+0x32/0x70 41. [<8d12b658>] ata_device_add+0x1f8/0x4a0 42. [<8d10c286>] devres_alloc+0x16/0x50 43. [<8d132e4c>] pata_platform_probe+0x15c/0x280 44. [<8d0db230>] devm_ioport_map+0x0/0x70 45. [<8d10ab2e>] platform_drv_probe+0xe/0x20 46. [<8d108714>] really_probe+0xd4/0x190 47. [<8d108886>] driver_probe_device+0x96/0xe0 48. [<8d108ac6>] __driver_attach+0xf6/0x160 49. [<8d1076d8>] bus_for_each_dev+0x48/0x90 50. [<8d1089d0>] __driver_attach+0x0/0x160 51. [<8d107660>] next_device+0x0/0x30 52. [<8d107e5c>] bus_add_driver+0x4c/0x1a0 53. [<8d240a04>] init+0x64/0x1e0 54. [<8d003004>] kernel_thread_helper+0x4/0x10 55. [<8d2409a0>] init+0x0/0x1e0 56. [<8d003000>] kernel_thread_helper+0x0/0x10 57. 58. 59. Process: swapper (pid: 1, stack limit = 8d2c4001) 60. Stack: (0x8d2c5c30 to 0x8d2c6000) 61. 62. 5c20: 8d1301c4 8d3b82c8 8d1305c2 00000000 63. 5c40: 8d12b658 8d3b82c8 00000000 0000005d 8d2c5e88 8d2c5e48 00000001 00000050 64. 5c60: 8d10c286 8d3aff40 8d3aff1c 8d132e4c 00000000 00000000 8d22aa64 8d22aa5c 65. 5c80: 8d22abd8 8d2c5ccc 8d0db230 8d2c5c8c 8d2c5c8c 8d22aa64 8d235838 8d23579c 66. 67. 5ca0: 000001f0 000001f0 000001f1 000001f1 000001f2 000001f3 000001f4 000001f5 68. 5cc0: 000001f6 000001f7 000001f7 000003f6 000003f6 00000000 00000000 00000000 69. 5ce0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 70. 5d00: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 71. 5d20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 72. 5d40: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 73. 5d60: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 74. 75. 5d80: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 76. 5da0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 77. 5dc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 78. 5de0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 79. 80. 5e00: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 81. 5e20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 82. 5e40: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 83. 5e60: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 84. 85. 5e80: 00000001 00000000 00000001 00000000 00000000 0000005d 00000000 00000000 86. 5ea0: 00000011 00000000 00000000 00000000 00000000 8d10ab2e 8d25ded8 00000000 87. 5ec0: 8d235700 8d3a19a0 8d22aa64 8d22ab20 8d108714 8d108886 8d24e4b4 00000000 88. 5ee0: 00000000 8d22aa64 8d3a19a0 8d23577c 8d108ac6 00000000 8d235700 8d235700 89. 90. 5f00: 8d22aaa4 8d22aa64 8d1076d8 8d1089d0 8d107660 00000000 8d233a78 8d233a78 91. 5f20: 8d22aaac 8d107e5c 8d233978 8d235714 8d235700 00000000 8d240a04 00000000 92. 5f40: 8d24e4b4 00000000 8d24c864 00000000 8d24e454 8d2c4000 b7b5172f 6b0efe54 93. 5f60: 811bf03b b7da224d 9cbe7a22 65638d08 54bd1cdd ce0970c4 b45f0458 43f881df 94. 5f80: 00000001 8d003004 00000000 00000000 00000000 00000000 00000000 00000000 95. 5fa0: 00000000 00000000 00000000 00000000 00000000 8d2409a0 00000000 00000000 96. 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8d2c5fa0 97. 98. 5fe0: 8d003000 00000000 40000000 00000000 00000000 00000000 00000000 059c02bf 99. Kernel panic - not syncing: Attempted to kill init! _________________________________________________________________ Express yourself instantly with MSN Messenger! Download today it's FREE! http://messenger.msn.click-url.com/go/onm00200471ave/direct/01/ |
From: Kristoffer E. <kri...@ho...> - 2007-03-12 20:49:15
|
Greetings, I've synced the changes I had with git and it now compiles without any issues. At bootup though I receive a kernel panic and "not syncing: Attempted to kill init!". Im unable to create a bootlog since I have no serial cable for my jornada. The only part of the Kernel panic I can see is just the data dump, which doesnt help you much. (adresses running from 1c80: -> 1fe0). I believe its somehow related to the PATA driver, but hard to be sure. My patches for git are these: diff --git a/arch/sh/boards/hp6xx/setup.c b/arch/sh/boards/hp6xx/setup.c index b5a9664..abec0e0 100644 --- a/arch/sh/boards/hp6xx/setup.c +++ b/arch/sh/boards/hp6xx/setup.c @@ -15,15 +15,52 @@ #include <asm/io.h> #include <asm/irq.h> #include <asm/hp6xx.h> #include <asm/cpu/dac.h> +#include <linux/platform_device.h> #define SCPCR 0xa4000116 #define SCPDR 0xa4000136 +static struct resource cf_ide_resources[] = { + [0] = { + .start = 0x1f0, + .end = 0x1f0 + 8, + .flags = IORESOURCE_IO, + }, + [1] = { + .start = 0x3f6, + .end = 0x3f7, + .flags = IORESOURCE_IO, + }, + [2] = { + .start = 93, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cf_ide_device = { + .name = "pata_platform", + .id = -1, + .num_resources = ARRAY_SIZE(cf_ide_resources), + .resource = cf_ide_resources, +}; + +static struct platform_device *hp6xx_devices[] __initdata = { + + &cf_ide_device, +}; + +static int __init hp6xx_devices_setup(void) +{ + return platform_add_devices(hp6xx_devices,ARRAY_SIZE(hp6xx_devices)); +} + static void __init hp6xx_setup(char **cmdline_p) { u8 v8; u16 v; + device_initcall(hp6xx_devices_setup); + v = inw(HD64461_STBCR); v |= HD64461_STBCR_SURTST | HD64461_STBCR_SIRST | HD64461_STBCR_STM1ST | HD64461_STBCR_STM0ST | diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c index 06ed060..b56fab8 100644 --- a/arch/sh/drivers/dma/dma-sh.c +++ b/arch/sh/drivers/dma/dma-sh.c @@ -19,6 +19,13 @@ #include <asm/dma.h> #include <asm/io.h> #include "dma-sh.h" +#ifdef CONFIG_CPU_SUBTYPE_SH7709 + #define DMTE0_IRQ 48 + #define DMTE1_IRQ 49 + #define DMTE2_IRQ 50 + #define DMTE3_IRQ 51 +#endif + static int dmte_irq_map[] = { DMTE0_IRQ, DMTE1_IRQ, diff --git a/include/asm-sh/hp6xx.h b/include/asm-sh/hp6xx.h index f35134c..f628be7 100644 --- a/include/asm-sh/hp6xx.h +++ b/include/asm-sh/hp6xx.h @@ -14,6 +14,8 @@ #define HP680_BTN_IRQ IRQ0_IRQ #define HP680_TS_IRQ IRQ3_IRQ #define HP680_HD64461_IRQ IRQ4_IRQ +#define IRQ3_IRQ 35 + #define DAC_LCD_BRIGHTNESS 0 #define DAC_SPEAKER_VOLUME 1 diff --git a/include/asm-sh/hp6xx.h b/include/asm-sh/hp6xx.h index f628be7..17787a6 100644 --- a/include/asm-sh/hp6xx.h +++ b/include/asm-sh/hp6xx.h @@ -47,6 +47,8 @@ #define ADC_CHANNEL_CHARGE 5 #define HD64461_GPADR_SPEAKER 0x01 #define HD64461_GPADR_PCMCIA0 (0x02|0x08) +#define TIMER1_IRQ 16 + #define HD64461_GPBDR_LCDOFF 0x01 #define HD64461_GPBDR_LCD_CONTRAST_MASK 0x78 #define HD64461_GPBDR_LED_RED 0x80 diff --git a/drivers/input/touchscreen/hp680_ts_input.c b/drivers/input/touchscreen/hp680_ts_input.c index 2490874..61c1502 100644 --- a/drivers/input/touchscreen/hp680_ts_input.c +++ b/drivers/input/touchscreen/hp680_ts_input.c @@ -21,7 +21,7 @@ #define SCPDR 0xa4000136 static void do_softint(void *data); static struct input_dev *hp680_ts_dev; -static DECLARE_WORK(work, do_softint, 0); +static DECLARE_WORK(work, do_softint); static void do_softint(void *data) { diff --git a/drivers/video/backlight/hp680_bl.c b/drivers/video/backlight/hp680_bl.c index 0899fcc..b2faf82 100644 --- a/drivers/video/backlight/hp680_bl.c +++ b/drivers/video/backlight/hp680_bl.c @@ -125,8 +125,7 @@ static int hp680bl_remove(struct platfor { struct backlight_device *bd = platform_get_drvdata(pdev); +// hp680bl_data.brightness = 0; +// hp680bl_data.power = 0; hp680bl_send_intensity(bd); backlight_device_unregister(bd); diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7709.c b/arch/sh/kernel/cpu/sh3/setup-sh7709.c index dc9b211..013e87f 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7709.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7709.c @@ -55,6 +55,8 @@ __initcall(sh7709_devices_setup); #define IPRx(A,N) .addr=A, .shift=0*N*-1 #define IPRA(N) IPRx(0xfffffee2UL,N) #define IPRB(N) IPRx(0xfffffee4UL,N) +#define IPRC(N) IPRx(0xa0000016UL,N) +#define IPRD(N) IPRx(0xa0000018UL,N) #define IPRE(N) IPRx(0xa400001aUL,N) static struct ipr_data sh7709_ipr_map[] = { @@ -63,6 +65,12 @@ static struct ipr_data sh7709_ipr_map[] [22] = { IPRA(3-0), 2 }, /* RTC CUI */ [23 ... 26] = { IPRB(7-4), 3 }, /* SCI */ [27] = { IPRB(15-12), 2 }, /* WDT ITI */ + [32] = { IPRC(0), 1 }, /* IRQ 0 */ + [33] = { IPRC(1), 1 }, /* IRQ 1 */ + [34] = { IPRC(2), 1 }, /* IRQ 2 APM */ + [35] = { IPRC(3), 1 }, /* IRQ 3 TOUCHSCREEN */ + [36] = { IPRD(0), 1 }, /* IRQ 4 */ + [37] = { IPRD(1), 1 }, /* IRQ 5 */ [48 ... 51] = { IPRE(15-12), 7 }, /* DMA */ [52 ... 55] = { IPRE(11-8), 3 }, /* IRDA */ [56 ... 59] = { IPRE(7-4), 3 }, /* SCIF */ diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h index 29d4fb9..eaf77fe 100644 --- a/include/asm-sh/irq.h +++ b/include/asm-sh/irq.h @@ -190,7 +190,7 @@ static inline int generic_irq_demux(int #define irq_canonicalize(irq) (irq) #define irq_demux(irq) sh_mv.mv_irq_demux(irq) - +#define __irq_demux(irq) (irq) #ifdef CONFIG_4KSTACKS extern void irq_ctx_init(int cpu); extern void irq_ctx_exit(int cpu); diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h index 8ccf7ae..29d4fb9 100644 --- a/include/asm-sh/irq.h +++ b/include/asm-sh/irq.h @@ -23,6 +23,40 @@ #elif defined(CONFIG_CPU_SUBTYPE_SH7709) defined(CONFIG_CPU_SUBTYPE_SH7705) # define ONCHIP_NR_IRQS 64 // Actually 61 # define PINT_NR_IRQS 16 + + #define INTC_IRR0 0xa4000004UL + #define INTC_IRR1 0xa4000006UL + #define INTC_IRR2 0xa4000008UL + + #define INTC_IPRA 0xfffffee2UL + #define INTC_IPRB 0xfffffee4UL + #define INTC_IPRD 0xa4000018UL + + #define INTC_INTER 0xa4000014UL + + #define INTC_ICR0 0xfffffee0UL + #define INTC_ICR1 0xa4000010UL + #define INTC_ICR2 0xa4000012UL + + #define PORT_PACR 0xa4000100UL + #define PORT_PBCR 0xa4000102UL + #define PORT_PCCR 0xa4000104UL + #define PORT_PFCR 0xa400010aUL + + #define PORT_PADR 0xa4000120UL + #define PORT_PBDR 0xa4000122UL + #define PORT_PCDR 0xa4000124UL + #define PORT_PFDR 0xa400012aUL + + #define PINT0_IRQ 40 + #define PINT8_IRQ 41 + #define PINT0_IPR_ADDR INTC_IPRD + #define PINT8_IPR_ADDR INTC_IPRD + #define PINT0_IPR_POS 3 + #define PINT8_IPR_POS 2 + #define PINT0_PRIORITY 2 + #define PINT8_PRIORITY 2 + #elif defined(CONFIG_CPU_SUBTYPE_SH7710) # define ONCHIP_NR_IRQS 104 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) diff --git a/sound/oss/sh_dac_audio.c b/sound/oss/sh_dac_audio.c index 7ea9acc..b493660 100644 --- a/sound/oss/sh_dac_audio.c +++ b/sound/oss/sh_dac_audio.c @@ -104,7 +104,7 @@ static void dac_audio_set_rate(void) unsigned long interval; struct clk *clk; - clk = clk_get("module_clk"); + clk = clk_get(NULL, "module_clk"); interval = (clk_get_rate(clk) / 4) / rate; clk_put(clk); ctrl_outl(interval, TMU1_TCOR); _________________________________________________________________ Don't just search. Find. Check out the new MSN Search! http://search.msn.click-url.com/go/onm00200636ave/direct/01/ |
From: Kristoffer E. <kri...@ho...> - 2007-03-12 19:28:27
|
Not sure if you got these properly before Paul, so here goes again. Patches are against current git. declare-work() and clk_get() have changed their desired number of variables, therefore we need to adjust them. signed-off-by: Kristoffer Ericson <Kri...@ho...> _________________________________________________________________ Express yourself instantly with MSN Messenger! Download today it's FREE! http://messenger.msn.click-url.com/go/onm00200471ave/direct/01/ |
From: Paul M. <le...@li...> - 2007-03-12 06:13:48
|
On Mon, Mar 12, 2007 at 02:25:26PM +0900, Nobuhiro Iwamatsu wrote: > This patch is support Splution Engine's PCMCIA . > Please apply. > Applied, thanks. |
From: Paul M. <le...@li...> - 2007-03-12 05:53:58
|
On Mon, Mar 12, 2007 at 11:06:45AM +0900, Hideo Saito wrote: > I think that the following patch can avoid this problem by checking a > range of the value. Looks reasonable. Applied, thanks. |
From: Nobuhiro I. <he...@t-...> - 2007-03-12 05:25:33
|
Hi, all . This patch is support Splution Engine's PCMCIA . Please apply. -- Nobuhiro Iwamatsu E-Mail : he...@t-... GPG ID : 3170EBE9 Signed-off-by: Nobuhiro Iwamatsu <he...@t-...> diff --git a/arch/sh/boards/se/770x/setup.c b/arch/sh/boards/se/770x/setup.c index 45cbc36..dab5510 100644 --- a/arch/sh/boards/se/770x/setup.c +++ b/arch/sh/boards/se/770x/setup.c @@ -63,6 +63,31 @@ static void __init smsc_setup(char **cmdline_p) outb_p(CONFIG_EXIT, CONFIG_PORT); } + +static struct resource cf_ide_resources[] = { + [0] = { + .start = PA_MRSHPC_IO + 0x1f0, + .end = PA_MRSHPC_IO + 0x1f0 + 8, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PA_MRSHPC_IO + 0x1f0 + 0x206, + .end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = 7, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cf_ide_device = { + .name = "pata_platform", + .id = -1, + .num_resources = ARRAY_SIZE(cf_ide_resources), + .resource = cf_ide_resources, +}; + static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; static struct resource heartbeat_resources[] = { @@ -85,6 +110,7 @@ static struct platform_device heartbeat_device = { static struct platform_device *se_devices[] __initdata = { &heartbeat_device, + &cf_ide_device, }; static int __init se_devices_setup(void) |
From: Hideo S. <sa...@de...> - 2007-03-12 02:07:34
|
Hi Paul, When a SH7751R system includes a card that has wide range space like as graphics card, pci-pci bridge controller can't set correct address range used by the bridge to interconnect PCI buses. For example, when |*lower_limit| is 0xfd000000 and |bar_size| is 0x4000000, in the following program at arch/sh/drivers/pci/pci-auto.c, 0x0 is set in |bar_value|. pciauto_setup_bars() { ... bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size; ... *lower_limit = bar_value + bar_size; } As a result, 0x4000000 is set in |*lower_limit|, but this value is wrong. I think that the following patch can avoid this problem by checking a range of the value. --- arch/sh/drivers/pci/pci-auto.c.org Mon Feb 5 03:44:54 2007 +++ arch/sh/drivers/pci/pci-auto.c Mon Mar 12 11:04:21 2007 @@ -209,16 +209,22 @@ retry: goto retry; } } DBG(" unavailable -- skipping, value %x size %x\n", bar_value, bar_size); continue; } + if (bar_value < *lower_limit || (bar_value + bar_size) >= *upper_limit) { + DBG(" unavailable -- skipping, value %x size %x\n", + bar_value, bar_size); + continue; + } + #ifdef CONFIG_PCI_AUTO_UPDATE_RESOURCES /* Write it out and update our limit */ early_write_config_dword(hose, top_bus, current_bus, pci_devfn, bar, bar_value); #endif *lower_limit = bar_value + bar_size; |
From: Paul M. <le...@li...> - 2007-03-09 10:09:37
|
On Fri, Mar 09, 2007 at 09:39:54AM +0000, Kristoffer Ericson wrote: > Still getting those unaligned access issues. I've setup the setup.c to have > the proper cf_ide IO values but getting same error. > Current git should work for this case now that the PG_dcache_dirty bits have been reverted. It is quite interesting that you hit this on SH-3 though, this suggests that it's not actually a fault with the lazy write-back itself, but simply a missing write-back somewhere else that PG_mapped happens to paper over. > As soon as I get it working, I plan on start removing the PIO mapping so we > can get rid of io.c as Paul suggested. > You should be able to do that from the beginning. As long as pata_platform is capable of detecting the device and you're able to mount it, you're in reasonable shape as far as the I/O mappings are concerned. The only potential issue would be the access width, we've seen the ioread8() cause bus locks on early R7780RP-1 boards where it really does need to be a 16-bit access with the 8-bits masked. Looking at the hd64461 code, this should not be a problem. |
From: Kristoffer E. <kri...@ho...> - 2007-03-09 09:40:04
|
Still getting those unaligned access issues. I've setup the setup.c to have the proper cf_ide IO values but getting same error. Just want to get an idea where to look further since Im sure I've done correct. As soon as I get it working, I plan on start removing the PIO mapping so we can get rid of io.c as Paul suggested. Best wishes Kristoffer _________________________________________________________________ FREE pop-up blocking with the new MSN Toolbar - get it now! http://toolbar.msn.click-url.com/go/onm00200415ave/direct/01/ |
From: Nobuhiro I. <iwa...@ni...> - 2007-03-09 03:03:09
|
Hi , all . Add an RTC driver for Ricoh RS5C313 RTC chip. Please apply. regards, Nobuhiro Signed-off-by: Nobuhiro Iwamatsu <iwa...@ni...> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 95826b9..cc3c0b2 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -354,4 +354,10 @@ config RTC_DRV_V3020 This driver can also be built as a module. If so, the module will be called rtc-v3020. +config RTC_DRV_RS5C313 + tristate "Ricoh RS5C313" + depends on RTC_CLASS + help + If you say yes here you get support for the Ricoh RS5C313 RTC chips. + endmenu diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 92bfe1b..9af3129 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -38,3 +38,4 @@ obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max6902.o obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o obj-$(CONFIG_RTC_DRV_SH) += rtc-sh.o +obj-$(CONFIG_RTC_DRV_RS5C313) += rtc-rs5c313.o diff --git a/drivers/rtc/rtc-rs5c313.c b/drivers/rtc/rtc-rs5c313.c new file mode 100644 index 0000000..8751d2b --- /dev/null +++ b/drivers/rtc/rtc-rs5c313.c @@ -0,0 +1,408 @@ +/* + * Ricoh RS5C313 RTC device/driver + * Copyright (C) 2007 Nobuhiro Iwamatsu + * + * 2005-09-19 modifed by kogiidena + * + * Based on the old drivers/char/rs5c313_rtc.c by: + * Copyright (C) 2000 Philipp Rumpf <pr...@tu...> + * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka + * + * Based on code written by Paul Gortmaker. + * Copyright (C) 1996 Paul Gortmaker + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Based on other minimal char device drivers, like Alan's + * watchdog, Ted's random, etc. etc. + * + * 1.07 Paul Gortmaker. + * 1.08 Miquel van Smoorenburg: disallow certain things on the + * DEC Alpha as the CMOS clock is also used for other things. + * 1.09 Nikita Schmidt: epoch support and some Alpha cleanup. + * 1.09a Pete Zaitcev: Sun SPARC + * 1.09b Jeff Garzik: Modularize, init cleanup + * 1.09c Jeff Garzik: SMP cleanup + * 1.10 Paul Barton-Davis: add support for async I/O + * 1.10a Andrea Arcangeli: Alpha updates + * 1.10b Andrew Morton: SMP lock fix + * 1.10c Cesar Barros: SMP locking fixes and cleanup + * 1.10d Paul Gortmaker: delete paranoia check in rtc_exit + * 1.10e Maciej W. Rozycki: Handle DECstation's year weirdness. + * 1.11 Takashi Iwai: Kernel access functions + * rtc_register/rtc_unregister/rtc_control + * 1.11a Daniele Bellucci: Audit create_proc_read_entry in rtc_init + * 1.12 Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer + * CONFIG_HPET_EMULATE_RTC + * 1.13 Nobuhiro Iwamatsu: Updata driver. + */ + +#include <linux/module.h> +#include <linux/err.h> +#include <linux/rtc.h> +#include <linux/platform_device.h> +#include <linux/bcd.h> +#include <linux/delay.h> +#include <asm/io.h> + +#define DRV_NAME "rs5c313" +#define DRV_VERSION "1.13" + +#ifdef CONFIG_SH_LANDISK +/*****************************************************/ +/* LANDISK dependence part of RS5C313 */ +/*****************************************************/ + +#define SCSMR1 0xFFE00000 +#define SCSCR1 0xFFE00008 +#define SCSMR1_CA 0x80 +#define SCSCR1_CKE 0x03 +#define SCSPTR1 0xFFE0001C +#define SCSPTR1_EIO 0x80 +#define SCSPTR1_SPB1IO 0x08 +#define SCSPTR1_SPB1DT 0x04 +#define SCSPTR1_SPB0IO 0x02 +#define SCSPTR1_SPB0DT 0x01 + +#define SDA_OEN SCSPTR1_SPB1IO +#define SDA SCSPTR1_SPB1DT +#define SCL_OEN SCSPTR1_SPB0IO +#define SCL SCSPTR1_SPB0DT + +/* RICOH RS5C313 CE port */ +#define RS5C313_CE 0xB0000003 + +/* RICOH RS5C313 CE port bit */ +#define RS5C313_CE_RTCCE 0x02 + +/* SCSPTR1 data */ +unsigned char scsptr1_data; + +#define RS5C313_CEENABLE ctrl_outb(RS5C313_CE_RTCCE, RS5C313_CE); +#define RS5C313_CEDISABLE ctrl_outb(0x00, RS5C313_CE) +#define RS5C313_MISCOP ctrl_outb(0x02, 0xB0000008) + +static void rs5c313_init_port(void) +{ + /* Set SCK as I/O port and Initialize SCSPTR1 data & I/O port. */ + ctrl_outb(ctrl_inb(SCSMR1) & ~SCSMR1_CA, SCSMR1); + ctrl_outb(ctrl_inb(SCSCR1) & ~SCSCR1_CKE, SCSCR1); + + /* And Initialize SCL for RS5C313 clock */ + scsptr1_data = ctrl_inb(SCSPTR1) | SCL; /* SCL:H */ + ctrl_outb(scsptr1_data, SCSPTR1); + scsptr1_data = ctrl_inb(SCSPTR1) | SCL_OEN; /* SCL output enable */ + ctrl_outb(scsptr1_data, SCSPTR1); + RS5C313_CEDISABLE; /* CE:L */ +} + +static void rs5c313_write_data(unsigned char data) +{ + int i = 0; + + for(i = 0; i < 8; i++){ + /* SDA:Write Data */ + scsptr1_data = (scsptr1_data & ~SDA) + | ((((0x80 >> i) & data) >> (7 - i)) << 2); + ctrl_outb(scsptr1_data, SCSPTR1); + if(i == 0){ + scsptr1_data |= SDA_OEN; /* SDA:output enable */ + ctrl_outb(scsptr1_data, SCSPTR1); + } + ndelay(700); + scsptr1_data &= ~SCL; /* SCL:L */ + ctrl_outb(scsptr1_data, SCSPTR1); + ndelay(700); + scsptr1_data |= SCL; /* SCL:H */ + ctrl_outb(scsptr1_data, SCSPTR1); + } + + scsptr1_data &= ~SDA_OEN; /* SDA:output disable */ + ctrl_outb(scsptr1_data, SCSPTR1); + +} + +static unsigned char rs5c313_read_data(void) +{ + int i; + unsigned char data = 0; + + for(i = 0; i < 8; i++){ + ndelay(700); + /* SDA:Read Data */ + data |= ((ctrl_inb(SCSPTR1) & SDA) >> 2) << (7 - i); + scsptr1_data &= ~SCL; /* SCL:L */ + ctrl_outb(scsptr1_data, SCSPTR1); + ndelay(700); + scsptr1_data |= SCL; /* SCL:H */ + ctrl_outb(scsptr1_data, SCSPTR1); + } + return data & 0x0F; +} + +#endif /* CONFIG_SH_LANDISK */ + +/*****************************************************/ +/* machine independence part of RS5C313 */ +/*****************************************************/ + +/* RICOH RS5C313 address */ +#define RS5C313_ADDR_SEC 0x00 +#define RS5C313_ADDR_SEC10 0x01 +#define RS5C313_ADDR_MIN 0x02 +#define RS5C313_ADDR_MIN10 0x03 +#define RS5C313_ADDR_HOUR 0x04 +#define RS5C313_ADDR_HOUR10 0x05 +#define RS5C313_ADDR_WEEK 0x06 +#define RS5C313_ADDR_INTINTVREG 0x07 +#define RS5C313_ADDR_DAY 0x08 +#define RS5C313_ADDR_DAY10 0x09 +#define RS5C313_ADDR_MON 0x0A +#define RS5C313_ADDR_MON10 0x0B +#define RS5C313_ADDR_YEAR 0x0C +#define RS5C313_ADDR_YEAR10 0x0D +#define RS5C313_ADDR_CNTREG 0x0E +#define RS5C313_ADDR_TESTREG 0x0F + +/* RICOH RS5C313 control register */ +#define RS5C313_CNTREG_ADJ_BSY 0x01 +#define RS5C313_CNTREG_WTEN_XSTP 0x02 +#define RS5C313_CNTREG_12_24 0x04 +#define RS5C313_CNTREG_CTFG 0x08 + +/* RICOH RS5C313 test register */ +#define RS5C313_TESTREG_TEST 0x01 + +/* RICOH RS5C313 control bit */ +#define RS5C313_CNTBIT_READ 0x40 +#define RS5C313_CNTBIT_AD 0x20 +#define RS5C313_CNTBIT_DT 0x10 + +static unsigned char rs5c313_read_reg(unsigned char addr) +{ + + rs5c313_write_data(addr | RS5C313_CNTBIT_READ | RS5C313_CNTBIT_AD); + return rs5c313_read_data(); + +} + +static void rs5c313_write_reg(unsigned char addr, unsigned char data) +{ + data &= 0x0f; + rs5c313_write_data(addr | RS5C313_CNTBIT_AD); + rs5c313_write_data(data | RS5C313_CNTBIT_DT); + return; +} + +#define rs5c313_read_cntreg() rs5c313_read_reg(RS5C313_ADDR_CNTREG) +#define rs5c313_write_cntreg(data) rs5c313_write_reg(RS5C313_ADDR_CNTREG,data) +#define rs5c313_write_intintvreg(data) rs5c313_write_reg(RS5C313_ADDR_INTINTVREG,data) + +static int rs5c313_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + int data = 0; + + while( 1 ){ + RS5C313_CEENABLE; /* CE:H */ + + /* Initialize control reg. 24 hour */ + rs5c313_write_cntreg(0x04); + + if(!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY)){ + break; + } + + RS5C313_CEDISABLE; + ndelay(700); /* CE:L */ + + } + + data = rs5c313_read_reg(RS5C313_ADDR_SEC); + data |= (rs5c313_read_reg(RS5C313_ADDR_SEC10) << 4); + tm->tm_sec = BCD2BIN(data); + + data = rs5c313_read_reg(RS5C313_ADDR_MIN); + data |= (rs5c313_read_reg(RS5C313_ADDR_MIN10) << 4); + tm->tm_min = BCD2BIN(data); + + data = rs5c313_read_reg(RS5C313_ADDR_HOUR); + data |= (rs5c313_read_reg(RS5C313_ADDR_HOUR10) << 4); + tm->tm_hour = BCD2BIN(data); + + data = rs5c313_read_reg(RS5C313_ADDR_DAY); + data |= (rs5c313_read_reg(RS5C313_ADDR_DAY10) << 4); + tm->tm_mday = BCD2BIN(data); + + data = rs5c313_read_reg(RS5C313_ADDR_MON); + data |= (rs5c313_read_reg(RS5C313_ADDR_MON10) << 4); + tm->tm_mon = BCD2BIN(data) - 1; + + data = rs5c313_read_reg(RS5C313_ADDR_YEAR); + data |= (rs5c313_read_reg(RS5C313_ADDR_YEAR10) << 4); + tm->tm_year = BCD2BIN(data); + if(tm->tm_year < 70){ + tm->tm_year += 100; + } + + data = rs5c313_read_reg(RS5C313_ADDR_WEEK); + tm->tm_wday = BCD2BIN(data); + + RS5C313_CEDISABLE; + ndelay(700); /* CE:L */ + + return 0; +} + +static int rs5c313_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + + int data = 0; + + /* busy check. */ + while( 1 ){ + RS5C313_CEENABLE; /* CE:H */ + + /* Initiatlize control reg. 24 hour */ + rs5c313_write_cntreg(0x04); + + if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY)){ + break; + } + RS5C313_MISCOP; + RS5C313_CEDISABLE; + ndelay(700); /* CE:L */ + } + + data = BIN2BCD(tm->tm_sec); + rs5c313_write_reg(RS5C313_ADDR_SEC, data); + rs5c313_write_reg(RS5C313_ADDR_SEC10, (data >> 4)); + + data = BIN2BCD(tm->tm_min); + rs5c313_write_reg(RS5C313_ADDR_MIN, data ); + rs5c313_write_reg(RS5C313_ADDR_MIN10, (data >> 4)); + + data = BIN2BCD(tm->tm_hour); + rs5c313_write_reg(RS5C313_ADDR_HOUR, data); + rs5c313_write_reg(RS5C313_ADDR_HOUR10, (data >> 4)); + + data = BIN2BCD(tm->tm_mday); + rs5c313_write_reg(RS5C313_ADDR_DAY, data); + rs5c313_write_reg(RS5C313_ADDR_DAY10, (data>> 4)); + + data = BIN2BCD(tm->tm_mon + 1); + rs5c313_write_reg(RS5C313_ADDR_MON, data); + rs5c313_write_reg(RS5C313_ADDR_MON10, (data >> 4)); + + data = BIN2BCD(tm->tm_year % 100); + rs5c313_write_reg(RS5C313_ADDR_YEAR, data); + rs5c313_write_reg(RS5C313_ADDR_YEAR10, (data >> 4)); + + data = BIN2BCD(tm->tm_wday); + rs5c313_write_reg(RS5C313_ADDR_WEEK, data); + + RS5C313_CEDISABLE; /* CE:H */ + ndelay(700); + + return 0; +} + +static void rs5c313_check_xstp_bit(void) +{ + struct rtc_time tm; + + RS5C313_CEENABLE; /* CE:H */ + if(rs5c313_read_cntreg() & RS5C313_CNTREG_WTEN_XSTP){ + /* INT interval reg. OFF */ + rs5c313_write_intintvreg(0x00); + /* Initialize control reg. 24 hour & adjust */ + rs5c313_write_cntreg(0x07); + + /* busy check. */ + while(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY){ + RS5C313_MISCOP; + } + + memset( &tm , 0 , sizeof( struct rtc_time )); + tm.tm_mday = 1; + tm.tm_mon = 1; + + rs5c313_rtc_set_time(NULL, &tm); + printk(KERN_ERR + "RICHO RS5C313: invalid value, resetting to 1 Jan 2000\n"); + + } + RS5C313_CEDISABLE; + ndelay(700); /* CE:L */ + +} + +static const struct rtc_class_ops rs5c313_rtc_ops = { + .read_time = rs5c313_rtc_read_time, + .set_time = rs5c313_rtc_set_time, +}; + +static int rs5c313_rtc_probe(struct platform_device *pdev) +{ + int err = 0 ; + struct rtc_device *rtc + = rtc_device_register("rs5c313", + &pdev->dev, + &rs5c313_rtc_ops, + THIS_MODULE); + if(IS_ERR( rtc )){ + err = PTR_ERR( rtc ); + return err; + } + + platform_set_drvdata( pdev, rtc ); + + return err ; +} + +static int __devexit rs5c313_rtc_remove(struct platform_device *pdev) +{ + struct rtc_device *rtc = platform_get_drvdata( pdev ); + + rtc_device_unregister( rtc ); + + return 0; +} + +static struct platform_driver rs5c313_rtc_platform_driver = { + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, + .probe = rs5c313_rtc_probe, + .remove = __devexit_p( rs5c313_rtc_remove ), +}; + +static int __init rs5c313_rtc_init(void) +{ + int err = 0; + + if((err = platform_driver_register( &rs5c313_rtc_platform_driver ))){ + return err; + } + + rs5c313_init_port(); + rs5c313_check_xstp_bit(); + + return err; +} + +static void __exit rs5c313_rtc_exit(void) +{ + platform_driver_unregister( &rs5c313_rtc_platform_driver ); +} + +module_init(rs5c313_rtc_init); +module_exit(rs5c313_rtc_exit); + +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("kogiidena , Nobuhiro Iwamatsu <iwa...@ni...>"); +MODULE_DESCRIPTION("Ricoh RS5C313 RTC device driver"); +MODULE_LICENSE("GPL"); + -- Nobuhiro Iwamatsu E-Mail : iwa...@ni... GPG ID : 3170EBE9 |
From: Paul M. <le...@li...> - 2007-03-07 16:10:03
|
On Wed, Mar 07, 2007 at 09:33:50PM +0530, Reddy Raja wrote: > _______________________________________________ > linuxsh-dev mailing list > lin...@li... > https://lists.sourceforge.net/lists/listinfo/linuxsh-dev These instructions are at the bottom of every mail sent to the list for a reason.. Somehow you managed to get yourself subscribed, the same approach works for unsubscribing, too. |
From: Reddy R. <are...@gm...> - 2007-03-07 16:03:57
|
From: Paul M. <le...@li...> - 2007-03-05 11:01:37
|
On Tue, Feb 20, 2007 at 02:43:12PM +0900, Hideo Saito wrote: > On Tue, 20 Feb 2007 10:48:12 +0900, Paul Mundt <le...@li...> wrote: > > Can you move your __flush_wback_region() in to the else path in > > flush_dcache_page() in arch/sh/mm/cache-sh4.c and see if the problem > > persists? > > I backed out the change for install_arg_page() at fs/exec.c and applied > following patch and tested it using appended test program. I can not > see this problem by my test. > Now that we've reverted to PG_mapped, can you try current git and verify whether your test program causes any problems for you or not? I've not been able to reproduce your crash.. |
From: Manuel L. <ma...@ro...> - 2007-03-05 08:59:41
|
Hello Paul, > > PCMCIA is (again) broken, this time on 2.6.21-rc1. > > After doing a p3_ioremap() of AREA5/6, accesses to it > > will hang (a simple CIS dump for example simply hangs > > on the first readb()). Kernel is not dead (sysrq-t from usb kbd works). > > > > X breaks too, btw. It just sits there and consumes 80% CPU. > > > > Reverting "lazy dcache writeback optimizations" fixes both issues on > > my SH7760. > > > Can you verify whether this works? > > diff --git a/arch/sh/mm/tlb-flush.c b/arch/sh/mm/tlb-flush.c > index d2f7b4a..927414f 100644 > --- a/arch/sh/mm/tlb-flush.c > +++ b/arch/sh/mm/tlb-flush.c > @@ -160,7 +160,7 @@ void update_mmu_cache(struct vm_area_struct *vma, > unsigned long phys = pte_val(pte) & PTE_PHYS_MASK; > int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags); > > - if (dirty) > + if (dirty || mapping_mapped(mapping)) > __flush_wback_region((void *)P1SEGADDR(phys), > PAGE_SIZE); > } Unfortunately not, same symptoms as described above. -- ml. |
From: Paul M. <le...@li...> - 2007-03-05 08:06:38
|
On Wed, Feb 21, 2007 at 01:38:56PM +0100, Manuel Lauss wrote: > PCMCIA is (again) broken, this time on 2.6.21-rc1. > After doing a p3_ioremap() of AREA5/6, accesses to it > will hang (a simple CIS dump for example simply hangs > on the first readb()). Kernel is not dead (sysrq-t from usb kbd works). > > X breaks too, btw. It just sits there and consumes 80% CPU. > > Reverting "lazy dcache writeback optimizations" fixes both issues on > my SH7760. > Can you verify whether this works? diff --git a/arch/sh/mm/tlb-flush.c b/arch/sh/mm/tlb-flush.c index d2f7b4a..927414f 100644 --- a/arch/sh/mm/tlb-flush.c +++ b/arch/sh/mm/tlb-flush.c @@ -160,7 +160,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long phys = pte_val(pte) & PTE_PHYS_MASK; int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags); - if (dirty) + if (dirty || mapping_mapped(mapping)) __flush_wback_region((void *)P1SEGADDR(phys), PAGE_SIZE); } |
From: Paul M. <le...@li...> - 2007-03-02 13:42:00
|
On Fri, Mar 02, 2007 at 05:00:51AM -0800, Cmmn Ml wrote: > We are trying to build a SH3 7705 based device which runs linux 2.6 > kernel. When we try to identify the most closest port to our board we > found that there are two boards. > > > 1. Renesas EDOSK7705 > 2. (Solution Engine) SE7705 > > > However we found that the build for EDOSK7705 is broaken in linux > 2.6.16 (after applying the SH linux stable patch relavant to this > kernel version sh--stable--2.6.16). But if we use the SE7705 > configuration with processor as SH7705 it builds without any error. > Further we found that files relavant to SE/770x have conditional > compilation to SH7705. Unfortunately we could not locate any board with > SE7705 (Solution Engine for SH7705). > First, why are you using such an old kernel? Please use current git, or at least 2.6.20. SH7705 has not had a lot of attention in some time, so it's quite possibly broken. The EDOSK7705 board will likely be removed unless someone expresses an interest in it in the near future. > Can you / one of you tell me > > 1. Is there a Solution Engine board targeting SH7705? > There is a 7705 Solution Engine, yes. I'm not aware of anyone actively working on it, though. The SH7705 part itself has been obsoleted for some time, so I don't expect this to change much in the future either. |
From: Cmmn Ml <cm...@ya...> - 2007-03-02 13:01:14
|
Hello=0A =0AWe are trying to build a SH3 7705 based device which runs linux= 2.6 kernel. When we try to identify the most closest port to our board we = found that there are two boards.=0A =0ARenesas EDOSK7705 =0A(Solution Engin= e) SE7705 =0A =0AHowever we found that the build for EDOSK7705 is broaken i= n linux 2.6.16 (after applying the SH linux stable patch relavant to this k= ernel version sh--stable--2.6.16). But if we use the SE7705 configuration w= ith processor as SH7705 it builds without any error. Further we found that = files relavant to SE/770x have conditional compilation to SH7705. Unfortuna= tely we could not locate any board with SE7705 (Solution Engine for SH7705)= .=0A =0ACan you / one of you tell me =0A1. Is there a Solution Engine= board targeting SH7705?=0A2. If so can one of you point me to the we= b site for this so I can find more details about its designs? =0A =0A =0ATh= ank you in advance=0A=0ACmmn=0A=0A=0A =0A__________________________________= __________________________________________________=0ANeed a quick answer? G= et one in minutes from people who know.=0AAsk your question on www.Answers.= yahoo.com |
From: Kristoffer E. <kri...@ho...> - 2007-03-02 11:30:14
|
Big thanks, I'll sort it out later today. >From: Paul Mundt <le...@li...> >To: Manuel Lauss <ma...@ro...> >CC: Kristoffer Ericson ><kri...@ho...>,lin...@li... >Subject: Re: PATA Patch for Hp6xx >Date: Fri, 2 Mar 2007 15:30:14 +0900 > >On Fri, Mar 02, 2007 at 07:06:09AM +0100, Manuel Lauss wrote: > > On Thu, Mar 01, 2007 at 11:43:28PM +0000, Kristoffer Ericson wrote: > > > + .start = 0x1f0 + 0x206, <------------ >Error? > > > + .end = 0x1f0 +8 + 0x206 + 8, > > > + .flags = IORESOURCE_IO, > > > > 3f6 is correct. .end should be 3f7. (have alook at > > arch/sh/cchips/hd6446x/hd64461/io.c::PORT2ADDR()). > > > > Maybe you could even use the "real" MMIO addresses of > > the hd64461 pcmcia0 region (0xb50001f0), and one day get rid of > > that ugly io.c file altogether... > > >Indeed, and in this case, there's really no reason _not_ to use the MMIO >address. The reason some folks were using the PIO addresses before were >as a lame way to take care of port shifting, and this is really the wrong >way to go about it. If there's a real inability to do an access of that >size, then it's something the driver has to deal with, we shouldn't be >papering over it in the machvec. > >I would say rip out the HD64461 entries from the machvec entirely and see >what falls out. I imagine PCMCIA will be a problem, but this needs an >overhaul for the hardirq changes anyways, and then we're likely left with >something much smaller that we can push in as an MFD driver, and kill off >the rest of the cchip mess. > >The io.c's have always been utter crap, the sooner we can kill off the >outstanding ones, the better. _________________________________________________________________ Express yourself instantly with MSN Messenger! Download today it's FREE! http://messenger.msn.click-url.com/go/onm00200471ave/direct/01/ |