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From: Markus B. <sup...@go...> - 2007-07-23 07:16:14
|
Hello Paul,
this patch adds support for the Magic Panel Release 2 SH7720 board to 2.6.22.
The board is currently under development and not publicly available. We
thought that it is better to have a template than nothing to get the SH7720
running on another board. Maybe somebody with a Solution Engine Light (MS7720RP01)
volunteers to write a BSP for this board as a template.
Signed-off by: Markus Brunner <sup...@gm...>
Signed-off by: Mark Jonas <to...@gm...>
---
arch/sh/Kconfig | 11
arch/sh/Makefile | 1
arch/sh/boards/magicpanelr2/Makefile | 5
arch/sh/boards/magicpanelr2/irq.c | 80 ++
arch/sh/boards/magicpanelr2/setup.c | 305 +++++++++
arch/sh/configs/magicpanelr2_defconfig | 1016 +++++++++++++++++++++++++++++++++
arch/sh/drivers/heartbeat.c | 4
arch/sh/tools/mach-types | 1
include/asm-sh/magicpanelr2.h | 131 ++++
9 files changed, 1554 insertions(+)
diff -upNr linux-2.6.22-rc7-mod-CPU/arch/sh/boards/magicpanelr2/irq.c linux-2.6.22-rc7-mod/arch/sh/boards/magicpanelr2/irq.c
--- linux-2.6.22-rc7-mod-CPU/arch/sh/boards/magicpanelr2/irq.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.22-rc7-mod/arch/sh/boards/magicpanelr2/irq.c 2007-07-20 18:13:51.000000000 +0200
@@ -0,0 +1,80 @@
+/*
+ * linux/arch/sh/boards/magicpanel/irq.c
+ *
+ * Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ * Magic Panel Release 2 board specific irq setup
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/magicpanelr2.h>
+
+static struct ipr_data mpr2_ipr_map[] = {
+ /* IRQ, IPR-idx, shift, priority */
+ { 32, 2, 0, 13 }, /* IRQ0 CAN1 */
+ { 33, 2, 4, 13 }, /* IRQ1 CAN2 */
+ { 34, 2, 8, 13 }, /* IRQ2 CAN3 */
+ { 35, 2, 12, 6 }, /* IRQ3 SMSC9115 */
+ { 84, 7, 12, 14 }, /* PINTA (FLASH_READY, /PWR1, /PWR2) */
+};
+
+/*
+ * Initialize IRQ setting
+ */
+void __initmv init_mpr2_IRQ(void)
+{
+
+
+#if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 1
+
+ ctrl_outw(ICR1_IRQ3_LOW | ICR1_IRQ2_LOW | ICR1_IRQ1_FALL | \
+ ICR1_IRQ0_FALL, INTC_ICR1);
+ ctrl_outw(0x0000, INTC_ICR2);
+
+ /* PINT4 and PINT5 are used as independent interrupt pins
+ * PINT4: CAN2_IRQ (low level sensitive)
+ * PINT5: CAN3_IRQ (low level sensitive)
+ */
+ /* set polarity of PINT interrupts to low level */
+ CLRBITS_OUTW(ICR2_PINT4S | ICR2_PINT5S, ICR2);
+ /* enable PINT interrupts */
+ SETBITS_OUTW(PINTER_PINT4E | PINTER_PINT5E, PINTER);
+
+#elif ((CONFIG_SH_MAGIC_PANEL_R2_VERSION >= 2) && \
+ (CONFIG_SH_MAGIC_PANEL_R2_VERSION <= 3))
+ /* IRQ0..3 are independent interrupt pins
+ * IRQ5: BUSY - touch screen - (falling edge sensitive)
+ * IRQ4: PENIRQ - touch screen - (rising edge sensitive)
+ * IRQ3: LAN_IRQ - Ethernet - (low level sensitive)
+ * IRQ2: CAN3_IRQ - CAN - (low level sensitive)
+ * IRQ1: CAN2_IRQ - CAN - (low level sensitive)
+ * IRQ0: CAN1_IRQ - CAN - (low level sensitive)
+ */
+ ctrl_outw(ICR1_IRQ5_FALL | ICR1_IRQ4_RISE | ICR1_IRQ3_LOW | \
+ ICR1_IRQ2_LOW | ICR1_IRQ1_LOW | ICR1_IRQ0_LOW, INTC_ICR1);
+
+
+ /* PINT4, PINT6 and PINT7 are used as independent interrupt pins
+ * PINT7: /PWR2 (low level sensitive)
+ * PINT6: /PWR1 (low level sensitive)
+ * PINT4: FLASH_READY (high level sensitive)
+ */
+ /* set polarity of PINT interrupts to low level */
+ CLRBITS_OUTW((ICR2_PINT7S | ICR2_PINT6S), INTC_ICR2);
+ /* set polarity of PINT interrupts to high level */
+ SETBITS_OUTW(ICR2_PINT4S, INTC_ICR2);
+ /* enable PINT interrupts */
+ ctrl_outw(PINTER_PINT7E | PINTER_PINT6E | PINTER_PINT4E, PINTER);
+#endif
+
+
+ make_ipr_irq(mpr2_ipr_map, ARRAY_SIZE(mpr2_ipr_map));
+}
+
+
diff -upNr linux-2.6.22-rc7-mod-CPU/arch/sh/boards/magicpanelr2/Makefile linux-2.6.22-rc7-mod/arch/sh/boards/magicpanelr2/Makefile
--- linux-2.6.22-rc7-mod-CPU/arch/sh/boards/magicpanelr2/Makefile 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.22-rc7-mod/arch/sh/boards/magicpanelr2/Makefile 2007-07-20 18:14:51.000000000 +0200
@@ -0,0 +1,5 @@
+#
+# Makefile for the Magic Panel specific parts
+#
+
+obj-y := setup.o irq.o
\ No newline at end of file
diff -upNr linux-2.6.22-rc7-mod-CPU/arch/sh/boards/magicpanelr2/setup.c linux-2.6.22-rc7-mod/arch/sh/boards/magicpanelr2/setup.c
--- linux-2.6.22-rc7-mod-CPU/arch/sh/boards/magicpanelr2/setup.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.22-rc7-mod/arch/sh/boards/magicpanelr2/setup.c 2007-07-20 16:30:40.000000000 +0200
@@ -0,0 +1,305 @@
+/*
+ * linux/arch/sh/boards/magicpanel/setup.c
+ *
+ * Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ * Magic Panel Release 2 board setup
+ *
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/autoconf.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+
+#include <linux/hdreg.h>
+#include <linux/ide.h>
+#include <asm/magicpanelr2.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+
+extern void init_mpr2_IRQ(void);
+
+static void __initmv setup_chip_select(void);
+static int __initmv ethernet_reset_finished(void);
+static void __initmv setup_port_multiplexing(void);
+
+#define LAN9115_READY (ctrl_inl(0xA8000084UL) & 0x00000001UL)
+
+/* Wait until reset finished. Timeout is 100ms. */
+static int __initmv ethernet_reset_finished(void)
+{
+ int i;
+
+ if (LAN9115_READY) {
+ return 1;
+ }
+
+ for (i = 0; i < 10; ++i) {
+ mdelay(10);
+ if (LAN9115_READY) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+static int __initmv reset_ethernet(void)
+{
+ /* PMDR: LAN_RESET=on */
+ CLRBITS_OUTB(0x10, PORT_PMDR);
+
+ udelay(200);
+
+ /* PMDR: LAN_RESET=off */
+ SETBITS_OUTB(0x10, PORT_PMDR);
+}
+
+static void __initmv setup_chip_select(void)
+{
+ /* CS2: LAN (0x08000000 - 0x0bffffff) */
+ /* no idle cycles, normal space, 8 bit data bus */
+ ctrl_outl(0x36db0400, CS2BCR);
+ /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+ ctrl_outl(0x000003c0, CS2WCR);
+
+ /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */
+ /* no idle cycles, normal space, 8 bit data bus */
+ ctrl_outl(0x00000200, CS4BCR);
+ /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+ ctrl_outl(0x00100981, CS4WCR);
+
+ /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */
+ /* no idle cycles, normal space, 8 bit data bus */
+ ctrl_outl(0x00000200, CS5ABCR);
+ /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+ ctrl_outl(0x00100981, CS5AWCR);
+
+ /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */
+ /* no idle cycles, normal space, 8 bit data bus */
+ ctrl_outl(0x00000200, CS5BBCR);
+ /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+ ctrl_outl(0x00100981, CS5BWCR);
+
+ /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */
+ /* no idle cycles, normal space, 8 bit data bus */
+ ctrl_outl(0x00000200, CS6ABCR);
+ /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
+ ctrl_outl(0x001009C1, CS6AWCR);
+}
+
+static void __initmv setup_port_multiplexing(void)
+{
+ /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
+ * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1);
+ */
+ ctrl_outw(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */
+
+ /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
+ * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0);
+ */
+ ctrl_outw(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */
+
+ /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
+ * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0;
+ */
+ ctrl_outw(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */
+
+ /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
+ * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0);
+ */
+ ctrl_outw(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */
+
+ /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
+ * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM;
+ */
+ ctrl_outw(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */
+
+ /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
+ * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc);
+ */
+ ctrl_outw(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */
+
+ /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2);
+ * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9);
+ */
+ ctrl_outw(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */
+
+ /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
+ * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR;
+ */
+ ctrl_outw(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */
+
+ /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
+ * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC;
+ */
+ ctrl_outw(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */
+
+ /* K7 (x); K6 (x); K5 (x); K4 (x);
+ * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY)
+ */
+ ctrl_outw(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */
+
+ /* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
+ * L3 TCK; L2 (x); L1 (x); L0 (x);
+ */
+ ctrl_outw(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */
+
+ /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED);
+ * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL);
+ * M1 CS5B(CAN3_CS); M0 GPI+(nc);
+ */
+ ctrl_outw(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */
+
+ /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit,
+ * LAN_RESET=off, BUZZER=off, LCD_BL=off
+ */
+ #if (CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2)
+ ctrl_outb(0x30, PORT_PMDR);
+ #elif (CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3)
+ ctrl_outb(0xF0, PORT_PMDR);
+ #else
+ #error Unknown revision of PLATFORM_MP_R2
+ #endif
+
+ /* P7 (x); P6 (x); P5 (x);
+ * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);
+ * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ)
+ */
+ ctrl_outw(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */
+ ctrl_outb(0x10, PORT_PPDR);
+
+ /* R7 A25; R6 A24; R5 A23; R4 A22;
+ * R3 A21; R2 A20; R1 A19; R0 A0;
+ */
+ ctrl_outw(0x0000, PORT_PRCR); /* 00 00 00 00 00 00 00 00 */
+
+ /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
+ * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK;
+ */
+ ctrl_outw(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */
+
+ /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
+ * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG)
+ */
+ ctrl_outw(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */
+
+ /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
+ * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK;
+ */
+ ctrl_outw(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */
+
+ /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
+ * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT);
+ */
+ ctrl_outw(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */
+}
+
+static void __initmv mpr2_setup(char **cmdline_p)
+{
+ __set_io_port_base(0xa0000000);
+
+ /* set Pin Select Register A:
+ * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2,
+ * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND
+ */
+ ctrl_outw(0xAABC, PORT_PSELA);
+ /* set Pin Select Register B:
+ * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC,
+ * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved
+ */
+ ctrl_outw(0x3C00, PORT_PSELB);
+ /* set Pin Select Register C:
+ * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved
+ */
+ ctrl_outw(0x0000, PORT_PSELC);
+ /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK,
+ * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved
+ */
+ ctrl_outw(0x0000, PORT_PSELD);
+ /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */
+ ctrl_outw(0x0101, PORT_UTRCTL);
+ /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */
+ ctrl_outw(0xA5C0, PORT_UCLKCR_W);
+
+ setup_chip_select();
+
+ setup_port_multiplexing();
+
+ reset_ethernet();
+
+ printk(KERN_INFO "%s A.%i\n", get_system_type(),
+ CONFIG_SH_MAGIC_PANEL_R2_VERSION);
+
+ if (ethernet_reset_finished() == 0) {
+ printk(KERN_WARNING "Ethernet not ready\n");
+ }
+}
+
+static struct resource smc911x_resources[] = {
+ [0] = {
+ .start = 0xa8000000,
+ .end = 0xabffffff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 35,
+ .end = 35,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device smc911x_device = {
+ .name = "smc911x",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(smc911x_resources),
+ .resource = smc911x_resources,
+};
+
+static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+
+static struct resource heartbeat_resources[] = {
+ [0] = {
+ .start = PA_LED,
+ .end = PA_LED + ARRAY_SIZE(heartbeat_bit_pos) - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device heartbeat_device = {
+ .name = "heartbeat",
+ .id = -1,
+ .dev = {
+ .platform_data = heartbeat_bit_pos,
+ },
+ .num_resources = ARRAY_SIZE(heartbeat_resources),
+ .resource = heartbeat_resources,
+};
+
+static struct platform_device *mpr2_devices[] __initdata = {
+ &heartbeat_device,
+ &smc911x_device,
+};
+
+static int __init mpr2_devices_setup(void)
+{
+ return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices));
+}
+__initcall(mpr2_devices_setup);
+
+/*
+ * The Machine Vector
+ */
+
+struct sh_machine_vector mv_mpr2 __initmv = {
+ .mv_name = "Magic Panel Release 2",
+ .mv_setup = mpr2_setup,
+ .mv_nr_irqs = 112,
+ .mv_init_irq = init_mpr2_IRQ,
+};
+ALIAS_MV(mpr2)
diff -upNr linux-2.6.22-rc7-mod-CPU/arch/sh/configs/magicpanelr2_defconfig linux-2.6.22-rc7-mod/arch/sh/configs/magicpanelr2_defconfig
--- linux-2.6.22-rc7-mod-CPU/arch/sh/configs/magicpanelr2_defconfig 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.22-rc7-mod/arch/sh/configs/magicpanelr2_defconfig 2007-07-20 16:55:25.000000000 +0200
@@ -0,0 +1,1016 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.22-rc7
+# Fri Jul 20 16:54:11 2007
+#
+CONFIG_SUPERH=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_UTS_NS is not set
+CONFIG_AUDIT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+
+#
+# Block layer
+#
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+
+#
+# System type
+#
+# CONFIG_SH_SOLUTION_ENGINE is not set
+# CONFIG_SH_7722_SOLUTION_ENGINE is not set
+# CONFIG_SH_7751_SOLUTION_ENGINE is not set
+# CONFIG_SH_7780_SOLUTION_ENGINE is not set
+# CONFIG_SH_7300_SOLUTION_ENGINE is not set
+# CONFIG_SH_7343_SOLUTION_ENGINE is not set
+# CONFIG_SH_73180_SOLUTION_ENGINE is not set
+# CONFIG_SH_7751_SYSTEMH is not set
+# CONFIG_SH_HP6XX is not set
+# CONFIG_SH_SATURN is not set
+# CONFIG_SH_DREAMCAST is not set
+# CONFIG_SH_MPC1211 is not set
+# CONFIG_SH_SH03 is not set
+# CONFIG_SH_SECUREEDGE5410 is not set
+# CONFIG_SH_HS7751RVOIP is not set
+# CONFIG_SH_7710VOIPGW is not set
+# CONFIG_SH_RTS7751R2D is not set
+# CONFIG_SH_HIGHLANDER is not set
+# CONFIG_SH_EDOSK7705 is not set
+# CONFIG_SH_SH4202_MICRODEV is not set
+# CONFIG_SH_LANDISK is not set
+# CONFIG_SH_TITAN is not set
+# CONFIG_SH_SHMIN is not set
+# CONFIG_SH_7206_SOLUTION_ENGINE is not set
+# CONFIG_SH_7619_SOLUTION_ENGINE is not set
+# CONFIG_SH_LBOX_RE2 is not set
+CONFIG_SH_MAGIC_PANEL_R2=y
+# CONFIG_SH_UNKNOWN is not set
+CONFIG_SH_MAGIC_PANEL_R2_VERSION=3
+
+#
+# Processor selection
+#
+CONFIG_CPU_SH3=y
+
+#
+# SH-2 Processor Support
+#
+# CONFIG_CPU_SUBTYPE_SH7604 is not set
+# CONFIG_CPU_SUBTYPE_SH7619 is not set
+
+#
+# SH-2A Processor Support
+#
+# CONFIG_CPU_SUBTYPE_SH7206 is not set
+
+#
+# SH-3 Processor Support
+#
+# CONFIG_CPU_SUBTYPE_SH7300 is not set
+# CONFIG_CPU_SUBTYPE_SH7705 is not set
+# CONFIG_CPU_SUBTYPE_SH7706 is not set
+# CONFIG_CPU_SUBTYPE_SH7707 is not set
+# CONFIG_CPU_SUBTYPE_SH7708 is not set
+# CONFIG_CPU_SUBTYPE_SH7709 is not set
+# CONFIG_CPU_SUBTYPE_SH7710 is not set
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+CONFIG_CPU_SUBTYPE_SH7720=y
+
+#
+# SH-4 Processor Support
+#
+# CONFIG_CPU_SUBTYPE_SH7750 is not set
+# CONFIG_CPU_SUBTYPE_SH7091 is not set
+# CONFIG_CPU_SUBTYPE_SH7750R is not set
+# CONFIG_CPU_SUBTYPE_SH7750S is not set
+# CONFIG_CPU_SUBTYPE_SH7751 is not set
+# CONFIG_CPU_SUBTYPE_SH7751R is not set
+# CONFIG_CPU_SUBTYPE_SH7760 is not set
+# CONFIG_CPU_SUBTYPE_SH4_202 is not set
+
+#
+# ST40 Processor Support
+#
+# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
+# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
+
+#
+# SH-4A Processor Support
+#
+# CONFIG_CPU_SUBTYPE_SH7770 is not set
+# CONFIG_CPU_SUBTYPE_SH7780 is not set
+# CONFIG_CPU_SUBTYPE_SH7785 is not set
+
+#
+# SH4AL-DSP Processor Support
+#
+# CONFIG_CPU_SUBTYPE_SH73180 is not set
+# CONFIG_CPU_SUBTYPE_SH7343 is not set
+# CONFIG_CPU_SUBTYPE_SH7722 is not set
+
+#
+# Memory management options
+#
+CONFIG_QUICKLIST=y
+CONFIG_MMU=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_MEMORY_START=0x0C000000
+CONFIG_MEMORY_SIZE=0x03F00000
+CONFIG_VSYSCALL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+
+#
+# Cache configuration
+#
+# CONFIG_SH_DIRECT_MAPPED is not set
+# CONFIG_SH_WRITETHROUGH is not set
+# CONFIG_SH_OCRAM is not set
+
+#
+# Processor features
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+# CONFIG_SH_FPU_EMU is not set
+CONFIG_SH_DSP=y
+CONFIG_SH_ADC=y
+CONFIG_CPU_HAS_INTEVT=y
+CONFIG_CPU_HAS_IPR_IRQ=y
+CONFIG_CPU_HAS_SR_RB=y
+
+#
+# Timer and clock configuration
+#
+CONFIG_SH_TMU=y
+CONFIG_SH_TIMER_IRQ=16
+CONFIG_SH_PCLK_FREQ=24000000
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# DMA support
+#
+CONFIG_SH_DMA_API=y
+CONFIG_SH_DMA=y
+CONFIG_NR_ONCHIP_DMA_CHANNELS=6
+# CONFIG_NR_DMA_CHANNELS_BOOL is not set
+
+#
+# Companion Chips
+#
+# CONFIG_HD6446X_SERIES is not set
+
+#
+# Additional SuperH Device Drivers
+#
+CONFIG_HEARTBEAT=y
+# CONFIG_PUSH_SWITCH is not set
+
+#
+# Kernel features
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_SMP is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+
+#
+# Boot options
+#
+CONFIG_ZERO_PAGE_OFFSET=0x00001000
+CONFIG_BOOT_LINK_OFFSET=0x00800000
+# CONFIG_UBC_WAKEUP is not set
+# CONFIG_CMDLINE_BOOL is not set
+
+#
+# Bus options
+#
+# CONFIG_PCI is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options (EXPERIMENTAL)
+#
+# CONFIG_PM is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+# CONFIG_PNPACPI is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# Misc devices
+#
+# CONFIG_BLINK is not set
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_STNIC is not set
+# CONFIG_SMC91X is not set
+CONFIG_SMC911X=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_ROCKETPORT is not set
+# CONFIG_DIGIEPCA is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_SYNCLINKMP is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_RIO is not set
+# CONFIG_STALDRV is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=48
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=2
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+# CONFIG_HWMON is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# HID Devices
+#
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+
+#
+# USB support
+#
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
+# InfiniBand support
+#
+
+#
+# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+#
+
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SH=y
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_MINIX_FS=m
+# CONFIG_ROMFS_FS is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=m
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_BIND34=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=y
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=y
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+CONFIG_DEBUG_SLAB=y
+CONFIG_DEBUG_SLAB_LEAK=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_DEBUG_KOBJECT=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_VM=y
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_FORCED_INLINING is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SH_STANDARD_BIOS is not set
+# CONFIG_EARLY_SCIF_CONSOLE is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_4KSTACKS is not set
+CONFIG_SH_KGDB=y
+
+#
+# KGDB configuration options
+#
+# CONFIG_MORE_COMPILE_OPTIONS is not set
+# CONFIG_KGDB_NMI is not set
+CONFIG_KGDB_SYSRQ=y
+
+#
+# Serial port setup
+#
+CONFIG_KGDB_DEFPORT=1
+CONFIG_KGDB_DEFBAUD=115200
+CONFIG_KGDB_DEFPARITY_N=y
+# CONFIG_KGDB_DEFPARITY_E is not set
+# CONFIG_KGDB_DEFPARITY_O is not set
+CONFIG_KGDB_DEFBITS_8=y
+# CONFIG_KGDB_DEFBITS_7 is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -upNr linux-2.6.22-rc7-mod-CPU/arch/sh/drivers/heartbeat.c linux-2.6.22-rc7-mod/arch/sh/drivers/heartbeat.c
--- linux-2.6.22-rc7-mod-CPU/arch/sh/drivers/heartbeat.c 2007-07-20 09:57:19.000000000 +0200
+++ linux-2.6.22-rc7-mod/arch/sh/drivers/heartbeat.c 2007-07-17 17:00:37.000000000 +0200
@@ -39,7 +39,11 @@ static void heartbeat_timer(unsigned lon
struct heartbeat_data *hd = (struct heartbeat_data *)data;
static unsigned bit = 0, up = 1;
+#if defined(CONFIG_SH_MAGIC_PANEL_R2)
+ ctrl_outb(~(1 << hd->bit_pos[bit]), (unsigned long)hd->base);
+#else
ctrl_outw(1 << hd->bit_pos[bit], (unsigned long)hd->base);
+#endif
bit += up;
if ((bit == 0) || (bit == ARRAY_SIZE(hd->bit_pos)-1))
up = -up;
diff -upNr linux-2.6.22-rc7-mod-CPU/arch/sh/Kconfig linux-2.6.22-rc7-mod/arch/sh/Kconfig
--- linux-2.6.22-rc7-mod-CPU/arch/sh/Kconfig 2007-07-19 16:24:31.000000000 +0200
+++ linux-2.6.22-rc7-mod/arch/sh/Kconfig 2007-07-20 16:12:37.000000000 +0200
@@ -269,6 +269,12 @@ config SH_LBOX_RE2
help
Select L-BOX RE2 if configuring for the NTT COMWARE L-BOX RE2.
+config SH_MAGIC_PANEL_R2
+ bool "Magic Panel R2"
+ select CPU_SUBTYPE_SH7720
+ help
+ Select Magic Panel R2 if configuring for Magic Panel R2.
+
config SH_UNKNOWN
bool "BareCPU"
help
@@ -283,6 +289,11 @@ config SH_UNKNOWN
endchoice
+config SH_MAGIC_PANEL_R2_VERSION
+ int SH_MAGIC_PANEL_R2_VERSION
+ depends on SH_MAGIC_PANEL_R2
+ default "3"
+
source "arch/sh/boards/renesas/hs7751rvoip/Kconfig"
source "arch/sh/boards/renesas/rts7751r2d/Kconfig"
source "arch/sh/boards/renesas/r7780rp/Kconfig"
diff -upNr linux-2.6.22-rc7-mod-CPU/arch/sh/Makefile linux-2.6.22-rc7-mod/arch/sh/Makefile
--- linux-2.6.22-rc7-mod-CPU/arch/sh/Makefile 2007-07-20 14:07:40.000000000 +0200
+++ linux-2.6.22-rc7-mod/arch/sh/Makefile 2007-07-20 16:43:15.000000000 +0200
@@ -113,6 +113,7 @@ machdir-$(CONFIG_SH_SHMIN) := shmin
machdir-$(CONFIG_SH_7206_SOLUTION_ENGINE) := se/7206
machdir-$(CONFIG_SH_7619_SOLUTION_ENGINE) := se/7619
machdir-$(CONFIG_SH_LBOX_RE2) := lboxre2
+machdir-$(CONFIG_SH_MAGIC_PANEL_R2) := magicpanelr2
machdir-$(CONFIG_SH_UNKNOWN) := unknown
incdir-y := $(notdir $(machdir-y))
diff -upNr linux-2.6.22-rc7-mod-CPU/arch/sh/tools/mach-types linux-2.6.22-rc7-mod/arch/sh/tools/mach-types
--- linux-2.6.22-rc7-mod-CPU/arch/sh/tools/mach-types 2007-07-20 17:48:40.000000000 +0200
+++ linux-2.6.22-rc7-mod/arch/sh/tools/mach-types 2007-07-20 17:48:50.000000000 +0200
@@ -34,3 +34,4 @@ R7785RP SH_R7785RP
TITAN SH_TITAN
SHMIN SH_SHMIN
7710VOIPGW SH_7710VOIPGW
+MAGICPANELR2 SH_MAGIC_PANEL_R2
diff -upNr linux-2.6.22-rc7-mod-CPU/include/asm-sh/magicpanelr2.h linux-2.6.22-rc7-mod/include/asm-sh/magicpanelr2.h
--- linux-2.6.22-rc7-mod-CPU/include/asm-sh/magicpanelr2.h 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.22-rc7-mod/include/asm-sh/magicpanelr2.h 2007-07-20 18:14:09.000000000 +0200
@@ -0,0 +1,131 @@
+/*
+ * include/asm-sh/magicpanelr2.h
+ *
+ * Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ * I/O addresses and bitmasks for Magic Panel Release 2 board
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_SH_MAGICPANELR2_H
+#define __ASM_SH_MAGICPANELR2_H
+
+#include <asm/port.h>
+
+#define __IO_PREFIX mpr2
+#include <asm/io_generic.h>
+
+
+#define SETBITS_OUTB(mask, reg) ctrl_outb(ctrl_inb(reg) | mask, reg)
+#define SETBITS_OUTW(mask, reg) ctrl_outw(ctrl_inw(reg) | mask, reg)
+#define SETBITS_OUTL(mask, reg) ctrl_outl(ctrl_inl(reg) | mask, reg)
+#define CLRBITS_OUTB(mask, reg) ctrl_outb(ctrl_inb(reg) & ~mask, reg)
+#define CLRBITS_OUTW(mask, reg) ctrl_outw(ctrl_inw(reg) & ~mask, reg)
+#define CLRBITS_OUTL(mask, reg) ctrl_outl(ctrl_inl(reg) & ~mask, reg)
+
+
+#define PA_LED PORT_PADR /* LED */
+
+
+/* BSC */
+#define CMNCR 0xA4FD0000UL
+#define CS0BCR 0xA4FD0004UL
+#define CS2BCR 0xA4FD0008UL
+#define CS3BCR 0xA4FD000CUL
+#define CS4BCR 0xA4FD0010UL
+#define CS5ABCR 0xA4FD0014UL
+#define CS5BBCR 0xA4FD0018UL
+#define CS6ABCR 0xA4FD001CUL
+#define CS6BBCR 0xA4FD0020UL
+#define CS0WCR 0xA4FD0024UL
+#define CS2WCR 0xA4FD0028UL
+#define CS3WCR 0xA4FD002CUL
+#define CS4WCR 0xA4FD0030UL
+#define CS5AWCR 0xA4FD0034UL
+#define CS5BWCR 0xA4FD0038UL
+#define CS6AWCR 0xA4FD003CUL
+#define CS6BWCR 0xA4FD0040UL
+
+
+#define ICR1_MAI 0x8000
+#define ICR1_IRQLVL 0x4000
+#define ICR1_BLMSK 0x2000
+#define ICR1_IRQ5 0x0C00
+#define ICR1_IRQ5_HIGH 0x0C00
+#define ICR1_IRQ5_LOW 0x0800
+#define ICR1_IRQ5_RISE 0x0400
+#define ICR1_IRQ5_FALL 0x0000
+#define ICR1_IRQ4 0x0300
+#define ICR1_IRQ4_HIGH 0x0300
+#define ICR1_IRQ4_LOW 0x0200
+#define ICR1_IRQ4_RISE 0x0100
+#define ICR1_IRQ4_FALL 0x0000
+#define ICR1_IRQ3 0x00C0
+#define ICR1_IRQ3_HIGH 0x00C0
+#define ICR1_IRQ3_LOW 0x0080
+#define ICR1_IRQ3_RISE 0x0040
+#define ICR1_IRQ3_FALL 0x0000
+#define ICR1_IRQ2 0x0030
+#define ICR1_IRQ2_HIGH 0x0030
+#define ICR1_IRQ2_LOW 0x0020
+#define ICR1_IRQ2_RISE 0x0010
+#define ICR1_IRQ2_FALL 0x0000
+#define ICR1_IRQ1 0x000C
+#define ICR1_IRQ1_HIGH 0x000C
+#define ICR1_IRQ1_LOW 0x0008
+#define ICR1_IRQ1_RISE 0x0004
+#define ICR1_IRQ1_FALL 0x0000
+#define ICR1_IRQ0 0x0003
+#define ICR1_IRQ0_HIGH 0x0003
+#define ICR1_IRQ0_LOW 0x0002
+#define ICR1_IRQ0_RISE 0x0001
+#define ICR1_IRQ0_FALL 0x0000
+#define ICR2_PINT15S 0x8000
+#define ICR2_PINT14S 0x4000
+#define ICR2_PINT13S 0x2000
+#define ICR2_PINT12S 0x1000
+#define ICR2_PINT11S 0x0800
+#define ICR2_PINT10S 0x0400
+#define ICR2_PINT9S 0x0200
+#define ICR2_PINT8S 0x0100
+#define ICR2_PINT7S 0x0080
+#define ICR2_PINT6S 0x0040
+#define ICR2_PINT5S 0x0020
+#define ICR2_PINT4S 0x0010
+#define ICR2_PINT3S 0x0008
+#define ICR2_PINT2S 0x0004
+#define ICR2_PINT1S 0x0002
+#define ICR2_PINT0S 0x0001
+
+
+#define PINTER ( 0xA4140014 )
+#define PINTER_PINT15E 0x8000
+#define PINTER_PINT14E 0x4000
+#define PINTER_PINT13E 0x2000
+#define PINTER_PINT12E 0x1000
+#define PINTER_PINT11E 0x0800
+#define PINTER_PINT10E 0x0400
+#define PINTER_PINT9E 0x0200
+#define PINTER_PINT8E 0x0100
+#define PINTER_PINT7E 0x0080
+#define PINTER_PINT6E 0x0040
+#define PINTER_PINT5E 0x0020
+#define PINTER_PINT4E 0x0010
+#define PINTER_PINT3E 0x0008
+#define PINTER_PINT2E 0x0004
+#define PINTER_PINT1E 0x0002
+#define PINTER_PINT0E 0x0001
+
+/*usb*/
+
+#define PORT_UTRCTL 0xA405012CUL
+#define PORT_UCLKCR_W 0xA40A0008UL
+
+#define INTC_ICR0 0xA414FEE0UL
+#define INTC_ICR1 0xA4140010UL
+#define INTC_ICR2 0xA4140012UL
+
+#endif /* __ASM_SH_MAGICPANELR2_H */
|
|
From: Markus B. <sup...@go...> - 2007-07-23 07:11:40
|
Hello Paul,
this patch adds support for the SH7720 SH3-DSP CPU to 2.6.22.
How are the chances to get it accepted?
Signed-off by: Markus Brunner <sup...@gm...>
Signed-off by: Mark Jonas <to...@gm...>
---
Status of the patch
DMA is untested. Suggestions how to test it are welcome.
UBC is untested. Booting is fine with, or without the "Wakeup UBC on startup" option.
Not surprising, because the bootloader didn't disable it. Suggestions how to test it are welcome.
Is anybody really using it? It looks a little unmaintained.
We removed the UBC_TYPE_SH7729 define in asm-sh/ubc.h, because it is unused, but looks rather important because of all the ifdef CPU_SUBTYPEs.
A small bug was fixed after line 367 rtc-sh.c. The comment already claimed to stop the RTC,
but actually it was not done. This is not necessary for all CPUs, but at least for 7720 and 7705.
Added asm-sh/port.h and asm-sh/cpu-sh3/port.h because the registers of the PFC
are defined all over the place and port.h seemed to be the right place.
The SH7720 has PINT interrupts, but support wasn't added. The reason is that the
existing driver is not flexible enough.
We tried to implement early printk but failed miserably. The scif_sercon_init function was never called.
Any hints?
kgdb is working, but I have problems using ttySC1, however ttySC1 is working fine for other things.
Ethernet NFS performance is pretty bad (about 500 kB/s). I have not done any research on this yet.
arch/sh/drivers/dma/Kconfig | 1
arch/sh/drivers/dma/dma-sh.c | 11 +-
arch/sh/kernel/cpu/sh3/Makefile | 2
arch/sh/kernel/cpu/sh3/clock-sh7720.c | 88 ++++++++++++++++
arch/sh/kernel/cpu/sh3/probe.c | 3
arch/sh/kernel/cpu/sh3/setup-sh7720.c | 183 ++++++++++++++++++++++++++++++++++
arch/sh/kernel/setup.c | 2
arch/sh/kernel/timers/timer-tmu.c | 1
arch/sh/mm/Kconfig | 8 +
drivers/net/Kconfig | 2
drivers/net/smc911x.h | 4
drivers/rtc/rtc-sh.c | 7 -
drivers/serial/sh-sci.c | 33 ++++++
drivers/serial/sh-sci.h | 40 ++++++-
include/asm-sh/cpu-sh3/cache.h | 4
include/asm-sh/cpu-sh3/dma.h | 13 ++
include/asm-sh/cpu-sh3/mmu_context.h | 11 +-
include/asm-sh/cpu-sh3/port.h | 67 ++++++++++++
include/asm-sh/cpu-sh3/timer.h | 10 +
include/asm-sh/cpu-sh3/ubc.h | 2
include/asm-sh/port.h | 22 ++++
include/asm-sh/processor.h | 2
include/asm-sh/ubc.h | 6 -
23 files changed, 492 insertions(+), 30 deletions(-)
diff -upNr linux-2.6.22-rc7-orig/arch/sh/drivers/dma/dma-sh.c linux-2.6.22-rc7-mod-CPU/arch/sh/drivers/dma/dma-sh.c
--- linux-2.6.22-rc7-orig/arch/sh/drivers/dma/dma-sh.c 2007-07-04 10:27:03.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/drivers/dma/dma-sh.c 2007-07-20 16:58:21.000000000 +0200
@@ -24,13 +24,18 @@ static int dmte_irq_map[] = {
DMTE1_IRQ,
DMTE2_IRQ,
DMTE3_IRQ,
-#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
defined(CONFIG_CPU_SUBTYPE_SH7760) || \
defined(CONFIG_CPU_SUBTYPE_SH7780)
DMTE4_IRQ,
DMTE5_IRQ,
+#endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7760) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7780)
DMTE6_IRQ,
- DMTE7_IRQ,
+ DMTE7_IRQ,
#endif
};
@@ -196,7 +201,7 @@ static int sh_dmac_get_dma_residue(struc
return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan);
}
-#ifdef CONFIG_CPU_SUBTYPE_SH7780
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7780)
#define dmaor_read_reg() ctrl_inw(DMAOR)
#define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
#else
diff -upNr linux-2.6.22-rc7-orig/arch/sh/drivers/dma/Kconfig linux-2.6.22-rc7-mod-CPU/arch/sh/drivers/dma/Kconfig
--- linux-2.6.22-rc7-orig/arch/sh/drivers/dma/Kconfig 2007-07-04 10:31:07.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/drivers/dma/Kconfig 2007-07-20 17:36:48.000000000 +0200
@@ -11,6 +11,7 @@ config SH_DMA
config NR_ONCHIP_DMA_CHANNELS
depends on SH_DMA
int "Number of on-chip DMAC channels"
+ default "6" if CPU_SUBTYPE_SH7720
default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
default "12" if CPU_SUBTYPE_SH7780
default "4"
diff -upNr linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/clock-sh7720.c linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/clock-sh7720.c
--- linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/clock-sh7720.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/clock-sh7720.c 2007-07-20 17:37:11.000000000 +0200
@@ -0,0 +1,88 @@
+/*
+ * arch/sh/kernel/cpu/sh3/clock-sh7720.c
+ *
+ * SH7720 support for the clock framework
+ *
+ * Copyright (C) 2005 Paul Mundt
+ * Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ * strongly based on arch/sh/kernel/cpu/sh3/clock-sh7705.c
+ *
+ * FRQCR parsing hacked out of arch/sh/kernel/time.c
+ *
+ * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
+ * Copyright (C) 2000 Philipp Rumpf <pr...@tu...>
+ * Copyright (C) 2002, 2003, 2004 Paul Mundt
+ * Copyright (C) 2002 M. R. Brown <mr...@li...>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <asm/clock.h>
+#include <asm/freq.h>
+#include <linux/io.h>
+
+/*
+ * SH7720 uses the same divisors as the generic SH-3 case, it's just the
+ * FRQCR layout that is a bit different..
+ */
+static int stc_multipliers[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
+static int ifc_divisors[] = { 1, 2, 3, 4, 1, 1, 1, 1 };
+static int pfc_divisors[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
+
+static void master_clk_init(struct clk *clk)
+{
+ clk->rate *= pfc_divisors[ctrl_inw(FRQCR) & 0x0007];
+}
+
+static struct clk_ops sh7720_master_clk_ops = {
+ .init = master_clk_init,
+};
+
+static void module_clk_recalc(struct clk *clk)
+{
+ int idx = ctrl_inw(FRQCR) & 0x0007;
+ clk->rate = clk->parent->rate / pfc_divisors[idx];
+}
+
+static struct clk_ops sh7720_module_clk_ops = {
+ .recalc = module_clk_recalc,
+};
+
+static void bus_clk_recalc(struct clk *clk)
+{
+ int idx = (ctrl_inw(FRQCR) & 0x0300) >> 8;
+ clk->rate = clk->parent->rate / stc_multipliers[idx];
+}
+
+static struct clk_ops sh7720_bus_clk_ops = {
+ .recalc = bus_clk_recalc,
+};
+
+static void cpu_clk_recalc(struct clk *clk)
+{
+ int idx = (ctrl_inw(FRQCR) & 0x0030) >> 4;
+ clk->rate = clk->parent->rate / ifc_divisors[idx];
+}
+
+static struct clk_ops sh7720_cpu_clk_ops = {
+ .recalc = cpu_clk_recalc,
+};
+
+static struct clk_ops *sh7720_clk_ops[] = {
+ &sh7720_master_clk_ops,
+ &sh7720_module_clk_ops,
+ &sh7720_bus_clk_ops,
+ &sh7720_cpu_clk_ops,
+};
+
+void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+{
+ if (idx < ARRAY_SIZE(sh7720_clk_ops)) {
+ *ops = sh7720_clk_ops[idx];
+ }
+}
+
diff -upNr linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/Makefile linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/Makefile
--- linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/Makefile 2007-07-04 10:31:07.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/Makefile 2007-07-19 13:26:49.000000000 +0200
@@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setu
obj-$(CONFIG_CPU_SUBTYPE_SH7300) += setup-sh7300.o
obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o
obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o
# Primary on-chip clocks (common)
clock-$(CONFIG_CPU_SH3) := clock-sh3.o
@@ -21,5 +22,6 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7705) := cl
clock-$(CONFIG_CPU_SUBTYPE_SH7706) := clock-sh7706.o
clock-$(CONFIG_CPU_SUBTYPE_SH7709) := clock-sh7709.o
clock-$(CONFIG_CPU_SUBTYPE_SH7710) := clock-sh7300.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7720) := clock-sh7720.o
obj-y += $(clock-y)
diff -upNr linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/probe.c linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/probe.c
--- linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/probe.c 2007-07-04 10:31:07.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/probe.c 2007-07-20 17:37:25.000000000 +0200
@@ -81,6 +81,9 @@ int __init detect_cpu_and_cache_system(v
#if defined(CONFIG_CPU_SUBTYPE_SH7712)
current_cpu_data.type = CPU_SH7712;
#endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7720)
+ current_cpu_data.type = CPU_SH7720;
+#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
current_cpu_data.type = CPU_SH7705;
diff -upNr linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/setup-sh7720.c linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/setup-sh7720.c
--- linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/setup-sh7720.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/setup-sh7720.c 2007-07-20 17:37:37.000000000 +0200
@@ -0,0 +1,183 @@
+/*
+ * SH7720 Setup
+ *
+ * Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ * Based on arch/sh(kernel/cpu/setup-sh7750.c:
+ *
+ * Copyright (C) 2006 Paul Mundt
+ * Copyright (C) 2006 Jamie Lenehan
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/io.h>
+#include <asm/sci.h>
+
+static struct resource rtc_resources[] = {
+ [0] = {
+ .start = 0xa413fec0,
+ .end = 0xa413fec0 + 0x28 - 1,
+ .flags = IORESOURCE_IO,
+ },
+ [1] = {
+ /* Period IRQ */
+ .start = 21,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ /* Carry IRQ */
+ .start = 22,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ /* Alarm IRQ */
+ .start = 20,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device rtc_device = {
+ .name = "sh-rtc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(rtc_resources),
+ .resource = rtc_resources,
+};
+
+static struct plat_sci_port sci_platform_data[] = {
+ {
+ .mapbase = 0xa4430000,
+ .flags = UPF_BOOT_AUTOCONF,
+ .type = PORT_SCIF,
+ .irqs = { 80, 80, 80, 80 },
+ }, {
+ .mapbase = 0xa4438000,
+ .flags = UPF_BOOT_AUTOCONF,
+ .type = PORT_SCIF,
+ .irqs = { 81, 81, 81, 81 },
+ }, {
+
+ .flags = 0,
+ }
+};
+
+static struct platform_device sci_device = {
+ .name = "sh-sci",
+ .id = -1,
+ .dev = {
+ .platform_data = sci_platform_data,
+ },
+};
+
+static struct platform_device *sh7720_devices[] __initdata = {
+ &rtc_device,
+ &sci_device,
+};
+
+static int __init sh7720_devices_setup(void)
+{
+ return platform_add_devices(sh7720_devices,
+ ARRAY_SIZE(sh7720_devices));
+}
+__initcall(sh7720_devices_setup);
+
+static struct ipr_data sh7720_ipr_map[] = {
+ /* IRQ, IPR-idx, shift, priority */
+ /* IPRA */
+ { 16, 0, 12, 2 }, /* TMU0 TUNI0 */
+ { 17, 0, 8, 2 }, /* TMU1 TUNI1 */
+ { 18, 0, 4, 2 }, /* TMU2 TUNI2 */
+ { 20, 0, 0, 2 }, /* RTC ATI */
+ { 21, 0, 0, 2 }, /* RTC PRI */
+ { 22, 0, 0, 2 }, /* RTC CUI */
+
+ /* IPRB */
+ { 27, 1, 12, 2 }, /* WDT ITI */
+ { 28, 1, 8, 2 }, /* REF RCMI*/
+ { 23, 1, 4, 2 }, /* SIM ERI */
+ { 24, 1, 4, 2 }, /* SIM RXI */
+ { 25, 1, 4, 2 }, /* SIM TXI */
+ { 26, 1, 4, 2 }, /* SIM TEND */
+
+ /* IPRC */
+ /* IRQ3..0 are board specific. */
+
+ /* IPRD */
+ { 38, 3, 8, 2 }, /* TMU SUNI */
+ { 39, 3, 12, 7 }, /* USBF SPD */
+ /* IRQ5..4 are board specific. */
+
+ /* IPRE */
+ { 48, 4, 12, 1 }, /* DMAC_1 DEI0 */
+ { 49, 4, 12, 1 }, /* DMAC_1 DEI1 */
+ { 50, 4, 12, 1 }, /* DMAC_1 DEI2 */
+ { 51, 4, 12, 1 }, /* DMAC_1 DEI3 */
+ { 56, 4, 4, 2 }, /* LCD LCDCI */
+ { 60, 4, 0, 2 }, /* SSL SSLI */
+
+ /* IPRF */
+ { 79, 5, 12, 2 }, /* ADC ADCI */
+ { 76, 5, 8, 1 }, /* DMAC_2 DEI4 */
+ { 77, 5, 8, 1 }, /* DMAC_2 DEI5 */
+ { 65, 5, 4, 7 }, /* USBF USBFI0 */
+ { 66, 5, 4, 7 }, /* USBF USBFI1 */
+ {104, 5, 0, 2 }, /* CMT CMI */
+
+ /* IPRG */
+ { 80, 6, 12, 2 }, /* SCIF0 SCIFI0 */
+ { 81, 6, 8, 2 }, /* SCIF1 SCIFI1 */
+
+ /* IPRH */
+ /* PINTA and PINTB are board specific. */
+ { 92, 7, 4, 2 }, /* TPU TPI0 */
+ { 93, 7, 4, 2 }, /* TPU TPI1 */
+ { 94, 7, 4, 2 }, /* TPU TPI2 */
+ { 95, 7, 4, 2 }, /* TPU TPI3 */
+ { 96, 7, 0, 2 }, /* IIC IICI */
+
+ /* IPRI */
+ { 88, 8, 12, 2 }, /* SIOF0 SIOFI0 */
+ { 89, 8, 8, 2 }, /* SIOF1 SIOFI1 */
+ {100, 8, 4, 2 }, /* MMC MMCI0 */
+ {101, 8, 4, 2 }, /* MMC MMCI1 */
+ {102, 8, 4, 2 }, /* MMC MMCI2 */
+ {103, 8, 4, 2 }, /* MMC MMCI3 */
+ {107, 8, 0, 2 }, /* PCC PCCI */
+
+ /* IPRJ */
+ { 67, 9, 8, 6 }, /* USBH USBHI */
+ {111, 9, 0, 2 }, /* AFEIF AFECI */
+};
+
+static unsigned long ipr_offsets[] = {
+ 0xA414FEE2UL, /* 0: IPRA */
+ 0xA414FEE4UL, /* 1: IPRB */
+ 0xA4140016UL, /* 2: IPRC */
+ 0xA4140018UL, /* 3: IPRD */
+ 0xA414001AUL, /* 4: IPRE */
+ 0xA4080000UL, /* 5: IPRF */
+ 0xA4080002UL, /* 6: IPRG */
+ 0xA4080004UL, /* 7: IPRH */
+ 0xA4080006UL, /* 8: IPRI */
+ 0xA4080008UL /* 9: IPRJ */
+};
+
+/* given the IPR index return the address of the IPR register */
+unsigned int map_ipridx_to_addr(int idx)
+{
+ if (idx >= ARRAY_SIZE(ipr_offsets)) {
+ return 0;
+ }
+ return ipr_offsets[idx];
+}
+
+void __init init_IRQ_ipr()
+{
+ make_ipr_irq(sh7720_ipr_map, ARRAY_SIZE(sh7720_ipr_map));
+}
+
diff -upNr linux-2.6.22-rc7-orig/arch/sh/kernel/setup.c linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/setup.c
--- linux-2.6.22-rc7-orig/arch/sh/kernel/setup.c 2007-07-04 10:31:08.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/setup.c 2007-07-17 09:50:54.000000000 +0200
@@ -409,7 +409,7 @@ static const char *cpu_name[] = {
[CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
[CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
[CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710",
- [CPU_SH7712] = "SH7712",
+ [CPU_SH7712] = "SH7712", [CPU_SH7720] = "SH7720",
[CPU_SH7729] = "SH7729", [CPU_SH7750] = "SH7750",
[CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R",
[CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R",
diff -upNr linux-2.6.22-rc7-orig/arch/sh/kernel/timers/timer-tmu.c linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/timers/timer-tmu.c
--- linux-2.6.22-rc7-orig/arch/sh/kernel/timers/timer-tmu.c 2007-07-04 10:31:08.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/timers/timer-tmu.c 2007-07-20 14:00:21.000000000 +0200
@@ -173,6 +173,7 @@ static int tmu_timer_init(void)
tmu_timer_stop();
#if !defined(CONFIG_CPU_SUBTYPE_SH7300) && \
+ !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
!defined(CONFIG_CPU_SUBTYPE_SH7760) && \
!defined(CONFIG_CPU_SUBTYPE_SH7785)
ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
diff -upNr linux-2.6.22-rc7-orig/arch/sh/mm/Kconfig linux-2.6.22-rc7-mod-CPU/arch/sh/mm/Kconfig
--- linux-2.6.22-rc7-orig/arch/sh/mm/Kconfig 2007-07-04 10:31:08.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/mm/Kconfig 2007-07-04 10:39:33.000000000 +0200
@@ -113,6 +113,14 @@ config CPU_SUBTYPE_SH7712
help
Select SH7712 if you have a SH3-DSP SH7712 CPU.
+config CPU_SUBTYPE_SH7720
+ bool "Support SH7720 processor"
+ select CPU_SH3
+ select CPU_HAS_IPR_IRQ
+# select CPU_HAS_PINT_IRQ
+ help
+ Select SH7720 if you have a SH3-DSP SH7720 CPU.
+
comment "SH-4 Processor Support"
config CPU_SUBTYPE_SH7750
diff -upNr linux-2.6.22-rc7-orig/drivers/net/Kconfig linux-2.6.22-rc7-mod-CPU/drivers/net/Kconfig
--- linux-2.6.22-rc7-orig/drivers/net/Kconfig 2007-07-04 10:31:20.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/drivers/net/Kconfig 2007-07-19 15:47:19.000000000 +0200
@@ -879,7 +879,7 @@ config SMC911X
tristate "SMSC LAN911[5678] support"
select CRC32
select MII
- depends on NET_ETHERNET && ARCH_PXA
+ depends on NET_ETHERNET && ( ARCH_PXA || SUPERH )
help
This is a driver for SMSC's LAN911x series of Ethernet chipsets
including the new LAN9115, LAN9116, LAN9117, and LAN9118.
diff -upNr linux-2.6.22-rc7-orig/drivers/net/smc911x.h linux-2.6.22-rc7-mod-CPU/drivers/net/smc911x.h
--- linux-2.6.22-rc7-orig/drivers/net/smc911x.h 2007-02-04 19:44:54.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/drivers/net/smc911x.h 2007-07-20 13:53:07.000000000 +0200
@@ -36,6 +36,10 @@
#define SMC_USE_PXA_DMA 1
#define SMC_USE_16BIT 0
#define SMC_USE_32BIT 1
+#elif CONFIG_SUPERH
+ #define SMC_USE_SH_DMA 0
+ #define SMC_USE_16BIT 0
+ #define SMC_USE_32BIT 1
#endif
diff -upNr linux-2.6.22-rc7-orig/drivers/rtc/rtc-sh.c linux-2.6.22-rc7-mod-CPU/drivers/rtc/rtc-sh.c
--- linux-2.6.22-rc7-orig/drivers/rtc/rtc-sh.c 2007-07-04 10:31:24.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/drivers/rtc/rtc-sh.c 2007-07-20 17:55:26.000000000 +0200
@@ -319,7 +319,8 @@ static int sh_rtc_read_time(struct devic
tm->tm_mday = BCD2BIN(readb(rtc->regbase + RDAYCNT));
tm->tm_mon = BCD2BIN(readb(rtc->regbase + RMONCNT)) - 1;
-#if defined(CONFIG_CPU_SH4)
+#if defined(CONFIG_CPU_SH4) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
yr = readw(rtc->regbase + RYRCNT);
yr100 = BCD2BIN(yr >> 8);
yr &= 0xff;
@@ -365,6 +366,7 @@ static int sh_rtc_set_time(struct device
/* Reset pre-scaler & stop RTC */
tmp = readb(rtc->regbase + RCR2);
tmp |= RCR2_RESET;
+ tmp &= ~RCR2_START;
writeb(tmp, rtc->regbase + RCR2);
writeb(BIN2BCD(tm->tm_sec), rtc->regbase + RSECCNT);
@@ -374,7 +376,8 @@ static int sh_rtc_set_time(struct device
writeb(BIN2BCD(tm->tm_mday), rtc->regbase + RDAYCNT);
writeb(BIN2BCD(tm->tm_mon + 1), rtc->regbase + RMONCNT);
-#ifdef CONFIG_CPU_SH3
+#if defined(CONFIG_CPU_SH3) && \
+ !defined(CONFIG_CPU_SUBTYPE_SH7720)
year = tm->tm_year % 100;
writeb(BIN2BCD(year), rtc->regbase + RYRCNT);
#else
diff -upNr linux-2.6.22-rc7-orig/drivers/serial/sh-sci.c linux-2.6.22-rc7-mod-CPU/drivers/serial/sh-sci.c
--- linux-2.6.22-rc7-orig/drivers/serial/sh-sci.c 2007-07-04 10:31:28.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/drivers/serial/sh-sci.c 2007-07-20 17:55:58.000000000 +0200
@@ -4,6 +4,7 @@
* SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
*
* Copyright (C) 2002 - 2006 Paul Mundt
+ * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
*
* based off of the old drivers/char/sh-sci.c by:
*
@@ -306,6 +307,38 @@ static void sci_init_pins_scif(struct ua
}
sci_out(port, SCFCR, fcr_val);
}
+#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
+static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
+{
+ unsigned int fcr_val = 0;
+ unsigned short data;
+
+ if (cflag & CRTSCTS) {
+ /* enable RTS/CTS */
+ if (port->mapbase == 0xa4430000) { /* SCIF0 */
+ /* Clear PTCR bit 9-2; enable all scif pins but sck */
+ data = ctrl_inw(PORT_PTCR);
+ ctrl_outw((data & 0xfc03), PORT_PTCR);
+ } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
+ /* Clear PVCR bit 9-2 */
+ data = ctrl_inw(PORT_PVCR);
+ ctrl_outw((data & 0xfc03), PORT_PVCR);
+ }
+ fcr_val |= SCFCR_MCE;
+ } else {
+ if (port->mapbase == 0xa4430000) { /* SCIF0 */
+ /* Clear PTCR bit 5-2; enable only tx and rx */
+ data = ctrl_inw(PORT_PTCR);
+ ctrl_outw((data & 0xffc3), PORT_PTCR);
+ } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
+ /* Clear PVCR bit 5-2 */
+ data = ctrl_inw(PORT_PVCR);
+ ctrl_outw((data & 0xffc3), PORT_PVCR);
+ }
+ }
+ sci_out(port, SCFCR, fcr_val);
+}
+
#elif defined(CONFIG_CPU_SH3)
/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
diff -upNr linux-2.6.22-rc7-orig/drivers/serial/sh-sci.h linux-2.6.22-rc7-mod-CPU/drivers/serial/sh-sci.h
--- linux-2.6.22-rc7-orig/drivers/serial/sh-sci.h 2007-07-04 10:31:28.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/drivers/serial/sh-sci.h 2007-07-20 18:02:16.000000000 +0200
@@ -9,6 +9,7 @@
* Modified to support multiple serial ports. Stuart Menefy (May 2000).
* Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
* Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
+ * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
*/
#include <linux/serial_core.h>
#include <asm/io.h>
@@ -23,6 +24,8 @@
#endif
#endif
+#include <asm/port.h>
+
#if defined(CONFIG_CPU_SUBTYPE_SH7708)
# define SCSPTR 0xffffff7c /* 8 bit */
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
@@ -53,6 +56,12 @@
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ONLY
+
+#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
+# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
+# define SCIF_ONLY
+#define SCIF_ORER 0x0200 /* overrun error bit */
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
# define SCSPTR1 0xffe0001c /* 8 bit SCI */
# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
@@ -212,7 +221,9 @@
#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
-#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
+#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
#define SCIF_ORER 0x0200
#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
#define SCIF_RFDC_MASK 0x007f
@@ -241,7 +252,9 @@
# define SCxSR_ERRORS(port) SCIF_ERRORS
# define SCxSR_RDxF(port) SCIF_RDF
# define SCxSR_TDxE(port) SCIF_TDFE
-#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
+#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
# define SCxSR_ORER(port) SCIF_ORER
#else
# define SCxSR_ORER(port) 0x0000
@@ -249,7 +262,9 @@
# define SCxSR_FER(port) SCIF_FER
# define SCxSR_PER(port) SCIF_PER
# define SCxSR_BRK(port) SCIF_BRK
-#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
+#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
@@ -358,7 +373,8 @@
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
- defined(CONFIG_CPU_SUBTYPE_SH7705)
+ defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
#define SCIF_FNS(name, scif_offset, scif_size) \
CPU_SCIF_FNS(name, scif_offset, scif_size)
#else
@@ -385,7 +401,8 @@
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
- defined(CONFIG_CPU_SUBTYPE_SH7705)
+ defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCBRR, 0x04, 8)
@@ -547,6 +564,16 @@ static inline int sci_rxd_in(struct uart
return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
return 1;
}
+#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
+static inline int sci_rxd_in(struct uart_port *port)
+{
+ if (port->mapbase == 0xa4430000) {
+ return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
+ } else if (port->mapbase == 0xa4438000) {
+ return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
+ }
+ return 1;
+}
#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
static inline int sci_rxd_in(struct uart_port *port)
{
@@ -691,7 +718,8 @@ static inline int sci_rxd_in(struct uart
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
-#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/cache.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/cache.h
--- linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/cache.h 2007-02-04 19:44:54.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/cache.h 2007-07-19 15:29:34.000000000 +0200
@@ -26,7 +26,9 @@
#define CCR_CACHE_ENABLE CCR_CACHE_CE
#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
-#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7710)
+#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
#define CCR3 0xa40000b4
#define CCR_CACHE_16KB 0x00010000
#define CCR_CACHE_32KB 0x00020000
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/dma.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/dma.h
--- linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/dma.h 2007-07-04 10:31:41.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/dma.h 2007-07-18 09:34:25.000000000 +0200
@@ -1,7 +1,20 @@
#ifndef __ASM_CPU_SH3_DMA_H
#define __ASM_CPU_SH3_DMA_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7720)
+#define SH_DMAC_BASE 0xa4010020
+
+#define DMTE0_IRQ 48
+#define DMTE1_IRQ 49
+#define DMTE2_IRQ 50
+#define DMTE3_IRQ 51
+#define DMTE4_IRQ 76
+#define DMTE5_IRQ 77
+
+#else
#define SH_DMAC_BASE 0xa4000020
+#endif
/* Definitions for the SuperH DMAC */
#define TM_BURST 0x00000020
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/mmu_context.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/mmu_context.h
--- linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/mmu_context.h 2007-07-04 10:31:41.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/mmu_context.h 2007-07-20 17:02:17.000000000 +0200
@@ -27,13 +27,14 @@
#define TRA 0xffffffd0
#define EXPEVT 0xffffffd4
-#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
- defined(CONFIG_CPU_SUBTYPE_SH7709) || \
- defined(CONFIG_CPU_SUBTYPE_SH7706) || \
- defined(CONFIG_CPU_SUBTYPE_SH7300) || \
+#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7706) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7709) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7710) || \
defined(CONFIG_CPU_SUBTYPE_SH7712) || \
- defined(CONFIG_CPU_SUBTYPE_SH7710)
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
#else
#define INTEVT 0xffffffd8
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/port.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/port.h
--- linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/port.h 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/port.h 2007-07-20 12:35:28.000000000 +0200
@@ -0,0 +1,67 @@
+/*
+ * include/asm-sh/cpu-sh3/port.h
+ *
+ * Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ * Addresses for the Pin Function Controller
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _CPU_SH3_PORT_H
+#define _CPU_SH3_PORT_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7720)
+
+/* Control registers */
+#define PORT_PACR 0xA4050100UL
+#define PORT_PBCR 0xA4050102UL
+#define PORT_PCCR 0xA4050104UL
+#define PORT_PDCR 0xA4050106UL
+#define PORT_PECR 0xA4050108UL
+#define PORT_PFCR 0xA405010AUL
+#define PORT_PGCR 0xA405010CUL
+#define PORT_PHCR 0xA405010EUL
+#define PORT_PJCR 0xA4050110UL
+#define PORT_PKCR 0xA4050112UL
+#define PORT_PLCR 0xA4050114UL
+#define PORT_PMCR 0xA4050116UL
+#define PORT_PPCR 0xA4050118UL
+#define PORT_PRCR 0xA405011AUL
+#define PORT_PSCR 0xA405011CUL
+#define PORT_PTCR 0xA405011EUL
+#define PORT_PUCR 0xA4050120UL
+#define PORT_PVCR 0xA4050122UL
+
+/* Data registers */
+#define PORT_PADR 0xA4050140UL
+/* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */
+#define PORT_PBDR 0xA4050142UL
+#define PORT_PCDR 0xA4050144UL
+#define PORT_PDDR 0xA4050146UL
+#define PORT_PEDR 0xA4050148UL
+#define PORT_PFDR 0xA405014AUL
+#define PORT_PGDR 0xA405014CUL
+#define PORT_PHDR 0xA405014EUL
+#define PORT_PJDR 0xA4050150UL
+#define PORT_PKDR 0xA4050152UL
+#define PORT_PLDR 0xA4050154UL
+#define PORT_PMDR 0xA4050156UL
+#define PORT_PPDR 0xA4050158UL
+#define PORT_PRDR 0xA405015AUL
+#define PORT_PSDR 0xA405015CUL
+#define PORT_PTDR 0xA405015EUL
+#define PORT_PUDR 0xA4050160UL
+#define PORT_PVDR 0xA4050162UL
+
+/* Pin Select Registers */
+#define PORT_PSELA 0xA4050124UL
+#define PORT_PSELB 0xA4050126UL
+#define PORT_PSELC 0xA4050128UL
+#define PORT_PSELD 0xA405012AUL
+
+#endif
+
+#endif
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/timer.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/timer.h
--- linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/timer.h 2007-02-04 19:44:54.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/timer.h 2007-07-20 17:38:37.000000000 +0200
@@ -24,11 +24,14 @@
* ---------------------------------------------------------------------------
*/
-#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
+#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
+ !defined(CONFIG_CPU_SUBTYPE_SH7727)
#define TMU_TOCR 0xfffffe90 /* Byte access */
#endif
-#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
+#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
#define TMU_TSTR 0xa412fe92 /* Byte access */
#define TMU0_TCOR 0xa412fe94 /* Long access */
@@ -57,7 +60,8 @@
#define TMU2_TCOR 0xfffffeac /* Long access */
#define TMU2_TCNT 0xfffffeb0 /* Long access */
#define TMU2_TCR 0xfffffeb4 /* Word access */
-#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
+#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
+ !defined(CONFIG_CPU_SUBTYPE_SH7727)
#define TMU2_TCPR2 0xfffffeb8 /* Long access */
#endif
#endif
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/ubc.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/ubc.h
--- linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/ubc.h 2007-02-04 19:44:54.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/ubc.h 2007-07-20 12:35:28.000000000 +0200
@@ -11,7 +11,7 @@
#ifndef __ASM_CPU_SH3_UBC_H
#define __ASM_CPU_SH3_UBC_H
-#if defined(CONFIG_CPU_SUBTYPE_SH7710)
+#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7720)
#define UBC_BARA 0xa4ffffb0
#define UBC_BAMRA 0xa4ffffb4
#define UBC_BBRA 0xa4ffffb8
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/port.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/port.h
--- linux-2.6.22-rc7-orig/include/asm-sh/port.h 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/port.h 2007-07-20 12:35:45.000000000 +0200
@@ -0,0 +1,22 @@
+/*
+ * include/asm-sh/port.h
+ *
+ * Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ * Addresses for the Pin Function Controller
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _ASM_SH_PORT_H
+#define _ASM_SH_PORT_H
+
+#if defined(CONFIG_CPU_SH3)
+
+#include <asm/cpu/port.h>
+
+#endif
+
+#endif
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/processor.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/processor.h
--- linux-2.6.22-rc7-orig/include/asm-sh/processor.h 2007-07-04 10:31:41.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/processor.h 2007-07-04 10:39:33.000000000 +0200
@@ -45,7 +45,7 @@ enum cpu_type {
CPU_SH7705, CPU_SH7706, CPU_SH7707,
CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
- CPU_SH7729, CPU_SH7300,
+ CPU_SH7720, CPU_SH7729, CPU_SH7300,
/* SH-4 types */
CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/ubc.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/ubc.h
--- linux-2.6.22-rc7-orig/include/asm-sh/ubc.h 2007-07-04 10:27:25.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/ubc.h 2007-07-20 12:35:45.000000000 +0200
@@ -15,12 +15,6 @@
#include <asm/cpu/ubc.h>
/* User Break Controller */
-#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
- defined(CONFIG_CPU_SUBTYPE_SH7300)
-#define UBC_TYPE_SH7729 (current_cpu_data.type == CPU_SH7729)
-#else
-#define UBC_TYPE_SH7729 0
-#endif
#define BAMR_ASID (1 << 2)
#define BAMR_NONE 0
|
|
From: Magnus D. <mag...@gm...> - 2007-07-23 06:00:57
|
On 7/22/07, Paul Mundt <le...@li...> wrote: > On Sat, Jul 21, 2007 at 11:08:27PM -0700, Kristoffer Ericson wrote: > > Since fallout of make_ipr_irq Im not quite sure how to repair this for > > pint irq's. Ive looked at the dma-sh solution but not sure if thats the > > proper way to go. > > > At a quick glance, PINT seems to use a couple of IPR IRQs for cascade, > with the bulk of the logic in the demux. In this case, you're going to > want to make sure that your CPU includes those PINT vectors in its IPR > map, and then set up chained handlers for both where the PINT demux kicks > in as normal. > > None of that should be terribly difficult, though you are going to want > to convert your CPU subtype to the new INTC that Magnus wrote, he might > be able to give you some more input if you run in to some barriers doing > the conversion. I'd be happy to convert the 7709 setup code to work with the new intc handler. And after that I can build pint support on top of intc as well. This needs to be tested though and I don't have any 7709 hardware around. So if anyone could help out testing things that would be great. That would at least solve the issue of converting the 7709 setup code to intc. But maybe hp6xx hardware isn't enough to test pint. I wonder if it is using the pint interrupts at all. Hacking up pint support for a board that doesn't use it seems the wrong way to go... The only board-specific irq constants that i can find being used on hp6xx seem to be located in hp6xx.h except for the IRQ number for hd644661 which is located in the config file as CONFIG_HD64461_IRQ=36. These values all seem to map to IRQ pins. The irq number 93 otoh, it is associated with the pata_platform setup data in arch/sh/boards/hp6xx/setup.c and that is pretty close to PINT_IRQ_BASE which seems to be set to 86. So maybe we have a pint interrupt there after all... Kristoffer, do you have hp6xx hardware and some time for testing? Thanks! / magnus |
|
From: Paul M. <le...@li...> - 2007-07-22 02:18:15
|
On Sat, Jul 21, 2007 at 06:47:04PM -0700, Kristoffer Ericson wrote: > Im assuming this has something to to with the latest rework of IRQ. > <olegfink^> include/asm/irq.h:127:1: warning: "NR_IRQS" redefined This looks utterly bogus. Please provide the .config that manages to produce this, or post the entire build error. > <olegfink^> arch/sh/kernel/cpu/irq/pint.c:134: error: implicit declaration of function `disable_irq_nosync' > This is simply missing an #include <linux/interrupt.h>, which you'll want to add in as you do the PINT->INTC conversion. |
|
From: Paul M. <le...@li...> - 2007-07-22 02:16:04
|
On Fri, Jul 20, 2007 at 05:00:16PM +0900, Magnus Damm wrote: > sh: update r2d defconfig and fix SH7751R pci compliation On Fri, Jul 20, 2007 at 06:30:12PM +0900, Magnus Damm wrote: > sh: intc - add support for 7750 V2 Applied with some minor changes, thanks. They've already been pushed out to Linus and now reside in current git. |
|
From: Paul M. <le...@li...> - 2007-07-21 23:51:13
|
On Sat, Jul 21, 2007 at 11:08:27PM -0700, Kristoffer Ericson wrote: > Since fallout of make_ipr_irq Im not quite sure how to repair this for > pint irq's. Ive looked at the dma-sh solution but not sure if thats the > proper way to go. > No, dma-sh isn't a way you want to go for any sort of IRQ-related suggestions. > arch/sh/kernel/cpu/irq/pint.c (uses make_ipr_irq) > At a quick glance, PINT seems to use a couple of IPR IRQs for cascade, with the bulk of the logic in the demux. In this case, you're going to want to make sure that your CPU includes those PINT vectors in its IPR map, and then set up chained handlers for both where the PINT demux kicks in as normal. None of that should be terribly difficult, though you are going to want to convert your CPU subtype to the new INTC that Magnus wrote, he might be able to give you some more input if you run in to some barriers doing the conversion. SH7722 Solution Engine currently uses a chained handler with a demux in this scheme, so you may want to look as that as an example. Especially as the CPU itself was the first one converted to the generic INTC model. |
|
From: Kristoffer E. <kri...@gm...> - 2007-07-21 21:04:07
|
Greetings, Since fallout of make_ipr_irq Im not quite sure how to repair this for pint irq's. Ive looked at the dma-sh solution but not sure if thats the proper way to go. arch/sh/kernel/cpu/irq/pint.c (uses make_ipr_irq) -- Kristoffer Ericson <Kri...@Gm...> |
|
From: Kristoffer E. <kri...@gm...> - 2007-07-21 16:42:13
|
Im assuming this has something to to with the latest rework of IRQ. <olegfink^> include/asm/irq.h:127:1: warning: "NR_IRQS" redefined <olegfink^> arch/sh/kernel/cpu/irq/pint.c:134: error: implicit declaration of function `disable_irq_nosync' -- Kristoffer Ericson <Kri...@Gm...> |
|
From: Magnus D. <mag...@gm...> - 2007-07-20 09:31:21
|
sh: intc - add support for 7750 V2
This patch converts the cpu specific 7750 setup code to use the new intc
controller. Many new vectors are added and multiple processor variants
including 7750, 7750s, 7750r, 7751 and 7751r should all have the correct
vectors hooked up.
IRLM interrupts can be enabled using ipr_irq_enable_irlm() which now is
marked as __init.
The only change since the first version is per cpu type plat_irq_setup().
Signed-off-by: Magnus Damm <da...@ig...>
---
Tested on r2d hardware.
arch/sh/Kconfig | 6
arch/sh/configs/landisk_defconfig | 2
arch/sh/configs/lboxre2_defconfig | 2
arch/sh/configs/rts7751r2d_defconfig | 2
arch/sh/configs/se7750_defconfig | 2
arch/sh/kernel/cpu/sh4/setup-sh7750.c | 285 ++++++++++++++++++++++++---------
arch/sh/mm/Kconfig | 10 -
include/asm-sh/hw_irq.h | 2
8 files changed, 231 insertions(+), 80 deletions(-)
--- 0004/arch/sh/Kconfig
+++ work/arch/sh/Kconfig 2007-07-20 17:57:10.000000000 +0900
@@ -212,6 +212,7 @@ config SOLUTION_ENGINE
config SH_SOLUTION_ENGINE
bool "SolutionEngine"
select SOLUTION_ENGINE
+ select CPU_HAS_IPR_IRQ
depends on CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7750
help
Select SolutionEngine if configuring for a Hitachi SH7709
@@ -244,6 +245,7 @@ config SH_7722_SOLUTION_ENGINE
config SH_7751_SOLUTION_ENGINE
bool "SolutionEngine7751"
select SOLUTION_ENGINE
+ select CPU_HAS_IPR_IRQ
depends on CPU_SUBTYPE_SH7751
help
Select 7751 SolutionEngine if configuring for a Hitachi SH7751
@@ -321,6 +323,7 @@ config SH_MPC1211
config SH_SH03
bool "Interface CTP/PCI-SH03"
depends on CPU_SUBTYPE_SH7751 && BROKEN
+ select CPU_HAS_IPR_IRQ
select SYS_SUPPORTS_PCI
help
CTP/PCI-SH03 is a CPU module computer that is produced
@@ -330,6 +333,7 @@ config SH_SH03
config SH_SECUREEDGE5410
bool "SecureEdge5410"
depends on CPU_SUBTYPE_SH7751R
+ select CPU_HAS_IPR_IRQ
select SYS_SUPPORTS_PCI
help
Select SecureEdge5410 if configuring for a SnapGear SH board.
@@ -384,6 +388,7 @@ config SH_LANDISK
config SH_TITAN
bool "TITAN"
depends on CPU_SUBTYPE_SH7751R
+ select CPU_HAS_IPR_IRQ
select SYS_SUPPORTS_PCI
help
Select Titan if you are configuring for a Nimble Microsystems
@@ -392,6 +397,7 @@ config SH_TITAN
config SH_SHMIN
bool "SHMIN"
depends on CPU_SUBTYPE_SH7706
+ select CPU_HAS_IPR_IRQ
help
Select SHMIN if configuring for the SHMIN board.
--- 0001/arch/sh/configs/landisk_defconfig
+++ work/arch/sh/configs/landisk_defconfig 2007-07-20 17:57:10.000000000 +0900
@@ -217,7 +217,7 @@ CONFIG_SH_FPU=y
# CONFIG_SH_DSP is not set
# CONFIG_SH_STORE_QUEUES is not set
CONFIG_CPU_HAS_INTEVT=y
-CONFIG_CPU_HAS_IPR_IRQ=y
+CONFIG_CPU_HAS_INTC_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
CONFIG_CPU_HAS_PTEA=y
--- 0001/arch/sh/configs/lboxre2_defconfig
+++ work/arch/sh/configs/lboxre2_defconfig 2007-07-20 17:57:10.000000000 +0900
@@ -222,7 +222,7 @@ CONFIG_SH_FPU=y
# CONFIG_SH_DSP is not set
# CONFIG_SH_STORE_QUEUES is not set
CONFIG_CPU_HAS_INTEVT=y
-CONFIG_CPU_HAS_IPR_IRQ=y
+CONFIG_CPU_HAS_INTC_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
CONFIG_CPU_HAS_PTEA=y
--- 0006/arch/sh/configs/rts7751r2d_defconfig
+++ work/arch/sh/configs/rts7751r2d_defconfig 2007-07-20 17:57:10.000000000 +0900
@@ -218,7 +218,7 @@ CONFIG_SH_FPU=y
# CONFIG_SH_DSP is not set
# CONFIG_SH_STORE_QUEUES is not set
CONFIG_CPU_HAS_INTEVT=y
-CONFIG_CPU_HAS_IPR_IRQ=y
+CONFIG_CPU_HAS_INTC_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
CONFIG_CPU_HAS_PTEA=y
--- 0001/arch/sh/configs/se7750_defconfig
+++ work/arch/sh/configs/se7750_defconfig 2007-07-20 17:57:10.000000000 +0900
@@ -226,7 +226,7 @@ CONFIG_SH_FPU=y
# CONFIG_SH_DSP is not set
# CONFIG_SH_STORE_QUEUES is not set
CONFIG_CPU_HAS_INTEVT=y
-CONFIG_CPU_HAS_IPR_IRQ=y
+CONFIG_CPU_HAS_INTC_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
CONFIG_CPU_HAS_PTEA=y
--- 0001/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ work/arch/sh/kernel/cpu/sh4/setup-sh7750.c 2007-07-20 18:24:24.000000000 +0900
@@ -82,88 +82,233 @@ static int __init sh7750_devices_setup(v
}
__initcall(sh7750_devices_setup);
-static struct ipr_data ipr_irq_table[] = {
- /* IRQ, IPR-idx, shift, priority */
- { 16, 0, 12, 2 }, /* TMU0 TUNI*/
- { 17, 0, 12, 2 }, /* TMU1 TUNI */
- { 18, 0, 4, 2 }, /* TMU2 TUNI */
- { 19, 0, 4, 2 }, /* TMU2 TIPCI */
- { 27, 1, 12, 2 }, /* WDT ITI */
- { 20, 0, 0, 2 }, /* RTC ATI (alarm) */
- { 21, 0, 0, 2 }, /* RTC PRI (period) */
- { 22, 0, 0, 2 }, /* RTC CUI (carry) */
- { 23, 1, 4, 3 }, /* SCI ERI */
- { 24, 1, 4, 3 }, /* SCI RXI */
- { 25, 1, 4, 3 }, /* SCI TXI */
- { 40, 2, 4, 3 }, /* SCIF ERI */
- { 41, 2, 4, 3 }, /* SCIF RXI */
- { 42, 2, 4, 3 }, /* SCIF BRI */
- { 43, 2, 4, 3 }, /* SCIF TXI */
- { 34, 2, 8, 7 }, /* DMAC DMTE0 */
- { 35, 2, 8, 7 }, /* DMAC DMTE1 */
- { 36, 2, 8, 7 }, /* DMAC DMTE2 */
- { 37, 2, 8, 7 }, /* DMAC DMTE3 */
- { 38, 2, 8, 7 }, /* DMAC DMAE */
-};
-
-static unsigned long ipr_offsets[] = {
- 0xffd00004UL, /* 0: IPRA */
- 0xffd00008UL, /* 1: IPRB */
- 0xffd0000cUL, /* 2: IPRC */
- 0xffd00010UL, /* 3: IPRD */
-};
-
-static struct ipr_desc ipr_irq_desc = {
- .ipr_offsets = ipr_offsets,
- .nr_offsets = ARRAY_SIZE(ipr_offsets),
-
- .ipr_data = ipr_irq_table,
- .nr_irqs = ARRAY_SIZE(ipr_irq_table),
-
- .chip = {
- .name = "IPR-sh7750",
- },
-};
-
-#ifdef CONFIG_CPU_SUBTYPE_SH7751
-static struct ipr_data ipr_irq_table_sh7751[] = {
- { 44, 2, 8, 7 }, /* DMAC DMTE4 */
- { 45, 2, 8, 7 }, /* DMAC DMTE5 */
- { 46, 2, 8, 7 }, /* DMAC DMTE6 */
- { 47, 2, 8, 7 }, /* DMAC DMTE7 */
- /* The following use INTC_INPRI00 for masking, which is a 32-bit
- register, not a 16-bit register like the IPRx registers, so it
- would need special support */
- /*{ 72, INTPRI00, 8, ? },*/ /* TMU3 TUNI */
- /*{ 76, INTPRI00, 12, ? },*/ /* TMU4 TUNI */
-};
-
-static struct ipr_desc ipr_irq_desc_sh7751 = {
- .ipr_offsets = ipr_offsets,
- .nr_offsets = ARRAY_SIZE(ipr_offsets),
-
- .ipr_data = ipr_irq_table_sh7751,
- .nr_irqs = ARRAY_SIZE(ipr_irq_table_sh7751),
-
- .chip = {
- .name = "IPR-sh7751",
- },
+enum {
+ UNUSED = 0,
+
+ /* interrupt sources */
+
+ IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
+ HUDI, GPIOI,
+ DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
+ DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
+ DMAC_DMAE,
+ PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
+ PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
+ TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
+ RTC_ATI, RTC_PRI, RTC_CUI,
+ SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
+ SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
+ WDT,
+ REF_RCMI, REF_ROVI,
+
+ /* interrupt groups */
+
+ DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
+};
+
+static struct intc_vect vectors[] = {
+ INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
+ INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
+ INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
+ INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
+ INTC_VECT(RTC_CUI, 0x4c0),
+ INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
+ INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
+ INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
+ INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
+ INTC_VECT(WDT, 0x560),
+ INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
+};
+
+static struct intc_group groups[] = {
+ INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
+ INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
+ INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
+ INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
+ INTC_GROUP(REF, REF_RCMI, REF_ROVI),
+};
+
+static struct intc_prio priorities[] = {
+ INTC_PRIO(SCIF, 3),
+ INTC_PRIO(SCI1, 3),
+ INTC_PRIO(DMAC, 7),
+};
+
+static struct intc_mask_reg mask_registers[] = {
+ { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, TMU4, TMU3,
+ PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
+ PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
+ PCIC1_PCIDMA3, PCIC0_PCISERR } },
+};
+
+static struct intc_prio_reg prio_registers[] = {
+ { 0xffd00004, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
+ { 0xffd00008, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
+ { 0xffd0000c, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
+ { 0xffd00010, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
+ { 0xfe080000, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
+ TMU4, TMU3,
+ PCIC1, PCIC0_PCISERR } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
+ priorities, NULL, prio_registers, NULL);
+
+/* SH7750, SH7750S and SH7751 all have 4-channel DMA controllers */
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7751) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7091)
+
+static struct intc_vect vectors_dma4[] = {
+ INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
+ INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
+ INTC_VECT(DMAC_DMAE, 0x6c0),
+};
+
+static struct intc_group groups_dma4[] = {
+ INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
+ DMAC_DMTE3, DMAC_DMAE),
};
+
+static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
+ vectors_dma4, groups_dma4,
+ priorities, NULL, prio_registers, NULL);
+
#endif
+/* SH7750R and SH7751R both have 8-channel DMA controllers */
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
+
+static struct intc_vect vectors_dma8[] = {
+ INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
+ INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
+ INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
+ INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
+ INTC_VECT(DMAC_DMAE, 0x6c0),
+};
+
+static struct intc_group groups_dma8[] = {
+ INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
+ DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
+ DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
+};
+
+static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
+ vectors_dma8, groups_dma8,
+ priorities, NULL, prio_registers, NULL);
+
+#endif
+
+/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751) \
+ || defined(CONFIG_CPU_SUBTYPE_SH7751R)
+
+static struct intc_vect vectors_tmu34[] = {
+ INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
+};
+
+static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
+ vectors_tmu34, NULL, priorities,
+ mask_registers, prio_registers, NULL);
+
+#endif
+
+/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
+
+static struct intc_vect vectors_irlm[] = {
+ INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
+ INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
+};
+
+static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
+ priorities, NULL, prio_registers, NULL);
+
+/* SH7751 and SH7751R both have PCI */
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
+
+static struct intc_vect vectors_pci[] = {
+ INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
+ INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
+ INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
+ INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
+};
+
+static struct intc_group groups_pci[] = {
+ INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
+ PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
+};
+
+static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
+ priorities, mask_registers, prio_registers, NULL);
+
+#endif
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7091)
+
+void __init plat_irq_setup(void)
+{
+ /* same vectors for SH7750 and SH7750S except for IRLM, see below.. */
+
+ register_intc_controller(&intc_desc);
+ register_intc_controller(&intc_desc_dma4);
+}
+
+#endif
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7750R)
+
void __init plat_irq_setup(void)
{
- register_ipr_controller(&ipr_irq_desc);
-#ifdef CONFIG_CPU_SUBTYPE_SH7751
- register_ipr_controller(&ipr_irq_desc_sh7751);
+ register_intc_controller(&intc_desc);
+ register_intc_controller(&intc_desc_dma8);
+ register_intc_controller(&intc_desc_tmu34);
+}
+
#endif
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7751)
+
+void __init plat_irq_setup(void)
+{
+ register_intc_controller(&intc_desc);
+ register_intc_controller(&intc_desc_dma4);
+ register_intc_controller(&intc_desc_tmu34);
+ register_intc_controller(&intc_desc_pci);
}
+#endif
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7751R)
+
+void __init plat_irq_setup(void)
+{
+ register_intc_controller(&intc_desc);
+ register_intc_controller(&intc_desc_dma8);
+ register_intc_controller(&intc_desc_tmu34);
+ register_intc_controller(&intc_desc_pci);
+}
+
+#endif
+
#define INTC_ICR 0xffd00000UL
#define INTC_ICR_IRLM (1<<7)
/* enable individual interrupt mode for external interupts */
-void ipr_irq_enable_irlm(void)
+void __init ipr_irq_enable_irlm(void)
{
+#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
+ BUG(); /* impossible to mask interrupts on SH7750 */
+#endif
+ register_intc_controller(&intc_desc_irlm);
+
ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
}
--- 0004/arch/sh/mm/Kconfig
+++ work/arch/sh/mm/Kconfig 2007-07-20 17:57:10.000000000 +0900
@@ -120,7 +120,7 @@ config CPU_SUBTYPE_SH7712
config CPU_SUBTYPE_SH7750
bool "Support SH7750 processor"
select CPU_SH4
- select CPU_HAS_IPR_IRQ
+ select CPU_HAS_INTC_IRQ
help
Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
@@ -135,17 +135,17 @@ config CPU_SUBTYPE_SH7091
config CPU_SUBTYPE_SH7750R
bool "Support SH7750R processor"
select CPU_SH4
- select CPU_HAS_IPR_IRQ
+ select CPU_HAS_INTC_IRQ
config CPU_SUBTYPE_SH7750S
bool "Support SH7750S processor"
select CPU_SH4
- select CPU_HAS_IPR_IRQ
+ select CPU_HAS_INTC_IRQ
config CPU_SUBTYPE_SH7751
bool "Support SH7751 processor"
select CPU_SH4
- select CPU_HAS_IPR_IRQ
+ select CPU_HAS_INTC_IRQ
help
Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
or if you have a HD6417751R CPU.
@@ -153,7 +153,7 @@ config CPU_SUBTYPE_SH7751
config CPU_SUBTYPE_SH7751R
bool "Support SH7751R processor"
select CPU_SH4
- select CPU_HAS_IPR_IRQ
+ select CPU_HAS_INTC_IRQ
config CPU_SUBTYPE_SH7760
bool "Support SH7760 processor"
--- 0004/include/asm-sh/hw_irq.h
+++ work/include/asm-sh/hw_irq.h 2007-07-20 17:57:10.000000000 +0900
@@ -44,7 +44,7 @@ void register_ipr_controller(struct ipr_
/*
* Enable individual interrupt mode for external IPR IRQs.
*/
-void ipr_irq_enable_irlm(void);
+void __init ipr_irq_enable_irlm(void);
typedef unsigned char intc_enum;
|
|
From: Magnus D. <mag...@gm...> - 2007-07-20 09:03:36
|
sh: intc - add support for 7750
This patch converts the cpu specific 7750 setup code to use the new intc
controller. Many new vectors are added and multiple processor variants
including 7750, 7750s, 7750r, 7751 and 7751r should all have the correct
vectors hooked up.
IRLM interrupts can be enabled using ipr_irq_enable_irlm() which now is
marked as __init.
Signed-off-by: Magnus Damm <da...@ig...>
---
Tested on r2d hardware.
arch/sh/Kconfig | 6
arch/sh/configs/landisk_defconfig | 2
arch/sh/configs/lboxre2_defconfig | 2
arch/sh/configs/rts7751r2d_defconfig | 2
arch/sh/configs/se7750_defconfig | 2
arch/sh/kernel/cpu/sh4/setup-sh7750.c | 254 +++++++++++++++++++++++----------
arch/sh/mm/Kconfig | 10 -
include/asm-sh/hw_irq.h | 2
8 files changed, 200 insertions(+), 80 deletions(-)
--- 0004/arch/sh/Kconfig
+++ work/arch/sh/Kconfig 2007-07-20 17:43:28.000000000 +0900
@@ -212,6 +212,7 @@ config SOLUTION_ENGINE
config SH_SOLUTION_ENGINE
bool "SolutionEngine"
select SOLUTION_ENGINE
+ select CPU_HAS_IPR_IRQ
depends on CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7750
help
Select SolutionEngine if configuring for a Hitachi SH7709
@@ -244,6 +245,7 @@ config SH_7722_SOLUTION_ENGINE
config SH_7751_SOLUTION_ENGINE
bool "SolutionEngine7751"
select SOLUTION_ENGINE
+ select CPU_HAS_IPR_IRQ
depends on CPU_SUBTYPE_SH7751
help
Select 7751 SolutionEngine if configuring for a Hitachi SH7751
@@ -321,6 +323,7 @@ config SH_MPC1211
config SH_SH03
bool "Interface CTP/PCI-SH03"
depends on CPU_SUBTYPE_SH7751 && BROKEN
+ select CPU_HAS_IPR_IRQ
select SYS_SUPPORTS_PCI
help
CTP/PCI-SH03 is a CPU module computer that is produced
@@ -330,6 +333,7 @@ config SH_SH03
config SH_SECUREEDGE5410
bool "SecureEdge5410"
depends on CPU_SUBTYPE_SH7751R
+ select CPU_HAS_IPR_IRQ
select SYS_SUPPORTS_PCI
help
Select SecureEdge5410 if configuring for a SnapGear SH board.
@@ -384,6 +388,7 @@ config SH_LANDISK
config SH_TITAN
bool "TITAN"
depends on CPU_SUBTYPE_SH7751R
+ select CPU_HAS_IPR_IRQ
select SYS_SUPPORTS_PCI
help
Select Titan if you are configuring for a Nimble Microsystems
@@ -392,6 +397,7 @@ config SH_TITAN
config SH_SHMIN
bool "SHMIN"
depends on CPU_SUBTYPE_SH7706
+ select CPU_HAS_IPR_IRQ
help
Select SHMIN if configuring for the SHMIN board.
--- 0001/arch/sh/configs/landisk_defconfig
+++ work/arch/sh/configs/landisk_defconfig 2007-07-20 17:37:54.000000000 +0900
@@ -217,7 +217,7 @@ CONFIG_SH_FPU=y
# CONFIG_SH_DSP is not set
# CONFIG_SH_STORE_QUEUES is not set
CONFIG_CPU_HAS_INTEVT=y
-CONFIG_CPU_HAS_IPR_IRQ=y
+CONFIG_CPU_HAS_INTC_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
CONFIG_CPU_HAS_PTEA=y
--- 0001/arch/sh/configs/lboxre2_defconfig
+++ work/arch/sh/configs/lboxre2_defconfig 2007-07-20 17:38:16.000000000 +0900
@@ -222,7 +222,7 @@ CONFIG_SH_FPU=y
# CONFIG_SH_DSP is not set
# CONFIG_SH_STORE_QUEUES is not set
CONFIG_CPU_HAS_INTEVT=y
-CONFIG_CPU_HAS_IPR_IRQ=y
+CONFIG_CPU_HAS_INTC_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
CONFIG_CPU_HAS_PTEA=y
--- 0006/arch/sh/configs/rts7751r2d_defconfig
+++ work/arch/sh/configs/rts7751r2d_defconfig 2007-07-20 17:38:34.000000000 +0900
@@ -218,7 +218,7 @@ CONFIG_SH_FPU=y
# CONFIG_SH_DSP is not set
# CONFIG_SH_STORE_QUEUES is not set
CONFIG_CPU_HAS_INTEVT=y
-CONFIG_CPU_HAS_IPR_IRQ=y
+CONFIG_CPU_HAS_INTC_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
CONFIG_CPU_HAS_PTEA=y
--- 0001/arch/sh/configs/se7750_defconfig
+++ work/arch/sh/configs/se7750_defconfig 2007-07-20 17:38:53.000000000 +0900
@@ -226,7 +226,7 @@ CONFIG_SH_FPU=y
# CONFIG_SH_DSP is not set
# CONFIG_SH_STORE_QUEUES is not set
CONFIG_CPU_HAS_INTEVT=y
-CONFIG_CPU_HAS_IPR_IRQ=y
+CONFIG_CPU_HAS_INTC_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
CONFIG_CPU_HAS_PTEA=y
--- 0001/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ work/arch/sh/kernel/cpu/sh4/setup-sh7750.c 2007-07-20 17:46:53.000000000 +0900
@@ -82,80 +82,189 @@ static int __init sh7750_devices_setup(v
}
__initcall(sh7750_devices_setup);
-static struct ipr_data ipr_irq_table[] = {
- /* IRQ, IPR-idx, shift, priority */
- { 16, 0, 12, 2 }, /* TMU0 TUNI*/
- { 17, 0, 12, 2 }, /* TMU1 TUNI */
- { 18, 0, 4, 2 }, /* TMU2 TUNI */
- { 19, 0, 4, 2 }, /* TMU2 TIPCI */
- { 27, 1, 12, 2 }, /* WDT ITI */
- { 20, 0, 0, 2 }, /* RTC ATI (alarm) */
- { 21, 0, 0, 2 }, /* RTC PRI (period) */
- { 22, 0, 0, 2 }, /* RTC CUI (carry) */
- { 23, 1, 4, 3 }, /* SCI ERI */
- { 24, 1, 4, 3 }, /* SCI RXI */
- { 25, 1, 4, 3 }, /* SCI TXI */
- { 40, 2, 4, 3 }, /* SCIF ERI */
- { 41, 2, 4, 3 }, /* SCIF RXI */
- { 42, 2, 4, 3 }, /* SCIF BRI */
- { 43, 2, 4, 3 }, /* SCIF TXI */
- { 34, 2, 8, 7 }, /* DMAC DMTE0 */
- { 35, 2, 8, 7 }, /* DMAC DMTE1 */
- { 36, 2, 8, 7 }, /* DMAC DMTE2 */
- { 37, 2, 8, 7 }, /* DMAC DMTE3 */
- { 38, 2, 8, 7 }, /* DMAC DMAE */
-};
-
-static unsigned long ipr_offsets[] = {
- 0xffd00004UL, /* 0: IPRA */
- 0xffd00008UL, /* 1: IPRB */
- 0xffd0000cUL, /* 2: IPRC */
- 0xffd00010UL, /* 3: IPRD */
-};
-
-static struct ipr_desc ipr_irq_desc = {
- .ipr_offsets = ipr_offsets,
- .nr_offsets = ARRAY_SIZE(ipr_offsets),
-
- .ipr_data = ipr_irq_table,
- .nr_irqs = ARRAY_SIZE(ipr_irq_table),
-
- .chip = {
- .name = "IPR-sh7750",
- },
-};
-
-#ifdef CONFIG_CPU_SUBTYPE_SH7751
-static struct ipr_data ipr_irq_table_sh7751[] = {
- { 44, 2, 8, 7 }, /* DMAC DMTE4 */
- { 45, 2, 8, 7 }, /* DMAC DMTE5 */
- { 46, 2, 8, 7 }, /* DMAC DMTE6 */
- { 47, 2, 8, 7 }, /* DMAC DMTE7 */
- /* The following use INTC_INPRI00 for masking, which is a 32-bit
- register, not a 16-bit register like the IPRx registers, so it
- would need special support */
- /*{ 72, INTPRI00, 8, ? },*/ /* TMU3 TUNI */
- /*{ 76, INTPRI00, 12, ? },*/ /* TMU4 TUNI */
-};
-
-static struct ipr_desc ipr_irq_desc_sh7751 = {
- .ipr_offsets = ipr_offsets,
- .nr_offsets = ARRAY_SIZE(ipr_offsets),
-
- .ipr_data = ipr_irq_table_sh7751,
- .nr_irqs = ARRAY_SIZE(ipr_irq_table_sh7751),
-
- .chip = {
- .name = "IPR-sh7751",
- },
+enum {
+ UNUSED = 0,
+
+ /* interrupt sources */
+
+ IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
+ HUDI, GPIOI,
+ DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
+ DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
+ DMAC_DMAE,
+ PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
+ PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
+ TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
+ RTC_ATI, RTC_PRI, RTC_CUI,
+ SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
+ SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
+ WDT,
+ REF_RCMI, REF_ROVI,
+
+ /* interrupt groups */
+
+ DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
+};
+
+static struct intc_vect vectors[] = {
+ INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
+ INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
+ INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
+ INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
+ INTC_VECT(RTC_CUI, 0x4c0),
+ INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
+ INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
+ INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
+ INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
+ INTC_VECT(WDT, 0x560),
+ INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
+};
+
+static struct intc_group groups[] = {
+ INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
+ INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
+ INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
+ INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
+ INTC_GROUP(REF, REF_RCMI, REF_ROVI),
+};
+
+static struct intc_prio priorities[] = {
+ INTC_PRIO(SCIF, 3),
+ INTC_PRIO(SCI1, 3),
+ INTC_PRIO(DMAC, 7),
+};
+
+static struct intc_mask_reg mask_registers[] = {
+ { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, TMU4, TMU3,
+ PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
+ PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
+ PCIC1_PCIDMA3, PCIC0_PCISERR } },
+};
+
+static struct intc_prio_reg prio_registers[] = {
+ { 0xffd00004, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
+ { 0xffd00008, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
+ { 0xffd0000c, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
+ { 0xffd00010, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
+ { 0xfe080000, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
+ TMU4, TMU3,
+ PCIC1, PCIC0_PCISERR } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
+ priorities, NULL, prio_registers, NULL);
+
+/* SH7750, SH7750S and SH7751 all have 4-channel DMA controllers */
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7750S) \
+ || defined(CONFIG_CPU_SUBTYPE_SH7751)
+
+static struct intc_vect vectors_dma4[] = {
+ INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
+ INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
+ INTC_VECT(DMAC_DMAE, 0x6c0),
+};
+
+static struct intc_group groups_dma4[] = {
+ INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
+ DMAC_DMTE3, DMAC_DMAE),
+};
+
+static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
+ vectors_dma4, groups_dma4,
+ priorities, NULL, prio_registers, NULL);
+
+#endif
+
+/* SH7750R and SH7751R both have 8-channel DMA controllers */
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
+
+static struct intc_vect vectors_dma8[] = {
+ INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
+ INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
+ INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
+ INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
+ INTC_VECT(DMAC_DMAE, 0x6c0),
+};
+
+static struct intc_group groups_dma8[] = {
+ INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
+ DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
+ DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
};
+
+static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
+ vectors_dma8, groups_dma8,
+ priorities, NULL, prio_registers, NULL);
+
+#endif
+
+/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751) \
+ || defined(CONFIG_CPU_SUBTYPE_SH7751R)
+
+static struct intc_vect vectors_tmu34[] = {
+ INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
+};
+
+static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
+ vectors_tmu34, NULL, priorities,
+ mask_registers, prio_registers, NULL);
+
+#endif
+
+/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
+
+static struct intc_vect vectors_irlm[] = {
+ INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
+ INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
+};
+
+static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
+ priorities, NULL, prio_registers, NULL);
+
+/* SH7751 and SH7751R both have PCI */
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
+
+static struct intc_vect vectors_pci[] = {
+ INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
+ INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
+ INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
+ INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
+};
+
+static struct intc_group groups_pci[] = {
+ INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
+ PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
+};
+
+static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
+ priorities, mask_registers, prio_registers, NULL);
+
#endif
void __init plat_irq_setup(void)
{
- register_ipr_controller(&ipr_irq_desc);
-#ifdef CONFIG_CPU_SUBTYPE_SH7751
- register_ipr_controller(&ipr_irq_desc_sh7751);
+ register_intc_controller(&intc_desc);
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7750S) \
+ || defined(CONFIG_CPU_SUBTYPE_SH7751)
+ register_intc_controller(&intc_desc_dma4);
+#endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
+ register_intc_controller(&intc_desc_dma8);
+#endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751) \
+ || defined(CONFIG_CPU_SUBTYPE_SH7751R)
+ register_intc_controller(&intc_desc_tmu34);
+#endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
+ register_intc_controller(&intc_desc_pci);
#endif
}
@@ -163,7 +272,12 @@ void __init plat_irq_setup(void)
#define INTC_ICR_IRLM (1<<7)
/* enable individual interrupt mode for external interupts */
-void ipr_irq_enable_irlm(void)
+void __init ipr_irq_enable_irlm(void)
{
+#if defined(CONFIG_CPU_SUBTYPE_SH7750)
+ BUG(); /* impossible to mask interrupts on SH7750 */
+#endif
+ register_intc_controller(&intc_desc_irlm);
+
ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
}
--- 0004/arch/sh/mm/Kconfig
+++ work/arch/sh/mm/Kconfig 2007-07-20 17:02:34.000000000 +0900
@@ -120,7 +120,7 @@ config CPU_SUBTYPE_SH7712
config CPU_SUBTYPE_SH7750
bool "Support SH7750 processor"
select CPU_SH4
- select CPU_HAS_IPR_IRQ
+ select CPU_HAS_INTC_IRQ
help
Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
@@ -135,17 +135,17 @@ config CPU_SUBTYPE_SH7091
config CPU_SUBTYPE_SH7750R
bool "Support SH7750R processor"
select CPU_SH4
- select CPU_HAS_IPR_IRQ
+ select CPU_HAS_INTC_IRQ
config CPU_SUBTYPE_SH7750S
bool "Support SH7750S processor"
select CPU_SH4
- select CPU_HAS_IPR_IRQ
+ select CPU_HAS_INTC_IRQ
config CPU_SUBTYPE_SH7751
bool "Support SH7751 processor"
select CPU_SH4
- select CPU_HAS_IPR_IRQ
+ select CPU_HAS_INTC_IRQ
help
Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
or if you have a HD6417751R CPU.
@@ -153,7 +153,7 @@ config CPU_SUBTYPE_SH7751
config CPU_SUBTYPE_SH7751R
bool "Support SH7751R processor"
select CPU_SH4
- select CPU_HAS_IPR_IRQ
+ select CPU_HAS_INTC_IRQ
config CPU_SUBTYPE_SH7760
bool "Support SH7760 processor"
--- 0004/include/asm-sh/hw_irq.h
+++ work/include/asm-sh/hw_irq.h 2007-07-20 17:27:57.000000000 +0900
@@ -44,7 +44,7 @@ void register_ipr_controller(struct ipr_
/*
* Enable individual interrupt mode for external IPR IRQs.
*/
-void ipr_irq_enable_irlm(void);
+void __init ipr_irq_enable_irlm(void);
typedef unsigned char intc_enum;
|
|
From: Magnus D. <mag...@gm...> - 2007-07-20 08:01:27
|
sh: update r2d defconfig and fix SH7751R pci compliation This patch updates the r2d board support in a few ways: - CPU_SUBTYPE_SH7751R is selected in the defconfig to play well with the r2d board Kconfig entry. Without this the defconfig results in no board enabled. - Enable EARLY_PRINTK. - Enable SH_STANDARD_BIOS - this works well for early printk on the r2d board. - Add "earlyprink=bios" to the cmdline for early serial port output by default. - CONFIG_SUBTYPE_SH7751R support is added to the sh-specific pci makefile. Signed-off-by: Magnus Damm <da...@ig...> --- arch/sh/configs/rts7751r2d_defconfig | 6 +++--- arch/sh/drivers/pci/Makefile | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) --- 0001/arch/sh/configs/rts7751r2d_defconfig +++ work/arch/sh/configs/rts7751r2d_defconfig 2007-07-20 16:43:57.000000000 +0900 @@ -155,7 +155,7 @@ CONFIG_CPU_SH4=y # CONFIG_CPU_SUBTYPE_SH7091 is not set # CONFIG_CPU_SUBTYPE_SH7750R is not set # CONFIG_CPU_SUBTYPE_SH7750S is not set -CONFIG_CPU_SUBTYPE_SH7751=y +# CONFIG_CPU_SUBTYPE_SH7751 is not set CONFIG_CPU_SUBTYPE_SH7751R=y # CONFIG_CPU_SUBTYPE_SH7760 is not set # CONFIG_CPU_SUBTYPE_SH4_202 is not set @@ -280,7 +280,7 @@ CONFIG_ZERO_PAGE_OFFSET=0x00010000 CONFIG_BOOT_LINK_OFFSET=0x00800000 # CONFIG_UBC_WAKEUP is not set CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="console=tty0 console=ttySC0,115200 root=/dev/sda1" +CONFIG_CMDLINE="console=tty0 console=ttySC0,115200 root=/dev/sda1 earlyprintk=bios" # # Bus options @@ -1323,7 +1323,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_SH_STANDARD_BIOS is not set +CONFIG_SH_STANDARD_BIOS=y CONFIG_EARLY_SCIF_CONSOLE=y CONFIG_EARLY_SCIF_CONSOLE_PORT=0xffe80000 CONFIG_EARLY_PRINTK=y --- 0001/arch/sh/drivers/pci/Makefile +++ work/arch/sh/drivers/pci/Makefile 2007-07-20 16:42:36.000000000 +0900 @@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_AUTO) += pci-auto.o obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o +obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o |
|
From: Paul M. <le...@li...> - 2007-07-20 07:34:56
|
On Fri, Jul 20, 2007 at 04:21:47PM +0900, Magnus Damm wrote: > sh: zero terminate 8250 platform data for r2d board > > struct plat_serial8250_port should contain a terminating zero entry > Applied, thanks. |
|
From: Magnus D. <mag...@gm...> - 2007-07-20 07:22:56
|
sh: zero terminate 8250 platform data for r2d board
struct plat_serial8250_port should contain a terminating zero entry
Signed-off-by: Magnus Damm <da...@ig...>
---
arch/sh/boards/renesas/rts7751r2d/setup.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
--- 0001/arch/sh/boards/renesas/rts7751r2d/setup.c
+++ work/arch/sh/boards/renesas/rts7751r2d/setup.c 2007-07-20 16:10:13.000000000 +0900
@@ -86,7 +86,10 @@ static struct plat_serial8250_port uart_
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.regshift = 2,
.uartclk = (9600 * 16),
- }
+ },
+ {
+ 0,
+ },
};
static struct platform_device uart_device = {
|
|
From: Mike F. <va...@ge...> - 2007-07-20 06:09:19
|
On Thursday 19 July 2007, Adrian McMenamin wrote:
> Signed-off by: Adrian McMenamin <ad...@mc...>
> @@ -183,6 +183,7 @@ int dmac_search_free_channel(const char *dev_id)
> return result;
>
> atomic_set(&channel->busy, 1);
> +
> return channel->chan;
> }
>
> @@ -194,7 +195,6 @@ int request_dma(unsigned int chan, const char
> *dev_id)
> struct dma_channel *channel = { 0 };
> struct dma_info *info = get_dma_info(chan);
> int result;
> -
> channel = get_dma_channel(chan);
> if (atomic_xchg(&channel->busy, 1))
> return -EBUSY;
> @@ -387,7 +388,7 @@ int register_dmac(struct dma_info *info)
> }
>
> list_add(&info->list, ®istered_dmac_list);
> -
> +
> return 0;
> }
> EXPORT_SYMBOL(register_dmac);
seems like whitespace noise in here ...
-mike
|
|
From: Paul M. <le...@li...> - 2007-07-20 03:11:58
|
On Fri, Jul 20, 2007 at 10:42:29AM +0900, Magnus Damm wrote: > sh: intc - improve group support On Fri, Jul 20, 2007 at 10:42:47AM +0900, Magnus Damm wrote: > sh: intc - add support for 7780 Both applied, thanks. |
|
From: Magnus D. <mag...@gm...> - 2007-07-20 01:43:48
|
sh: intc - add support for 7780
This patch converts the cpu specific 7780 setup code to use the new intc
controller. Many new vectors are added and also support for external interrupt
sense configuration. So with this patch it is now possible to configure
external interrupt pins as edge or level triggered using set_irq_type().
No external interrupts are registered by default. Use plat_irq_setup_pins()
to select between IRQ or IRL mode.
This patch also fixes the Alarm IRQ for the RTC.
Signed-off-by: Magnus Damm <da...@ig...>
---
Tested on a Highlander 7780
Applies to git sh-2.6 40f89da50eec1cab277677c5f6c00355a11fddc5
Needs intc group support
arch/sh/Kconfig | 1
arch/sh/configs/r7780mp_defconfig | 2
arch/sh/configs/r7780rp_defconfig | 2
arch/sh/configs/se7780_defconfig | 1
arch/sh/kernel/cpu/sh4a/setup-sh7780.c | 231 +++++++++++++++++++++++++++-----
arch/sh/mm/Kconfig | 2
include/asm-sh/hw_irq.h | 3
7 files changed, 204 insertions(+), 38 deletions(-)
--- 0001/arch/sh/Kconfig
+++ work/arch/sh/Kconfig 2007-07-20 10:02:38.000000000 +0900
@@ -253,6 +253,7 @@ config SH_7780_SOLUTION_ENGINE
bool "SolutionEngine7780"
select SOLUTION_ENGINE
select SYS_SUPPORTS_PCI
+ select CPU_HAS_INTC2_IRQ
depends on CPU_SUBTYPE_SH7780
help
Select 7780 SolutionEngine if configuring for a Renesas SH7780
--- 0001/arch/sh/configs/r7780mp_defconfig
+++ work/arch/sh/configs/r7780mp_defconfig 2007-07-20 09:55:27.000000000 +0900
@@ -191,7 +191,7 @@ CONFIG_SH_FPU=y
CONFIG_SH_STORE_QUEUES=y
CONFIG_SPECULATIVE_EXECUTION=y
CONFIG_CPU_HAS_INTEVT=y
-CONFIG_CPU_HAS_INTC2_IRQ=y
+CONFIG_CPU_HAS_INTC_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
#
--- 0001/arch/sh/configs/r7780rp_defconfig
+++ work/arch/sh/configs/r7780rp_defconfig 2007-07-20 09:55:27.000000000 +0900
@@ -241,7 +241,7 @@ CONFIG_SH_FPU=y
CONFIG_SH_STORE_QUEUES=y
CONFIG_SPECULATIVE_EXECUTION=y
CONFIG_CPU_HAS_INTEVT=y
-CONFIG_CPU_HAS_INTC2_IRQ=y
+CONFIG_CPU_HAS_INTC_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
#
--- 0001/arch/sh/configs/se7780_defconfig
+++ work/arch/sh/configs/se7780_defconfig 2007-07-20 10:00:20.000000000 +0900
@@ -218,6 +218,7 @@ CONFIG_SH_FPU=y
# CONFIG_SH_STORE_QUEUES is not set
CONFIG_CPU_HAS_INTEVT=y
CONFIG_CPU_HAS_INTC2_IRQ=y
+CONFIG_CPU_HAS_INTC_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
#
--- 0001/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ work/arch/sh/kernel/cpu/sh4a/setup-sh7780.c 2007-07-20 09:59:07.000000000 +0900
@@ -30,7 +30,7 @@ static struct resource rtc_resources[] =
},
[3] = {
/* Alarm IRQ */
- .start = 23,
+ .start = 20,
.flags = IORESOURCE_IRQ,
},
};
@@ -78,44 +78,205 @@ static int __init sh7780_devices_setup(v
}
__initcall(sh7780_devices_setup);
-static struct intc2_data intc2_irq_table[] = {
- { 28, 0, 24, 0, 0, 2 }, /* TMU0 */
+enum {
+ UNUSED = 0,
- { 21, 1, 0, 0, 2, 2 },
- { 22, 1, 1, 0, 2, 2 },
- { 23, 1, 2, 0, 2, 2 },
-
- { 40, 8, 24, 0, 3, 3 }, /* SCIF0 ERI */
- { 41, 8, 24, 0, 3, 3 }, /* SCIF0 RXI */
- { 42, 8, 24, 0, 3, 3 }, /* SCIF0 BRI */
- { 43, 8, 24, 0, 3, 3 }, /* SCIF0 TXI */
-
- { 76, 8, 16, 0, 4, 3 }, /* SCIF1 ERI */
- { 77, 8, 16, 0, 4, 3 }, /* SCIF1 RXI */
- { 78, 8, 16, 0, 4, 3 }, /* SCIF1 BRI */
- { 79, 8, 16, 0, 4, 3 }, /* SCIF1 TXI */
-
- { 64, 0x10, 8, 0, 14, 2 }, /* PCIC0 */
- { 65, 0x10, 0, 0, 15, 2 }, /* PCIC1 */
- { 66, 0x14, 24, 0, 16, 2 }, /* PCIC2 */
- { 67, 0x14, 16, 0, 17, 2 }, /* PCIC3 */
- { 68, 0x14, 8, 0, 18, 2 }, /* PCIC4 */
-};
-
-static struct intc2_desc intc2_irq_desc __read_mostly = {
- .prio_base = 0xffd40000,
- .msk_base = 0xffd40038,
- .mskclr_base = 0xffd4003c,
+ /* interrupt sources */
- .intc2_data = intc2_irq_table,
- .nr_irqs = ARRAY_SIZE(intc2_irq_table),
-
- .chip = {
- .name = "INTC2-sh7780",
- },
+ IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
+ IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
+ IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
+ IRL_HHLL, IRL_HHLH, IRL_HHHL,
+
+ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+ RTC_ATI, RTC_PRI, RTC_CUI,
+ WDT,
+ TMU0, TMU1, TMU2, TMU2_TICPI,
+ HUDI,
+ DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE,
+ SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
+ DMAC0_DMINT4, DMAC0_DMINT5, DMAC1_DMINT6, DMAC1_DMINT7,
+ CMT, HAC,
+ PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
+ PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
+ SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
+ SIOF, HSPI,
+ MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
+ DMAC1_DMINT8, DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11,
+ TMU3, TMU4, TMU5,
+ SSI,
+ FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
+ GPIOI0, GPIOI1, GPIOI2, GPIOI3,
+
+ /* interrupt groups */
+
+ RTC, TMU012, DMAC0, SCIF0, DMAC45, DMAC1,
+ PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO,
+};
+
+static struct intc_vect vectors[] = {
+ INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
+ INTC_VECT(RTC_CUI, 0x4c0),
+ INTC_VECT(WDT, 0x560),
+ INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
+ INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
+ INTC_VECT(HUDI, 0x600),
+ INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
+ INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0),
+ INTC_VECT(DMAC0_DMAE, 0x6c0),
+ INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
+ INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
+ INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0),
+ INTC_VECT(DMAC1_DMINT6, 0x7c0), INTC_VECT(DMAC1_DMINT7, 0x7e0),
+ INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
+ INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
+ INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
+ INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
+ INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
+ INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
+ INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0),
+ INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0),
+ INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
+ INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
+ INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
+ INTC_VECT(DMAC1_DMINT8, 0xd80), INTC_VECT(DMAC1_DMINT9, 0xda0),
+ INTC_VECT(DMAC1_DMINT10, 0xdc0), INTC_VECT(DMAC1_DMINT11, 0xde0),
+ INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
+ INTC_VECT(TMU5, 0xe40),
+ INTC_VECT(SSI, 0xe80),
+ INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20),
+ INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60),
+ INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0),
+ INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
+};
+
+static struct intc_group groups[] = {
+ INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
+ INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
+ INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
+ DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
+ INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
+ INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
+ DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
+ INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
+ INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
+ INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
+ INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
+ INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
+ FLCTL_FLTRQ0, FLCTL_FLTRQ1),
+ INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
+};
+
+static struct intc_prio priorities[] = {
+ INTC_PRIO(SCIF0, 3),
+ INTC_PRIO(SCIF1, 3),
+};
+
+static struct intc_mask_reg mask_registers[] = {
+ { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
+ { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
+ SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
+ PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
+ HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
+};
+
+static struct intc_prio_reg prio_registers[] = {
+ { 0xffd40000, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, TMU2, TMU2_TICPI } },
+ { 0xffd40004, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
+ { 0xffd40008, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
+ { 0xffd4000c, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
+ { 0xffd40010, 32, 8, /* INT2PRI4 */ { CMT, HAC, PCISERR, PCIINTA, } },
+ { 0xffd40014, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
+ PCIINTD, PCIC5 } },
+ { 0xffd40018, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
+ { 0xffd4001c, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities,
+ mask_registers, prio_registers, NULL);
+
+/* Support for external interrupt pins in IRQ mode */
+
+static struct intc_vect irq_vectors[] = {
+ INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
+ INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
+ INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
+ INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
+};
+
+static struct intc_mask_reg irq_mask_registers[] = {
+ { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
+ { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_prio_reg irq_prio_registers[] = {
+ { 0xffd00010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
+ IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_sense_reg irq_sense_registers[] = {
+ { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
+ IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC(intc_irq_desc, "sh7780-irq", irq_vectors,
+ NULL, NULL, irq_mask_registers, irq_prio_registers,
+ irq_sense_registers);
+
+/* External interrupt pins in IRL mode */
+
+static struct intc_vect irl_vectors[] = {
+ INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
+ INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
+ INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
+ INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
+ INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
+ INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
+ INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
+ INTC_VECT(IRL_HHHL, 0x3c0),
+};
+
+static struct intc_mask_reg irl3210_mask_registers[] = {
+ { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
+ { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
+ IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
+ IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
+ IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
+};
+
+static struct intc_mask_reg irl7654_mask_registers[] = {
+ { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
+ IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
+ IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
+ IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
};
+static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
+ NULL, NULL, irl7654_mask_registers, NULL, NULL);
+
+static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
+ NULL, NULL, irl3210_mask_registers, NULL, NULL);
+
void __init plat_irq_setup(void)
{
- register_intc2_controller(&intc2_irq_desc);
+ register_intc_controller(&intc_desc);
+}
+
+void __init plat_irq_setup_pins(int mode)
+{
+ switch (mode) {
+ case IRQ_MODE_IRQ:
+ register_intc_controller(&intc_irq_desc);
+ break;
+ case IRQ_MODE_IRL7654:
+ register_intc_controller(&intc_irl7654_desc);
+ break;
+ case IRQ_MODE_IRL3210:
+ register_intc_controller(&intc_irl3210_desc);
+ break;
+ default:
+ BUG();
+ }
}
--- 0001/arch/sh/mm/Kconfig
+++ work/arch/sh/mm/Kconfig 2007-07-20 09:55:27.000000000 +0900
@@ -189,7 +189,7 @@ config CPU_SUBTYPE_SH7770
config CPU_SUBTYPE_SH7780
bool "Support SH7780 processor"
select CPU_SH4A
- select CPU_HAS_INTC2_IRQ
+ select CPU_HAS_INTC_IRQ
config CPU_SUBTYPE_SH7785
bool "Support SH7785 processor"
--- 0001/include/asm-sh/hw_irq.h
+++ work/include/asm-sh/hw_irq.h 2007-07-20 09:55:27.000000000 +0900
@@ -115,4 +115,7 @@ void __init register_intc_controller(str
void __init plat_irq_setup(void);
+enum { IRQ_MODE_IRQ, IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
+void __init plat_irq_setup_pins(int mode);
+
#endif /* __ASM_SH_HW_IRQ_H */
|
|
From: Magnus D. <mag...@gm...> - 2007-07-20 01:43:34
|
sh: intc - improve group support
This patch improves intc group support, ie it makes it possible to group
interrupts together and mask / unmask the entire group. This also works
with priorities, so setting a priority for an entire group is also possible.
This patch is needed to properly support certain processors such as the 7780.
Fixes for NULL pointers in DECLARE_INTC_DESC() are also included.
Signed-off-by: Magnus Damm <da...@ig...>
---
Tested on a Highlander 7780
Applies to git sh-2.6 40f89da50eec1cab277677c5f6c00355a11fddc5
arch/sh/kernel/cpu/irq/intc.c | 93 ++++++++++++++++++++++++++++++++---------
1 file changed, 73 insertions(+), 20 deletions(-)
--- 0001/arch/sh/kernel/cpu/irq/intc.c
+++ work/arch/sh/kernel/cpu/irq/intc.c 2007-07-20 09:46:03.000000000 +0900
@@ -244,13 +244,33 @@ static unsigned int __init intc_find_pri
return REG_FN_ERROR;
}
+static intc_enum __init intc_grp_id(struct intc_desc *desc, intc_enum enum_id)
+{
+ struct intc_group *g = desc->groups;
+ unsigned int i, j;
+
+ for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
+ g = desc->groups + i;
+
+ for (j = 0; g->enum_ids[j]; j++) {
+ if (g->enum_ids[j] != enum_id)
+ continue;
+
+ return g->enum_id;
+ }
+ }
+
+ return 0;
+}
+
static unsigned int __init intc_prio_value(struct intc_desc *desc,
- intc_enum enum_id)
+ intc_enum enum_id, int do_grps)
{
+ struct intc_prio *p = desc->priorities;
unsigned int i;
- for (i = 0; i < desc->nr_priorities; i++) {
- struct intc_prio *p = desc->priorities + i;
+ for (i = 0; p && enum_id && i < desc->nr_priorities; i++) {
+ p = desc->priorities + i;
if (p->enum_id != enum_id)
continue;
@@ -258,16 +278,24 @@ static unsigned int __init intc_prio_val
return p->priority;
}
- return 1; /* default to the lowest priority if no priority is set */
+ if (do_grps)
+ return intc_prio_value(desc, intc_grp_id(desc, enum_id), 0);
+
+ /* default to the lowest priority possible if no priority is set
+ * - this needs to be at least 2 for 5-bit priorities on 7780
+ */
+
+ return 2;
}
static unsigned int __init intc_mask_data(struct intc_desc *desc,
- intc_enum enum_id)
+ intc_enum enum_id, int do_grps)
{
+ struct intc_mask_reg *mr = desc->mask_regs;
unsigned int i, j, fn;
- for (i = 0; i < desc->nr_mask_regs; i++) {
- struct intc_mask_reg *mr = desc->mask_regs + i;
+ for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
+ mr = desc->mask_regs + i;
for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
if (mr->enum_ids[j] != enum_id)
@@ -281,16 +309,20 @@ static unsigned int __init intc_mask_dat
}
}
+ if (do_grps)
+ return intc_mask_data(desc, intc_grp_id(desc, enum_id), 0);
+
return 0;
}
static unsigned int __init intc_prio_data(struct intc_desc *desc,
- intc_enum enum_id)
+ intc_enum enum_id, int do_grps)
{
+ struct intc_prio_reg *pr = desc->prio_regs;
unsigned int i, j, fn, bit, prio;
- for (i = 0; i < desc->nr_prio_regs; i++) {
- struct intc_prio_reg *pr = desc->prio_regs + i;
+ for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
+ pr = desc->prio_regs + i;
for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
if (pr->enum_ids[j] != enum_id)
@@ -300,7 +332,7 @@ static unsigned int __init intc_prio_dat
if (fn == REG_FN_ERROR)
return 0;
- prio = intc_prio_value(desc, enum_id);
+ prio = intc_prio_value(desc, enum_id, 1);
bit = pr->reg_width - ((j + 1) * pr->field_width);
BUG_ON(bit < 0);
@@ -309,27 +341,48 @@ static unsigned int __init intc_prio_dat
}
}
+ if (do_grps)
+ return intc_prio_data(desc, intc_grp_id(desc, enum_id), 0);
+
return 0;
}
static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id,
unsigned int irq)
{
- unsigned int mask_data = intc_mask_data(desc, enum_id);
- unsigned int prio_data = intc_prio_data(desc, enum_id);
- unsigned int data = mask_data ? mask_data : prio_data;
+ unsigned int data[2], primary;
+
+ /* Prefer single interrupt source bitmap over other combinations:
+ * 1. bitmap, single interrupt source
+ * 2. priority, single interrupt source
+ * 3. bitmap, multiple interrupt sources (groups)
+ * 4. priority, multiple interrupt sources (groups)
+ */
- BUG_ON(!data);
+ data[0] = intc_mask_data(desc, enum_id, 0);
+ data[1] = intc_prio_data(desc, enum_id, 0);
+
+ primary = 0;
+ if (!data[0] && data[1])
+ primary = 1;
+
+ data[0] = data[0] ? data[0] : intc_mask_data(desc, enum_id, 1);
+ data[1] = data[1] ? data[1] : intc_prio_data(desc, enum_id, 1);
+
+ if (!data[primary])
+ primary ^= 1;
+
+ BUG_ON(!data[primary]); /* must have primary masking method */
disable_irq_nosync(irq);
set_irq_chip_and_handler_name(irq, &desc->chip,
handle_level_irq, "level");
- set_irq_chip_data(irq, (void *)data);
-
- /* set priority */
+ set_irq_chip_data(irq, (void *)data[primary]);
- if (prio_data)
- intc_reg_fns[_INTC_FN(prio_data)].enable(desc, prio_data);
+ /* enable secondary masking method if present */
+ if (data[!primary])
+ intc_reg_fns[_INTC_FN(data[!primary])].enable(desc,
+ data[!primary]);
/* irq should be disabled by default */
desc->chip.mask(irq);
|
|
From: Adrian M. <ad...@ne...> - 2007-07-19 23:14:45
|
Signed-off by: Adrian McMenamin <ad...@mc...>
diff --git a/arch/sh/drivers/dma/dma-api.c
b/arch/sh/drivers/dma/dma-api.c
index cf8e119..0c9b3bc 100644
--- a/arch/sh/drivers/dma/dma-api.c
+++ b/arch/sh/drivers/dma/dma-api.c
@@ -31,8 +31,8 @@ struct dma_info *get_dma_info(unsigned int chan)
* the channel is.
*/
list_for_each_entry(info, ®istered_dmac_list, list) {
- if ((chan < info->first_channel_nr) ||
- (chan >= info->first_channel_nr + info->nr_channels))
+ if ((chan < info->first_vchannel_nr) ||
+ (chan >= info->first_vchannel_nr + info->nr_channels))
continue;
return info;
@@ -82,7 +82,7 @@ struct dma_channel *get_dma_channel(unsigned int chan)
for (i = 0; i < info->nr_channels; i++) {
channel = &info->channels[i];
- if (channel->chan == chan)
+ if (channel->chan == (chan - info->first_vchannel_nr))
return channel;
}
@@ -183,6 +183,7 @@ int dmac_search_free_channel(const char *dev_id)
return result;
atomic_set(&channel->busy, 1);
+
return channel->chan;
}
@@ -194,7 +195,6 @@ int request_dma(unsigned int chan, const char
*dev_id)
struct dma_channel *channel = { 0 };
struct dma_info *info = get_dma_info(chan);
int result;
-
channel = get_dma_channel(chan);
if (atomic_xchg(&channel->busy, 1))
return -EBUSY;
@@ -369,6 +369,7 @@ int register_dmac(struct dma_info *info)
}
total_channels = get_nr_channels();
+ info->first_vchannel_nr = total_channels;
for (i = 0; i < info->nr_channels; i++) {
struct dma_channel *chan = &info->channels[i];
@@ -387,7 +388,7 @@ int register_dmac(struct dma_info *info)
}
list_add(&info->list, ®istered_dmac_list);
-
+
return 0;
}
EXPORT_SYMBOL(register_dmac);
diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h
index 6034d4a..4c75b70 100644
--- a/include/asm-sh/dma.h
+++ b/include/asm-sh/dma.h
@@ -111,6 +111,7 @@ struct dma_info {
struct list_head list;
int first_channel_nr;
+ int first_vchannel_nr;
};
struct dma_chan_caps {
|
|
From: Paul M. <le...@li...> - 2007-07-19 18:18:22
|
On Thu, Jul 19, 2007 at 05:50:44PM +0530, Ashay Jaiswal wrote: > Hello Sir, > > I am trying to boot Linux-2.6.22.1 kernel on Highlander 7780 board. > I am using "r7780rp_defconfig" as my kernel configuration file: > > The kernel hangs at following point: > > scsi1 : sata_sil > ata1: SATA max UDMA/100 cmd 0xfd000280 ctl 0xfd00028a bmdma 0xfd000200 > irq 1 > ata2: SATA max UDMA/100 cmd 0xfd0002c0 ctl 0xfd0002ca bmdma 0xfd000208 > irq 1 > ata1: SATA link down (SStatus 0 SControl 310) > ata2: SATA link down (SStatus 0 SControl 310) > scsi2 : pata_platform > ata3: PATA max PIO0 cmd 0xb4001000 ctl 0xb400080c bmdma 0x00000000 irq 4 > First, are you sure you actually have an RP board, or is it the MP? If it's the latter, please select the MP support, as this will us totally different IRQ vectors. The other potential issue is if this is really an RP board, you're probably being bitten by the bus-width problem on the CF slot vs what libata expects it can do. We never bothered to work around this, since the RP boards were never in mass circulation, so the solution there is simply to disable pata_platform. |
|
From: Adrian M. <ad...@ne...> - 2007-07-18 23:06:05
|
Have to admit I am pretty tired so might not be thinking straight,
but...
025 struct dma_info *get_dma_info(unsigned int chan)
026 {
027 struct dma_info *info;
028
029 /*
030 * Look for each DMAC's range to determine who the owner of
031 * the channel is.
032 */
033 list_for_each_entry(info, ®istered_dmac_list, list) {
034 if ((chan < info->first_channel_nr) ||
035 (chan >= info->first_channel_nr + info->nr_channels))
036 continue;
037
038 return info;
039 }
040
041 return NULL;
042 }
To me the above looks like it has mixed up channels and virtual channels - eg when called with chan = 4 (for pvr2) it ought to return NULL
Is that right?
|
|
From: Magnus D. <mag...@gm...> - 2007-07-18 09:32:03
|
On 7/17/07, Jeff Garzik <je...@ga...> wrote: > Paul Mundt wrote: > > On Tue, Jul 17, 2007 at 05:42:52PM +0900, Magnus Damm wrote: > >> pata_platform: Fix NULL pointer dereference > >> > >> The platform-specific structures may leave pdev->dev.platform_data as NULL. > >> > >> Signed-off-by: Magnus Damm <da...@ig...> > > What is your suggestion for moving linux-2.6.git forward? This fix solves the problem for me and Paul seems to be happy with it as well. Jeff, can you please pick up this patch so we can unbreak things for rc1? Thanks! / magnus |
|
From: Paul M. <le...@li...> - 2007-07-18 09:02:09
|
On Wed, Jul 18, 2007 at 10:21:33AM +0900, Magnus Damm wrote: > sh: intc - add support for 7722 processor On Wed, Jul 18, 2007 at 10:22:10AM +0900, Magnus Damm wrote: > sh: clean up interrupt code for solution engine 7722 board On Wed, Jul 18, 2007 at 12:33:46PM +0900, Magnus Damm wrote: > sh: intc - shared IPR and INTC2 controller V2 On Wed, Jul 18, 2007 at 12:34:01PM +0900, Magnus Damm wrote: > sh: plat_irq_setup() V2 All applied, thanks. Some stylistic formatting was needed, and your editor also left quite a bit of trailing whitespace all over the place. In the future, please run your patches through scripts/checkpatch.pl to warn on these sorts of things -- or upgrade your text editor to something reasonable :-) |
|
From: Magnus D. <mag...@gm...> - 2007-07-18 03:34:52
|
sh: plat_irq_setup() V2
This patch unifies the cpu specific interrupt setup functions for interrupt
controller blocks such as ipr, intc2 and intc. There is no point in having
separate functions for each interrupt controller, so let's clean this up.
Version two removes the #ifdefs around plat_irq_setup() in irq.c
Signed-off-by: Magnus Damm <da...@ig...>
---
Applies to git linux-2.6 a5fcaa210626a79465321e344c91a6a7dc3881fa
Needs to be applied on top of sh7722 intc code.
arch/sh/kernel/cpu/sh2/setup-sh7619.c | 2 +-
arch/sh/kernel/cpu/sh2a/setup-sh7206.c | 2 +-
arch/sh/kernel/cpu/sh3/setup-sh7705.c | 2 +-
arch/sh/kernel/cpu/sh3/setup-sh7709.c | 2 +-
arch/sh/kernel/cpu/sh3/setup-sh7710.c | 2 +-
arch/sh/kernel/cpu/sh4/setup-sh7750.c | 2 +-
arch/sh/kernel/cpu/sh4/setup-sh7760.c | 8 ++------
arch/sh/kernel/cpu/sh4a/setup-sh7722.c | 2 +-
arch/sh/kernel/cpu/sh4a/setup-sh7780.c | 2 +-
arch/sh/kernel/cpu/sh4a/setup-sh7785.c | 2 +-
arch/sh/kernel/cpu/sh4a/setup-shx3.c | 2 +-
arch/sh/kernel/irq.c | 9 +--------
include/asm-sh/hw_irq.h | 4 ++--
13 files changed, 15 insertions(+), 26 deletions(-)
--- 0001/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ work/arch/sh/kernel/cpu/sh2/setup-sh7619.c 2007-07-18 10:17:44.000000000 +0900
@@ -88,7 +88,7 @@ static struct ipr_desc ipr_irq_desc = {
},
};
-void __init init_IRQ_ipr(void)
+void __init plat_irq_setup(void)
{
register_ipr_controller(&ipr_irq_desc);
}
--- 0001/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ work/arch/sh/kernel/cpu/sh2a/setup-sh7206.c 2007-07-18 10:17:44.000000000 +0900
@@ -107,7 +107,7 @@ static struct ipr_desc ipr_irq_desc = {
},
};
-void __init init_IRQ_ipr(void)
+void __init plat_irq_setup(void)
{
register_ipr_controller(&ipr_irq_desc);
}
--- 0001/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ work/arch/sh/kernel/cpu/sh3/setup-sh7705.c 2007-07-18 10:17:44.000000000 +0900
@@ -92,7 +92,7 @@ static struct ipr_desc ipr_irq_desc = {
},
};
-void __init init_IRQ_ipr(void)
+void __init plat_irq_setup(void)
{
register_ipr_controller(&ipr_irq_desc);
}
--- 0001/arch/sh/kernel/cpu/sh3/setup-sh7709.c
+++ work/arch/sh/kernel/cpu/sh3/setup-sh7709.c 2007-07-18 10:17:44.000000000 +0900
@@ -139,7 +139,7 @@ static struct ipr_desc ipr_irq_desc = {
},
};
-void __init init_IRQ_ipr(void)
+void __init plat_irq_setup(void)
{
register_ipr_controller(&ipr_irq_desc);
}
--- 0001/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ work/arch/sh/kernel/cpu/sh3/setup-sh7710.c 2007-07-18 10:17:44.000000000 +0900
@@ -101,7 +101,7 @@ static struct ipr_desc ipr_irq_desc = {
},
};
-void __init init_IRQ_ipr(void)
+void __init plat_irq_setup(void)
{
register_ipr_controller(&ipr_irq_desc);
}
--- 0001/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ work/arch/sh/kernel/cpu/sh4/setup-sh7750.c 2007-07-18 10:17:44.000000000 +0900
@@ -151,7 +151,7 @@ static struct ipr_desc ipr_irq_desc_sh77
};
#endif
-void __init init_IRQ_ipr(void)
+void __init plat_irq_setup(void)
{
register_ipr_controller(&ipr_irq_desc);
#ifdef CONFIG_CPU_SUBTYPE_SH7751
--- 0001/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ work/arch/sh/kernel/cpu/sh4/setup-sh7760.c 2007-07-18 10:17:44.000000000 +0900
@@ -109,11 +109,6 @@ static struct intc2_desc intc2_irq_desc
},
};
-void __init init_IRQ_intc2(void)
-{
- register_intc2_controller(&intc2_irq_desc);
-}
-
static struct ipr_data ipr_irq_table[] = {
/* IRQ, IPR-idx, shift, priority */
{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
@@ -163,7 +158,8 @@ static struct ipr_desc ipr_irq_desc = {
},
};
-void __init init_IRQ_ipr(void)
+void __init plat_irq_setup(void)
{
+ register_intc2_controller(&intc2_irq_desc);
register_ipr_controller(&ipr_irq_desc);
}
--- 0003/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ work/arch/sh/kernel/cpu/sh4a/setup-sh7722.c 2007-07-18 10:17:44.000000000 +0900
@@ -194,7 +194,7 @@ static struct intc_sense_reg sense_regis
DECLARE_INTC_DESC(intc_desc, "sh7722", vectors, groups, priorities,
mask_registers, prio_registers, sense_registers);
-void __init init_IRQ_ipr(void)
+void __init plat_irq_setup(void)
{
register_intc_controller(&intc_desc);
}
--- 0001/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ work/arch/sh/kernel/cpu/sh4a/setup-sh7780.c 2007-07-18 10:17:44.000000000 +0900
@@ -115,7 +115,7 @@ static struct intc2_desc intc2_irq_desc
},
};
-void __init init_IRQ_intc2(void)
+void __init plat_irq_setup(void)
{
register_intc2_controller(&intc2_irq_desc);
}
--- 0001/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ work/arch/sh/kernel/cpu/sh4a/setup-sh7785.c 2007-07-18 10:17:44.000000000 +0900
@@ -110,7 +110,7 @@ static struct intc2_desc intc2_irq_desc
},
};
-void __init init_IRQ_intc2(void)
+void __init plat_irq_setup(void)
{
register_intc2_controller(&intc2_irq_desc);
}
--- 0001/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ work/arch/sh/kernel/cpu/sh4a/setup-shx3.c 2007-07-18 10:17:44.000000000 +0900
@@ -79,7 +79,7 @@ static struct intc2_desc intc2_irq_desc
},
};
-void __init init_IRQ_intc2(void)
+void __init plat_irq_setup(void)
{
register_intc2_controller(&intc2_irq_desc);
}
--- 0001/arch/sh/kernel/irq.c
+++ work/arch/sh/kernel/irq.c 2007-07-18 11:41:21.000000000 +0900
@@ -253,14 +253,7 @@ void __init init_IRQ(void)
#ifdef CONFIG_CPU_HAS_PINT_IRQ
init_IRQ_pint();
#endif
-
-#ifdef CONFIG_CPU_HAS_INTC2_IRQ
- init_IRQ_intc2();
-#endif
-
-#ifdef CONFIG_CPU_HAS_IPR_IRQ
- init_IRQ_ipr();
-#endif
+ plat_irq_setup();
/* Perform the machine specific initialisation */
if (sh_mv.mv_init_irq)
--- 0002/include/asm-sh/hw_irq.h
+++ work/include/asm-sh/hw_irq.h 2007-07-18 10:17:44.000000000 +0900
@@ -23,7 +23,6 @@ struct intc2_desc {
};
void register_intc2_controller(struct intc2_desc *);
-void init_IRQ_intc2(void);
struct ipr_data {
unsigned char irq;
@@ -41,7 +40,6 @@ struct ipr_desc {
};
void register_ipr_controller(struct ipr_desc *);
-void init_IRQ_ipr(void);
/*
* Enable individual interrupt mode for external IPR IRQs.
@@ -115,4 +113,6 @@ static struct intc_desc symbol = { \
void __init register_intc_controller(struct intc_desc *desc);
+void __init plat_irq_setup(void);
+
#endif /* __ASM_SH_HW_IRQ_H */
|
|
From: Magnus D. <mag...@gm...> - 2007-07-18 03:34:37
|
sh: intc - shared IPR and INTC2 controller V2
This is the second version of the shared interrupt controller patch for the
sh architecture, fixing up handling of intc_reg_fns[].
The thee main advantages with this controller over the exisitng ones are:
- Both priority (ipr) and bitmap (intc2) registers are supported
- External pin sense configuration is supported, ie edge vs level triggered
- CPU/Board specific code maps 1:1 with datasheet for easy verification
This controller can easily coexist with the current IPR and INTC2 controllers,
but the idea is that CPU:s/Boards should be moved over to this controller
over time so we have a single code base to maintain.
Signed-off-by: Magnus Damm <da...@ig...>
---
Tested on a Solution Engline 7722
Applies to git sh-2.6 a927beaf01291e299d8fda858e6c8837f2e9a14c
arch/sh/Kconfig | 3
arch/sh/kernel/cpu/irq/Makefile | 1
arch/sh/kernel/cpu/irq/intc.c | 343 +++++++++++++++++++++++++++++++++++++++
include/asm-sh/hw_irq.h | 68 +++++++
4 files changed, 415 insertions(+)
--- 0001/arch/sh/Kconfig
+++ work/arch/sh/Kconfig 2007-07-18 11:49:39.000000000 +0900
@@ -178,6 +178,9 @@ config CPU_HAS_PINT_IRQ
config CPU_HAS_MASKREG_IRQ
bool
+config CPU_HAS_INTC_IRQ
+ bool
+
config CPU_HAS_INTC2_IRQ
bool
--- 0001/arch/sh/kernel/cpu/irq/Makefile
+++ work/arch/sh/kernel/cpu/irq/Makefile 2007-07-18 11:49:39.000000000 +0900
@@ -6,4 +6,5 @@ obj-y += imask.o
obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o
obj-$(CONFIG_CPU_HAS_PINT_IRQ) += pint.o
obj-$(CONFIG_CPU_HAS_MASKREG_IRQ) += maskreg.o
+obj-$(CONFIG_CPU_HAS_INTC_IRQ) += intc.o
obj-$(CONFIG_CPU_HAS_INTC2_IRQ) += intc2.o
--- /dev/null
+++ work/arch/sh/kernel/cpu/irq/intc.c 2007-07-18 12:03:24.000000000 +0900
@@ -0,0 +1,343 @@
+/*
+ * Shared interrupt handling code for IPR and INT2C types of IRQs.
+ *
+ * Copyright (C) 2007 Magnus Damm
+ *
+ * Based on intc2.c and ipr.c
+ *
+ * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
+ * Copyright (C) 2000 Kazumoto Kojima
+ * Copyright (C) 2001 David J. Mckay (dav...@st...)
+ * Copyright (C) 2003 Takashi Kusuda <kus...@hi...>
+ * Copyright (C) 2005, 2006 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+
+#define _INTC_MK(fn, idx, bit, value) \
+ ((fn) << 24 | ((value) << 16) | ((idx) << 8) | (bit))
+#define _INTC_FN(h) (h >> 24)
+#define _INTC_VALUE(h) ((h >> 16) & 0xff)
+#define _INTC_IDX(h) ((h >> 8) & 0xff)
+#define _INTC_BIT(h) (h & 0xff)
+
+#define _INTC_PTR(desc, member, data) \
+ (desc->member + _INTC_IDX(data))
+
+static inline struct intc_desc *get_intc_desc(unsigned int irq)
+{
+ struct irq_chip *chip = get_irq_chip(irq);
+ return (void *)((char *)chip - offsetof(struct intc_desc, chip));
+}
+
+static inline unsigned int set_field(unsigned int value,
+ unsigned int field_value,
+ unsigned int width,
+ unsigned int shift)
+{
+ value &= ~(((1 << width) - 1) << shift);
+ value |= field_value << shift;
+ return value;
+}
+
+static inline unsigned int set_prio_field(struct intc_desc *desc,
+ unsigned int value,
+ unsigned int priority,
+ unsigned int data)
+{
+ unsigned int width = _INTC_PTR(desc, prio_regs, data)->field_width;
+
+ return set_field(value, priority, width, _INTC_BIT(data));
+}
+
+static void disable_prio_16(struct intc_desc *desc, unsigned int data)
+{
+ unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
+
+ ctrl_outw(set_prio_field(desc, ctrl_inw(addr), 0, data), addr);
+}
+
+static void enable_prio_16(struct intc_desc *desc, unsigned int data)
+{
+ unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
+ unsigned int prio = _INTC_VALUE(data);
+
+ ctrl_outw(set_prio_field(desc, ctrl_inw(addr), prio, data), addr);
+}
+
+static void disable_prio_32(struct intc_desc *desc, unsigned int data)
+{
+ unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
+
+ ctrl_outl(set_prio_field(desc, ctrl_inl(addr), 0, data), addr);
+}
+
+static void enable_prio_32(struct intc_desc *desc, unsigned int data)
+{
+ unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
+ unsigned int prio = _INTC_VALUE(data);
+
+ ctrl_outl(set_prio_field(desc, ctrl_inl(addr), prio, data), addr);
+}
+
+static void disable_mask_8(struct intc_desc *desc, unsigned int data)
+{
+ ctrl_outb(1 << _INTC_BIT(data),
+ _INTC_PTR(desc, mask_regs, data)->set_reg);
+}
+
+static void enable_mask_8(struct intc_desc *desc, unsigned int data)
+{
+ ctrl_outb(1 << _INTC_BIT(data),
+ _INTC_PTR(desc, mask_regs, data)->clr_reg);
+}
+
+static void disable_mask_32(struct intc_desc *desc, unsigned int data)
+{
+ ctrl_outl(1 << _INTC_BIT(data),
+ _INTC_PTR(desc, mask_regs, data)->set_reg);
+}
+
+static void enable_mask_32(struct intc_desc *desc, unsigned int data)
+{
+ ctrl_outl(1 << _INTC_BIT(data),
+ _INTC_PTR(desc, mask_regs, data)->clr_reg);
+}
+
+enum { REG_FN_ERROR=0,
+ REG_FN_MASK_8, REG_FN_MASK_32,
+ REG_FN_PRIO_16, REG_FN_PRIO_32 };
+
+static struct {
+ void (*enable)(struct intc_desc *, unsigned int);
+ void (*disable)(struct intc_desc *, unsigned int);
+} intc_reg_fns[] = {
+ [REG_FN_MASK_8] = { enable_mask_8, disable_mask_8 },
+ [REG_FN_MASK_32] = { enable_mask_32, disable_mask_32 },
+ [REG_FN_PRIO_16] = { enable_prio_16, disable_prio_16 },
+ [REG_FN_PRIO_32] = { enable_prio_32, disable_prio_32 },
+};
+
+static void intc_enable(unsigned int irq)
+{
+ struct intc_desc *desc = get_intc_desc(irq);
+ unsigned int data = (unsigned int) get_irq_chip_data(irq);
+
+ intc_reg_fns[_INTC_FN(data)].enable(desc, data);
+}
+
+static void intc_disable(unsigned int irq)
+{
+ struct intc_desc *desc = get_intc_desc(irq);
+ unsigned int data = (unsigned int) get_irq_chip_data(irq);
+
+ intc_reg_fns[_INTC_FN(data)].disable(desc, data);
+}
+
+static void set_sense_16(struct intc_desc *desc, unsigned int data)
+{
+ unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
+ unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
+ unsigned int bit = _INTC_BIT(data);
+ unsigned int value = _INTC_VALUE(data);
+
+ ctrl_outw(set_field(ctrl_inw(addr), value, width, bit), addr);
+}
+
+static void set_sense_32(struct intc_desc *desc, unsigned int data)
+{
+ unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
+ unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
+ unsigned int bit = _INTC_BIT(data);
+ unsigned int value = _INTC_VALUE(data);
+
+ ctrl_outl(set_field(ctrl_inl(addr), value, width, bit), addr);
+}
+
+#define VALID(x) (x | 0x80)
+
+static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
+ [IRQ_TYPE_EDGE_FALLING] = VALID(0),
+ [IRQ_TYPE_EDGE_RISING] = VALID(1),
+ [IRQ_TYPE_LEVEL_LOW] = VALID(2),
+ [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
+};
+
+static int intc_set_sense(unsigned int irq, unsigned int type)
+{
+ struct intc_desc *desc = get_intc_desc(irq);
+ unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
+ unsigned int i, j, data, bit;
+ intc_enum enum_id = 0;
+
+ for (i = 0; i < desc->nr_vectors; i++) {
+ struct intc_vect *vect = desc->vectors + i;
+
+ if (evt2irq(vect->vect) != irq)
+ continue;
+
+ enum_id = vect->enum_id;
+ break;
+ }
+
+ if (!enum_id || !value)
+ return -EINVAL;
+
+ value ^= VALID(0);
+
+ for (i = 0; i < desc->nr_sense_regs; i++) {
+ struct intc_sense_reg *sr = desc->sense_regs + i;
+
+ for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
+ if (sr->enum_ids[j] != enum_id)
+ continue;
+
+ bit = sr->reg_width - ((j + 1) * sr->field_width);
+ data = _INTC_MK(0, i, bit, value);
+
+ switch(sr->reg_width) {
+ case 16: set_sense_16(desc, data); return 0;
+ case 32: set_sense_32(desc, data); return 0;
+ }
+ }
+ }
+
+ return -EINVAL;
+}
+
+static unsigned int __init intc_find_mask_handler(unsigned int width)
+{
+ switch (width) {
+ case 8: return REG_FN_MASK_8;
+ case 32: return REG_FN_MASK_32;
+ }
+
+ BUG();
+ return REG_FN_ERROR;
+}
+
+static unsigned int __init intc_find_prio_handler(unsigned int width)
+{
+ switch (width) {
+ case 16: return REG_FN_PRIO_16;
+ case 32: return REG_FN_PRIO_32;
+ }
+
+ BUG();
+ return REG_FN_ERROR;
+}
+
+static unsigned int __init intc_prio_value(struct intc_desc *desc,
+ intc_enum enum_id)
+{
+ unsigned int i;
+
+ for (i = 0; i < desc->nr_priorities; i++) {
+ struct intc_prio *p = desc->priorities + i;
+
+ if (p->enum_id != enum_id)
+ continue;
+
+ return p->priority;
+ }
+
+ return 1; /* default to the lowest priority if no priority is set */
+}
+
+static unsigned int __init intc_mask_data(struct intc_desc *desc,
+ intc_enum enum_id)
+{
+ unsigned int i, j, fn;
+
+ for (i = 0; i < desc->nr_mask_regs; i++) {
+ struct intc_mask_reg *mr = desc->mask_regs + i;
+
+ for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
+ if (mr->enum_ids[j] != enum_id)
+ continue;
+
+ fn = intc_find_mask_handler(mr->reg_width);
+ if (fn == REG_FN_ERROR)
+ return 0;
+
+ return _INTC_MK(fn, i, (mr->reg_width - 1) - j, 0);
+ }
+ }
+
+ return 0;
+}
+
+static unsigned int __init intc_prio_data(struct intc_desc *desc,
+ intc_enum enum_id)
+{
+ unsigned int i, j, fn, bit, prio;
+
+ for (i = 0; i < desc->nr_prio_regs; i++) {
+ struct intc_prio_reg *pr = desc->prio_regs + i;
+
+ for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
+ if (pr->enum_ids[j] != enum_id)
+ continue;
+
+ fn = intc_find_prio_handler(pr->reg_width);
+ if (fn == REG_FN_ERROR)
+ return 0;
+
+ prio = intc_prio_value(desc, enum_id);
+ bit = pr->reg_width - ((j + 1) * pr->field_width);
+
+ BUG_ON(bit < 0);
+
+ return _INTC_MK(fn, i, bit, prio);
+ }
+ }
+
+ return 0;
+}
+
+static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id,
+ unsigned int irq)
+{
+ unsigned int mask_data = intc_mask_data(desc, enum_id);
+ unsigned int prio_data = intc_prio_data(desc, enum_id);
+ unsigned int data = mask_data ? mask_data : prio_data;
+
+ BUG_ON(!data);
+
+ disable_irq_nosync(irq);
+ set_irq_chip_and_handler_name(irq, &desc->chip,
+ handle_level_irq, "level");
+ set_irq_chip_data(irq, (void *)data);
+
+ /* set priority */
+
+ if (prio_data)
+ intc_reg_fns[_INTC_FN(prio_data)].enable(desc, prio_data);
+
+ /* irq should be disabled by default */
+
+ desc->chip.mask(irq);
+}
+
+void __init register_intc_controller(struct intc_desc *desc)
+{
+ unsigned int i;
+
+ desc->chip.mask = intc_disable;
+ desc->chip.unmask = intc_enable;
+ desc->chip.mask_ack = intc_disable;
+ desc->chip.set_type = intc_set_sense;
+
+ for (i = 0; i < desc->nr_vectors; i++) {
+ struct intc_vect *vect = desc->vectors + i;
+
+ intc_register_irq(desc, vect->enum_id, evt2irq(vect->vect));
+ }
+}
--- 0001/include/asm-sh/hw_irq.h
+++ work/include/asm-sh/hw_irq.h 2007-07-18 11:49:39.000000000 +0900
@@ -1,6 +1,7 @@
#ifndef __ASM_SH_HW_IRQ_H
#define __ASM_SH_HW_IRQ_H
+#include <linux/init.h>
#include <asm/atomic.h>
extern atomic_t irq_err_count;
@@ -47,4 +48,71 @@ void init_IRQ_ipr(void);
*/
void ipr_irq_enable_irlm(void);
+typedef unsigned char intc_enum;
+
+struct intc_vect {
+ intc_enum enum_id;
+ unsigned short vect;
+};
+
+#define INTC_VECT(enum_id, vect) { enum_id, vect }
+
+struct intc_prio {
+ intc_enum enum_id;
+ unsigned char priority;
+};
+
+#define INTC_PRIO(enum_id, prio) { enum_id, prio }
+
+struct intc_group {
+ intc_enum enum_id;
+ intc_enum *enum_ids;
+};
+
+#define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } }
+
+struct intc_mask_reg {
+ unsigned long set_reg, clr_reg, reg_width;
+ intc_enum enum_ids[32];
+};
+
+struct intc_prio_reg {
+ unsigned long reg, reg_width, field_width;
+ intc_enum enum_ids[16];
+};
+
+struct intc_sense_reg {
+ unsigned long reg, reg_width, field_width;
+ intc_enum enum_ids[16];
+};
+
+struct intc_desc {
+ struct intc_vect *vectors;
+ unsigned int nr_vectors;
+ struct intc_group *groups;
+ unsigned int nr_groups;
+ struct intc_prio *priorities;
+ unsigned int nr_priorities;
+ struct intc_mask_reg *mask_regs;
+ unsigned int nr_mask_regs;
+ struct intc_prio_reg *prio_regs;
+ unsigned int nr_prio_regs;
+ struct intc_sense_reg *sense_regs;
+ unsigned int nr_sense_regs;
+ struct irq_chip chip;
+};
+
+#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
+#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
+ priorities, mask_regs, prio_regs, sense_regs) \
+static struct intc_desc symbol = { \
+ _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
+ _INTC_ARRAY(priorities), \
+ _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
+ _INTC_ARRAY(sense_regs), \
+ .chip.name = chipname, \
+}
+
+void __init register_intc_controller(struct intc_desc *desc);
+
#endif /* __ASM_SH_HW_IRQ_H */
|
|
From: Magnus D. <mag...@gm...> - 2007-07-18 02:40:28
|
On 7/18/07, Paul Mundt <le...@li...> wrote: > On Wed, Jul 18, 2007 at 10:23:05AM +0900, Magnus Damm wrote: > > --- 0001/arch/sh/kernel/irq.c > > +++ work/arch/sh/kernel/irq.c 2007-07-17 17:01:58.000000000 +0900 > > @@ -254,12 +254,9 @@ void __init init_IRQ(void) > > init_IRQ_pint(); > > #endif > > > > -#ifdef CONFIG_CPU_HAS_INTC2_IRQ > > - init_IRQ_intc2(); > > -#endif > > - > > -#ifdef CONFIG_CPU_HAS_IPR_IRQ > > - init_IRQ_ipr(); > > +#if defined(CONFIG_CPU_HAS_INTC2_IRQ) || defined(CONFIG_CPU_HAS_INTC2_IRQ) || \ > > + defined(CONFIG_CPU_HAS_INTC_IRQ) > > + plat_irq_setup(); > > #endif > > > > Eek. How about a weak dummy symbol instead? You've also double-cased > CPU_HAS_INTC2_IRQ, whereas I assume you meant to make one of them > CPU_HAS_IPR_IRQ. On the other hand, is it really a valid state for any > CPU not to have at least one of INTC2/INTC/IPR? In which case, make the > reference to the symbol explicit, and let the linker whine. Yeah, both ugly and incorrect - great. Sorry about that. I was thinking along the lines of a weak dummy symbol, but then I hesitated because I didn't know if it was needed at all. And then I looked at for instance setup-sh7300.c which doesn't seem to have any interrupt controller setup code at all... I guess the best solution is to require plat_irq_setup() to be present and fix the broken platforms. Thanks. / magnus |
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