Update of /cvsroot/linuxsh/linux/arch/sh/kernel/cpu/sh4
In directory sc8-pr-cvs6.sourceforge.net:/tmp/cvs-serv27220/arch/sh/kernel/cpu/sh4
Modified Files:
probe.c
Log Message:
Support for optional L2 cache on newer SH-4A CPUs.
Index: probe.c
===================================================================
RCS file: /cvsroot/linuxsh/linux/arch/sh/kernel/cpu/sh4/probe.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- probe.c 9 Aug 2006 03:53:04 -0000 1.8
+++ probe.c 10 Aug 2006 09:58:51 -0000 1.9
@@ -54,6 +54,16 @@
cpu_data->dcache.linesz = L1_CACHE_BYTES;
/*
+ * Setup some generic flags we can probe
+ */
+ if ((cvr & 0x02000000) == 0)
+ cpu_data->flags |= CPU_HAS_L2_CACHE;
+ if ((cvr & 0x10000000) == 0)
+ cpu_data->flags |= CPU_HAS_DSP;
+ if ((cvr & 0x20000000) == 1)
+ cpu_data->flags |= CPU_HAS_FPU;
+
+ /*
* Probe the underlying processor version/revision and
* adjust cpu_data setup accordingly.
*/
@@ -181,5 +191,30 @@
cpu_data->dcache.way_size = cpu_data->dcache.sets *
cpu_data->dcache.linesz;
+ /*
+ * Setup the L2 cache desc
+ *
+ * SH-4A's have an optional PIPT L2.
+ */
+ if (cpu_data->flags & CPU_HAS_L2_CACHE) {
+ /*
+ * Size calculation is much more sensible
+ * than it is for the L1.
+ *
+ * Sizes are 128KB, 258KB, 512KB, and 1MB.
+ */
+ size = (cvr & 0xf) << 7;
+
+ BUG_ON(!size);
+
+ cpu_data->scache.way_incr = (1 << 16);
+ cpu_data->scache.entry_shift = 5;
+ cpu_data->scache.entry_mask = 0xffe0;
+ cpu_data->scache.ways = 4;
+ cpu_data->scache.linesz = L1_CACHE_BYTES;
+ cpu_data->scache.sets = size /
+ (cpu_data->scache.linesz * cpu_data->scache.ways);
+ }
+
return 0;
}
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