Re: [Linuxptp-users] LinuxPTP on Cyclone V SoC
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Re: [Linuxptp-users] LinuxPTP on Cyclone V SoC
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From: Arthur D. <art...@cy...> - 2018-12-05 19:04:31
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<html><head></head><body><div style="font-family: Verdana;font-size: 12.0px;"><div>A brief update:<br/>
On the Cyclone V SoC device the clk_ptp_ref can either be the internal emac clock (derivative of the osc1_clk) or an external clock (e.g. from the fpga).<br/>
I need to use an external clock, but the stmmac drivers in kernel version 4.1.22 appears to only support the internal clock.<br/>
This seems to be fixed in later kernel versions (e.g .4.18), but when using version 4.18 linuxptp generates error messages in my system:<br/>
ptp4l -m -q -i eth0 -H -s:<br/>
socfpga-dwmac ff702000.ethernet eth0: No support for HW time stamping<br/>
ptp4l[36.915]: ioctl SIOCSHWTSTAMP failed: Operation not supported<br/>
ptp4l[36.915]: port 1: INITIALIZING to FAULTY on FAULT_DETECTED <br/>
(FT_UNSPECIFIED)<br/>
ptp4l[36.915]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE<br/>
<br/>
So I decided to keep the 4.1.22 version, and using 4.18 as a reference I hard coded the 4.1.22 driver to use the external ptp clock.<br/>
<br/>
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c <br/>
b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c<br/>
old mode 100644<br/>
new mode 100755<br/>
index ae690dd..0aa52d6<br/>
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c<br/>
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c<br/>
@@ -236,8 +236,8 @@ static int socfpga_dwmac_setup(struct socfpga_dwmac <br/>
*dwmac)<br/>
int phymode = dwmac->interface;<br/>
u32 reg_offset = dwmac->reg_offset;<br/>
u32 reg_shift = dwmac->reg_shift;<br/>
- u32 ctrl, val;<br/>
-<br/>
+ u32 ctrl, val, module;<br/>
+<br/>
switch (phymode) {<br/>
case PHY_INTERFACE_MODE_RGMII:<br/>
case PHY_INTERFACE_MODE_RGMII_ID:<br/>
@@ -268,8 +268,16 @@ static int socfpga_dwmac_setup(struct socfpga_dwmac <br/>
*dwmac)<br/>
ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);<br/>
ctrl |= val << reg_shift;<br/>
<br/>
+ //Hard code ptp clock source to f2h_ptp_ref_clk<br/>
+ ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);<br/>
+ regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,<br/>
+ &module);<br/>
+ module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));<br/>
+ regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,<br/>
+ module);<br/>
+<br/>
regmap_write(sys_mgr_base_addr, reg_offset, ctrl);<br/>
-<br/>
+<br/>
/* Deassert reset for the phy configuration to be sampled by<br/>
* the enet controller, and operation to start in requested mode<br/>
*/<br/>
<br/>
Using this patch my system runs as expected. I.e. the PPS signal is locked to the ptp reference clock coming from the FPGA.<br/>
/AD<br/>
<br/>
<br/>
Sent: Friday, October 19, 2018 at 12:51 PM<br/>
From: "Arthur Dent" <art...@cy...><br/>
To: "John Lemonovich" <joh...@fo...>, lin...@li...<br/>
Subject: Re: [Linuxptp-users] LinuxPTP on Cyclone V SoC<br/>
Hi John, thank you for your reply.<br/>
<br/>
Yes, I have read your summery and followed the steps there, and also gone through the info in:<br/>
<a href="https://sourceforge.net/p/linuxptp/mailman/linuxptp-users/thread/034101d2d661%24ccba5120%24662ef360%24%40foresys.com/#msg35861379" target="_blank">https://sourceforge.net/p/linuxptp/mailman/linuxptp-users/thread/034101d2d661%24ccba5120%24662ef360%24%40foresys.com/#msg35861379</a><br/>
<br/>
I am using kernel 4.1.22-ltsi-RT and 4.1.33-ltsi with these patches: <br/>
<a href="https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f" target="_blank">https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f</a>[<a href="https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f" target="_blank">https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f</a>] <br/>
<br/>
Did you have to do other changes on your 4.1.33-ltsi kernel than this? <br/>
<br/>
I have also tested with later kernel versions (4.18, 4.17 and 4.9 ltsi-RT), but they all generate various PTP related errors/issues in my system. <br/>
<br/>
BR<br/>
AD<br/>
<br/>
<br/>
<br/>
> Sent: Thursday, October 18, 2018 at 4:05 PM<br/>
> From: "John Lemonovich" <joh...@fo...><br/>
> To: "Arthur Dent" <art...@cy...>, lin...@li...<br/>
> Subject: RE: [Linuxptp-users] LinuxPTP on Cyclone V SoC<br/>
><br/>
> Arthur,<br/>
><br/>
><br/>
><br/>
> Last year I was trying to get ptp working in an Arria10 SoC – and I<br/>
> eventually got it all working pretty well. Eventually I went on to get it<br/>
> working with an Intel FPGA 10GbE MAC for the A10 as well. The Cyclone V SoC<br/>
> is very similar in that the HPS EMAC is actually the ST Micro MAC (stmmac),<br/>
> which is supported by the Linux kernel and LinuxPTP for HW timestamping (see<br/>
> table below). I made a post for exactly all the steps to make it work in my<br/>
> A10. I was helped greatly by Ian Thompson and Hunter Olson, and they were<br/>
> using the Cyclone V SoC. My A10 setup with clocking was a little different<br/>
> in the Qsys editor and in the device tree, than for the Cyclone V.<br/>
><br/>
><br/>
><br/>
> You can check out my summary here:<br/>
><br/>
> <a href="https://sourceforge.net/p/linuxptp/mailman/message/35861379/" target="_blank">https://sourceforge.net/p/linuxptp/mailman/message/35861379/</a>[<a href="https://sourceforge.net/p/linuxptp/mailman/message/35861379/" target="_blank">https://sourceforge.net/p/linuxptp/mailman/message/35861379/</a>]<br/>
><br/>
><br/>
><br/>
><br/>
><br/>
> Hope this helps,<br/>
><br/>
><br/>
><br/>
><br/>
><br/>
> John Lemonovich<br/>
><br/>
><br/>
><br/>
><br/>
><br/>
><br/>
><br/>
><br/>
><br/>
> From: Arthur Dent <art...@cy...><br/>
> Sent: Wednesday, October 17, 2018 3:31 PM<br/>
> To: lin...@li...<br/>
> Subject: [Linuxptp-users] LinuxPTP on Cyclone V SoC<br/>
><br/>
><br/>
><br/>
> Hello<br/>
><br/>
> I am trying to add PTP support on a Cyclone V SoC using the HPS EMAC1, but<br/>
> have some problems making it work.<br/>
> The problems seem to be related to a wrong clock source to the PTP engine<br/>
> and/or device tree issues. I am using:<br/>
> - Linux kernel 4.1.22 ltsi RT (real time) w/patches<br/>
> - LinuxPTP 2.0<br/>
><br/>
> Steps taken:<br/>
> 1: Compiling and installing linuxptp 2.0<br/>
> 2: In Quartus Qsys: The “Enable EMAC1 precision Time Protocol (PTP) FPGA<br/>
> interface” box has been ticked, and this enables three PTP related signals:<br/>
> - emac_ptp_ref_clock: This clock has been routed through the FPGA to an IO<br/>
> pin on the development board, and is connected to an external clock source.<br/>
> - ptp_pps_o: Routed through the FPGA to an IO pin on the development board<br/>
> and is connected to a scope.<br/>
> - the trig signal is unused (connected to GND)<br/>
> 3: Updating the device tree:<br/>
><br/>
> gmac1: ethernet@ff702000 {<br/>
> ........<br/>
> clocks = <&emac1_clk &ext_clk_ptp_ref> ;<br/>
> clock-names = "stmmaceth", "clk_ptp_ref";<br/>
> .....<br/>
> }<br/>
><br/>
> Defining my external ptp clock source:<br/>
> ext_clk_ptp_ref: ext_clk_ptp_ref{<br/>
> compatible = "fixed-clock";<br/>
> #clock-cells = <0>;<br/>
> clock-frequency = <25000000>; /* 25.00 MHz */<br/>
> clock-output-names = "ext_clk_ptp_ref";<br/>
> };<br/>
><br/>
> 4: Running a Yocto Krogoth distribution with various version of the linux<br/>
> kernel (4.18, 4.17, 4.9 ltsi-RT, and 4.1.22-ltsi-RT w/wo patches).<br/>
><br/>
> None of these kernel versions work as expected in my system.<br/>
> Kernel versions 4.17 and 4.18 do not seem to work at all, and I have ended<br/>
> up using version 4.1.22.ltsi-RT (real time) kernel with the patches<br/>
> recommended by "Hunter":<br/>
> <<a href="https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f" target="_blank">https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f</a>[<a href="https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f" target="_blank">https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f</a>]><br/>
> <a href="https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f" target="_blank">https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f</a>[<a href="https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f" target="_blank">https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f</a>]<br/>
> ref "Adding LinuxPTP to Arria 10 SoC" email.<br/>
><br/>
> Output when running the "hwstamp_ctl -i eth0 -r 0 -t 1 " command:<br/>
> Device driver does not have support for non-destructive SIOCGHWTSTAMP.<br/>
> new settings:<br/>
> tx_type 1<br/>
> rx_filter 0<br/>
> With the 4.1.22.ltsi-RT kernel and the command above I do get a 1PPS pulse<br/>
> each sec as long as my ext_clk_ptp_ref in the device tree is specified to be<br/>
> 25MHz.<br/>
> However, the actual frequency of this signal can be anything so the PTP<br/>
> engine does not seem to use my ext_clk_ptp_ref.<br/>
><br/>
><br/>
> The "ptp4l -m -q -i eth0 ptp4l" command is not working:<br/>
> ptp4l[193.348]: selected /dev/ptp0 as PTP clock<br/>
> ptp4l[193.388]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE<br/>
> ptp4l[193.389]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE<br/>
> ptp4l[200.843]: port 1: LISTENING to MASTER on<br/>
> ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES<br/>
> ptp4l[200.843]: selected local clock 70b3d5.fffe.761bc5 as best master<br/>
> ptp4l[200.843]: assuming the grand master role<br/>
> ptp4l[201.844]: timed out while polling for tx timestamp<br/>
> ptp4l[201.845]: increasing tx_timestamp_timeout may correct this issue,<br/>
> but it is likely caused by a driver bug<br/>
> ptp4l[201.845]: port 1: send sync failed<br/>
> ptp4l[201.845]: port 1: MASTER to FAULTY on FAULT_DETECTED<br/>
> (FT_UNSPECIFIED)<br/>
><br/>
> I have tried with various clocks sources (external and from the HPS) and<br/>
> longer tx timestamp timeout setting, but without success.<br/>
><br/>
><br/>
><br/>
> Is there anyone who has managed to get this working on a Cyclone V SoC<br/>
> platform and can share some insight into how to connect the PTP signal in<br/>
> Qsys and necessary device tree mappings?<br/>
><br/>
><br/>
> Thanks,<br/>
> AD<br/>
><br/>
><br/>
<br/>
<br/>
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