linuxptp-users

[Linuxptp-users] AR8031 (or other 1 GigE) PHC driver availability

[Dave B. <dav...@gm...>]

Hello,

We have been using LinuxPTP with great success on a system with a
dp83640 PHY and DaVinci MAC running Linux 4.2. We now need to move to
a 1 GigE based system with PHY-based timestamping, but it seems that
no driver exists which supports the PHC of the PHY we're targeting.

The system we're targeting is the TI am335x Starter Kit (TMDSSK3358),
which uses the Qualcomm Atheros ar8031 PHY, and the MAC in the am335x
processor uses the TI CPTS for timestamping.

I found a previous response from Richard on the linuxptp-devel mailing
list (URL: https://sourceforge.net/p/linuxptp/mailman/message/31706496/)
which states "Right now, the dp83640 is only PHY driver in the kernel
with time stamping and PHC supported", but since that was written on
2013-12-02 I am hopeful that there may be more options by now.
However, the mainline ar8031 PHY driver has no PHC support, and I see
no other PHY-based timestamping solutions listed in the Driver Support
Matrix in LinuxPTP's current readme file.

Is there any chance that a driver for the ar8031 with timestamping and
PHC support exists outside of mainline Linux so that we could still
potentially use this platform? Even an in-development driver could be
an option for us.

If not, is this group aware of any alternative 1 GigE PHYs with PHC
Linux driver support of some sort?

Any help or suggestions would be greatly appreciated.
Dave

Re: [Linuxptp-users] AR8031 (or other 1 GigE) PHC driver availability

[Richard C. <ric...@gm...>]

On Tue, Nov 22, 2016 at 09:38:43AM -0800, Dave Berg wrote:
> The system we're targeting is the TI am335x Starter Kit (TMDSSK3358),
> which uses the Qualcomm Atheros ar8031 PHY, and the MAC in the am335x
> processor uses the TI CPTS for timestamping.

Just FYI, we don't have generic support for systems with both a MAC
and a PHY PHC on the same interface.  If and when you get a PHY
driver, then you'll have to patch the MAC driver minimally to disable
CPTS support and pass the ioctls through.
 
> Is there any chance that a driver for the ar8031 with timestamping and
> PHC support exists outside of mainline Linux so that we could still
> potentially use this platform? Even an in-development driver could be
> an option for us.

I am not aware of any.

> If not, is this group aware of any alternative 1 GigE PHYs with PHC
> Linux driver support of some sort?

Yeah, a gigabit PHY with PHC would be great, but unfortunately I have
not seen one yet.  Too bad NatSemi^W TI didn't produce a GB phyter.

Sorry,
Richard

PS  IIRC, there is a technical hurdle to achieve real PHY time stamps
in gigabit devices.  Are you sure the Atheros time stamps in the PHY
and not on the MII bus inputs/outputs?  (Just curious)

Re: [Linuxptp-users] AR8031 (or other 1 GigE) PHC driver availability

[Dave B. <dav...@gm...>]

On Tue, 22 Nov 2016 11:00:12 -0800, Richard Cochran wrote:
> PS  IIRC, there is a technical hurdle to achieve real PHY time stamps
> in gigabit devices.  Are you sure the Atheros time stamps in the PHY
> and not on the MII bus inputs/outputs?  (Just curious)

I'm not sure I'm qualified to answer that question, but I'm including
the relevant figures and text excerpts that I found in the ar8031
datasheet below in case that helps.


Top Level Use of AR8031 in an IEEE 1588v2 system:
     +-----------------+          +-------------+
     |      AR8031     |  RGMII/  |  Controller |
     | +-------------+ |  SGMII   |-----+       |
Line | |1588v2 Module| |<-------->|     |       |
side | |   +-----+   | |          | MAC |       |
<--->| |   | RTC |   | |          |     |       |
     | |   +-----+   | |<-------->|     |       |
     | +-------------+ |   SMI    |-----+       |
     +-----------------+          +-------------+
       A      A      |
       |      |      V
 1588 ref.  Local   PPS
   clock    25MHz
 (optional)


Top Level Diagram of the AR8031's IEEE 1588v2 module:
               +---------------------------+
               |       1588v2 Module       |
  Time of Day  |  +---------------------+  |
<--------------+--|   IEEE 1588 Real    |  |
               |  |     Time Clock      |  |
<--------------+--|                     |  |
      PPS      |  +---------------------+  |
               |             A             |
               |             |             |
               |             V             |
    MDC/MDIO   |  +---------------------+  |
<--------------+->|  IEEE 1588 Control  |  |
               |  +---------------------+  |
               |             A             |
               |             |             |
               |             V             |
               |  +---------------------+  |
  RGMII/SGMII  |  | IEEE 1588 Timestamp |  |
<--------------+->|Unit Packet Detection|  |
               |  |    and Processing   |  |
               |  +---------------------+  |
               +---------------------------+


Block Diagram of the AR8031 1588v2 module:
   Rx      Tx
    A       |  RGMII/SGMII
    |       |<------------->
    |      +++
    |      | | Tx FIFO
    |      +++
    |       |
    |       V
 +----------+-----+
 |  .       |     |        +-------------+
 |  .       '-----+------->|             |
 |  ..............|<-------|             |
 |  miiswitch     |        | IEEE 1588v2 |
 |  ..............|------->|             |
 |  .        .----+<-------|             |
 |  .        |    |        |             |
 +-----------+----+        +-------------+
    A        |
    |        V
 +----------------+
 |                |
 |      PCS       |
 |                |
 +----------------+
    A        |
    |        V
    Rx       Tx

Page 27 excerpt:
"On the transmit side, the PHY will monitor and parse the incoming packet
from the top layer, upon the request of sending IEEE 1588v2 packet, it
will calculate the accurate time of transmission onto the media and a
timestamp accordingly."

Page 28 excerpt:
"On the receive side, the PHY will monitor and parse the incoming packet
from media, and will generate a timestamp upon the reception of IEEE
1588v2 packets. The built-in parser is capable of detecting IEEE 1588v2
on ethernet layer 2 (including untagged, one VLAN tagged and two VLAN
tagged), or layer 3 IPv4/UDP, and IPv6/UDP (including PPPoE and SNAP)."

Thanks for your answers to my questions.
Dave