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From: Richard C. <ric...@gm...> - 2013-08-12 10:39:41
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On Mon, Aug 12, 2013 at 03:19:30AM -0700, David Gravereaux wrote: > On 08/12/2013 02:51 AM, Richard Cochran wrote: > > Does the Netgear also show that the port is asCapable, like in a web > > interface? > > From the web interface it says it isn't capable. The web interface also > says my two Xmos AVB dev boards are also not capable. Okay, then it looks like Netgear has an issue. FWIW, I tested ptp4l together with a LabX Titanium 411 bridge and the XMOS AVB Demo Board, and it works fine with those. Thanks, Richard |
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From: Julien H. <ju...@ya...> - 2013-08-12 10:26:43
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Dear Richard, Thank you very much for your answer ! > Xenomai is great technology, but using it will introduce a *third* > clock into every host: the PHC, the Linux system clock, and the > Xenomai system clock. Probably you will want to directly synchronize > the Xenomai time with the PHC (= development effort). I thought that the CLOCK_REALTIME argument you use with the clock_gettime function in phc2sys was pointing to the nucleus system clock thanks to the XenomaiPosix skin, it's the same clock I use when I poll with the rtdm_clock_read function in my driver to send packets at the right time. > It sounds like you are using Xenomai for real time Ethernet packet > scheduling. An alternative solution would be to use the Intel i210 > PCIe card. It is not expensive, and it has a special feature, namely > real time transmission scheduling (but you would have to write a > driver for this yourself). You can synchronize the i210 using PTP and > then transmit during a globally synchronized time slot. Yes, an Intel engineer informed me about this new chip. But I couldn't find any cheap motherboard proposing several ethernet ports with i210 (I need at least 150 ports at a very low price !). And I don't want to introduce additionnal traffic to the ports I use for data transfer, I would like to reproduce the exact traffic the camera would generate. It's very difficult to find out documentation about AVB, therefore I didn't really understand how it works. > This chain will not work very well. The multi-port nodes (like board 2) > do not have their port clocks synchronized. I guess that using phc2sys > to synchronize them with introduce several hundred nanoseconds time > error per node. For good chaining performance, you really want to have > the PHC clocks synchronized in hardware. Thank you for this information. But it seems to work with the three boards I have (am I mistaken ?). The offsets I get with phc2sys applied to the 2 ports clocks are very low ~ a few tens nanoseconds and it's the same for the ptp clock of board 3 (event better if I increase the pch2sys frequency on board 2). But It probably won't be the same with 50 boards... > You might be able to break your network into ten chains of five, > connected by a 16 port transparent switch, for example. Yes. > Have you looked at the white rabbit project? Yes. White Rabbit is a competitor for the inter-telescopes synchronization in my project. But as I need a low cost architecture for a simulator which will have a short living time, I can't use White Rabbit. > > Could we use a mechanism built on a ethernet hub or switch (regular switch, > > not a IEEE1588 one because too expensive)? We’ll only use these links for > > a synchronization purpose. Can we expect a constant delay with a store and > > forward switch? Or should we use a hub? > You can try a normal switch, but they will introduce variable packet > delays. I have read about using a managed switch with prioritized PTP > queues instead of a PTP switch. However, I expect that you will need > special PTP hardware in order to meet your requirements. In my idea, I would like to use an ethernet HUB (not a switch). As the delay between master and slaves will remain constant, in a first phase I would evaluate it for each port and memorize it. In a second phase, as the communication would only go from the master to the slaves, the master would only send Sync and follow up messages. It would be easy to synchronize the slaves (no other data transmission on the synchronization links) to the master. Do you think it's possible (modifying code doesn't frighten me) ? And I still have the two problems I talked about in my last message : - after a certain amount of time, the offset I get with ptp4l or phc2sys (in a regular use of them with only two boards) increases suddenly to very high values (tipically 69950604426874) - when I start to use phc2sys with a new board (just to synchronize the CLOCK_REATIME to a ptp clock), offsets have an order of several microseconds and suddenly, they decrease (it can happen after hours to days) to a few nanoseconds and remain good even after several reboots... Did you ever faced such problems or is it inherent to the use of Xenomai with ptp ? > HTH, This helps a lot, thank you ! Julien |
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From: David G. <dav...@po...> - 2013-08-12 10:18:59
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On 08/12/2013 02:51 AM, Richard Cochran wrote: > Does the Netgear also show that the port is asCapable, like in a web > interface? From the web interface it says it isn't capable. The web interface also says my two Xmos AVB dev boards are also not capable. > Does ptp4l with slaveOnly=1 synchronize to the Netgear? Nothing synchronizes with it.. ever. -- David Gravereaux <dav...@po...> |
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From: Richard C. <ric...@gm...> - 2013-08-12 09:51:41
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On Mon, Aug 12, 2013 at 02:36:57AM -0700, David Gravereaux wrote: > > I want ptp4l to become master, which is why I have the priority set > lower than 248 and slaveOnly=0. Now if the Netgear can just talk to it > right... more phone calls to them in the AM. It looks like ptp4l thinks the port is asCapable. That means that the P2P mechanism to the Netgear is working (from ptp4l's perspective). Does the Netgear also show that the port is asCapable, like in a web interface? Does ptp4l with slaveOnly=1 synchronize to the Netgear? Thanks, Richard |
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From: David G. <dav...@po...> - 2013-08-12 09:36:20
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On 08/12/2013 02:22 AM, Richard Cochran wrote: > On Mon, Aug 12, 2013 at 01:40:51AM -0700, David Gravereaux wrote: >> On 08/12/2013 12:55 AM, Richard Cochran wrote: >>> >>> I guess wireshark is noticing the missing follow up information TLV. >>> Using the configuration file (or setting option follow_up_info) should >>> cure this. >> >> >> Yes and no. With follow_up_info=0, it attempts to sync. No attempt to >> sync without it. Guess I'll be doing more phone calls to Netgear tomorrow > > But is wireshark happy now? Never gets to a Follow_Up_Message (0x08) so I couldn't say. $ sudo ptp4l -i eth2 -f gPTP.cfg [sudo] password for davygrvy: ptp4l[202911.008]: PI servo: sync interval 1.000 kp 0.700 ki 0.300000 ptp4l[202911.016]: driver changed our HWTSTAMP options ptp4l[202911.016]: tx_type 1 not 1 ptp4l[202911.016]: rx_filter 1 not 12 ptp4l[202911.016]: port 1: INITIALIZING to LISTENING on INITIALIZE ptp4l[202911.016]: port 0: INITIALIZING to LISTENING on INITIALIZE ptp4l[202911.221]: port 1: setting asCapable ptp4l[202911.221]: port 1: peer port id set to 0026f2.fffe.f25aa0-1 <- Netgear 802.1AS clock. ptp4l[202912.016]: port 1: delay timeout ptp4l[202913.016]: port 1: delay timeout ptp4l[202914.016]: port 1: delay timeout ptp4l[202915.016]: port 1: delay timeout ptp4l[202916.016]: port 1: delay timeout ptp4l[202917.016]: port 1: announce timeout ptp4l[202917.016]: port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES ptp4l[202917.016]: selected best master clock a0369f.fffe.1cdd3b ptp4l[202917.016]: assuming the grand master role <- Netgear ignores this election ptp4l[202917.016]: port 1: delay timeout ptp4l[202917.141]: port 1: master sync timeout ptp4l[202917.266]: port 1: master sync timeout ptp4l[202917.391]: port 1: master sync timeout ptp4l[202917.516]: port 1: master sync timeout ptp4l[202917.641]: port 1: master sync timeout ptp4l[202917.766]: port 1: master sync timeout ptp4l[202917.891]: port 1: master sync timeout ptp4l[202918.016]: port 1: delay timeout ptp4l[202918.018]: port 1: master sync timeout ptp4l[202918.143]: port 1: master sync timeout ptp4l[202918.268]: port 1: master sync timeout ptp4l[202918.393]: port 1: master sync timeout ptp4l[202918.518]: port 1: master sync timeout ptp4l[202918.643]: port 1: master sync timeout ptp4l[202918.768]: port 1: master sync timeout ptp4l[202918.893]: port 1: master sync timeout ptp4l[202919.016]: port 1: master tx announce timeout ptp4l[202919.016]: port 1: delay timeout ptp4l[202919.018]: port 1: master sync timeout ptp4l[202919.143]: port 1: master sync timeout ptp4l[202919.268]: port 1: master sync timeout ptp4l[202919.393]: port 1: master sync timeout ptp4l[202919.518]: port 1: master sync timeout ptp4l[202919.643]: port 1: master sync timeout ptp4l[202919.768]: port 1: master sync timeout ptp4l[202919.893]: port 1: master sync timeout ptp4l[202920.017]: port 1: delay timeout ptp4l[202920.019]: port 1: master sync timeout ptp4l[202920.144]: port 1: master sync timeout ptp4l[202920.269]: port 1: master sync timeout ptp4l[202920.394]: port 1: master sync timeout ptp4l[202920.519]: port 1: master sync timeout ptp4l[202920.644]: port 1: master sync timeout ptp4l[202920.769]: port 1: master sync timeout ptp4l[202920.894]: port 1: master sync timeout ptp4l[202921.016]: port 1: master tx announce timeout ptp4l[202921.017]: port 1: delay timeout ptp4l[202921.019]: port 1: master sync timeout ptp4l[202921.144]: port 1: master sync timeout ptp4l[202921.269]: port 1: master sync timeout ptp4l[202921.394]: port 1: master sync timeout ptp4l[202921.519]: port 1: master sync timeout ptp4l[202921.644]: port 1: master sync timeout ptp4l[202921.769]: port 1: master sync timeout ptp4l[202921.894]: port 1: master sync timeout ptp4l[202922.017]: port 1: delay timeout ptp4l[202922.019]: port 1: master sync timeout ptp4l[202922.145]: port 1: master sync timeout ptp4l[202922.270]: port 1: master sync timeout ptp4l[202922.395]: port 1: master sync timeout ptp4l[202922.520]: port 1: master sync timeout ptp4l[202922.645]: port 1: master sync timeout ptp4l[202922.770]: port 1: master sync timeout ptp4l[202922.895]: port 1: master sync timeout ptp4l[202923.016]: port 1: master tx announce timeout ptp4l[202923.017]: port 1: delay timeout ptp4l[202923.020]: port 1: master sync timeout ptp4l[202923.145]: port 1: master sync timeout ptp4l[202923.270]: port 1: master sync timeout ptp4l[202923.395]: port 1: master sync timeout ptp4l[202923.520]: port 1: master sync timeout ptp4l[202923.645]: port 1: master sync timeout ptp4l[202923.770]: port 1: master sync timeout ptp4l[202923.895]: port 1: master sync timeout ptp4l[202924.017]: port 1: delay timeout ptp4l[202924.020]: port 1: master sync timeout ptp4l[202924.146]: port 1: master sync timeout ptp4l[202924.271]: port 1: master sync timeout ptp4l[202924.396]: port 1: master sync timeout ptp4l[202924.521]: port 1: master sync timeout ptp4l[202924.646]: port 1: master sync timeout ptp4l[202924.771]: port 1: master sync timeout ptp4l[202924.896]: port 1: master sync timeout ptp4l[202925.016]: port 1: master tx announce timeout ptp4l[202925.017]: port 1: delay timeout ptp4l[202925.021]: port 1: master sync timeout ptp4l[202925.146]: port 1: master sync timeout ptp4l[202925.271]: port 1: master sync timeout ptp4l[202925.396]: port 1: master sync timeout ptp4l[202925.521]: port 1: master sync timeout ptp4l[202925.646]: port 1: master sync timeout ptp4l[202925.771]: port 1: master sync timeout ptp4l[202925.896]: port 1: master sync timeout ptp4l[202926.017]: port 1: delay timeout ptp4l[202926.021]: port 1: master sync timeout ptp4l[202926.146]: port 1: master sync timeout ptp4l[202926.272]: port 1: master sync timeout ptp4l[202926.397]: port 1: master sync timeout ptp4l[202926.522]: port 1: master sync timeout ptp4l[202926.647]: port 1: master sync timeout ptp4l[202926.772]: port 1: master sync timeout ptp4l[202926.897]: port 1: master sync timeout ptp4l[202927.016]: port 1: master tx announce timeout ptp4l[202927.017]: port 1: delay timeout ptp4l[202927.022]: port 1: master sync timeout ptp4l[202927.147]: port 1: master sync timeout ptp4l[202927.272]: port 1: master sync timeout ptp4l[202927.397]: port 1: master sync timeout ptp4l[202927.522]: port 1: master sync timeout ptp4l[202927.647]: port 1: master sync timeout ptp4l[202927.772]: port 1: master sync timeout ptp4l[202927.897]: port 1: master sync timeout ptp4l[202928.017]: port 1: delay timeout ptp4l[202928.022]: port 1: master sync timeout ptp4l[202928.147]: port 1: master sync timeout ptp4l[202928.273]: port 1: master sync timeout ptp4l[202928.398]: port 1: master sync timeout ptp4l[202928.523]: port 1: master sync timeout ^Cptp4l[202928.647]: caught signal 2 > Can you post the output from ptp4l? > > BTW, > > - If ptp4l is the master, it sends follow ups (plus info). > - If ptp4l is slave, it consumes follow ups (plus info). I want ptp4l to become master, which is why I have the priority set lower than 248 and slaveOnly=0. Now if the Netgear can just talk to it right... more phone calls to them in the AM. Thanks for the assist. -- David Gravereaux <dav...@po...> |
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From: Richard C. <ric...@gm...> - 2013-08-12 09:23:18
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On Mon, Aug 12, 2013 at 01:40:51AM -0700, David Gravereaux wrote: > On 08/12/2013 12:55 AM, Richard Cochran wrote: > > > > I guess wireshark is noticing the missing follow up information TLV. > > Using the configuration file (or setting option follow_up_info) should > > cure this. > > > Yes and no. With follow_up_info=0, it attempts to sync. No attempt to > sync without it. Guess I'll be doing more phone calls to Netgear tomorrow But is wireshark happy now? Can you post the output from ptp4l? BTW, - If ptp4l is the master, it sends follow ups (plus info). - If ptp4l is slave, it consumes follow ups (plus info). Thanks, Richard |
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From: Richard C. <ric...@gm...> - 2013-08-12 09:13:39
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Julien, You have a very interesting and challenging application. You provided lots of detail, and so I won't try to make very specific comments right away. Please find a few general comments, below. On Sun, Aug 11, 2013 at 10:54:56PM +0100, Julien Houles wrote: > Configuration: > Linux 3.5.3 > Intel 82574l with e1000e-2.3.2 drivers > xenomai-2.6.2.1 Xenomai is great technology, but using it will introduce a *third* clock into every host: the PHC, the Linux system clock, and the Xenomai system clock. Probably you will want to directly synchronize the Xenomai time with the PHC (= development effort). It sounds like you are using Xenomai for real time Ethernet packet scheduling. An alternative solution would be to use the Intel i210 PCIe card. It is not expensive, and it has a special feature, namely real time transmission scheduling (but you would have to write a driver for this yourself). You can synchronize the i210 using PTP and then transmit during a globally synchronized time slot. > The first solution we imagine is making a chain. We bought 3 boards and > built the following setup: > - port 5 (p37p1, ptp5) board 1 linked to port 5 (p37p1, ptp5) board 2 > port 5 board 1 is master and port 5 board 2 is slave > - port 4 (p36p1, ptp4) board 2 linked to port 4 (p36p1, ptp4) board 3 > port 4 board 2 is master and port 4 board 3 is slave This chain will not work very well. The multi-port nodes (like board 2) do not have their port clocks synchronized. I guess that using phc2sys to synchronize them with introduce several hundred nanoseconds time error per node. For good chaining performance, you really want to have the PHC clocks synchronized in hardware. > General questions: > What do you think of such a chain ? Do you think the offset between board 1 > and board 50 will be acceptable (~ 1µs) I don't think this is possible without special measures. To quote 802.1AS-2011 (AVB): B.3 End-to-end time-synchronization performance The requirements of this standard and of standards referenced for each medium ensure that any two time-aware systems separated by six or fewer time-aware systems (i.e., seven or fewer hops) will be synchronized to within 1 μs peak-to-peak of each other during steady-state operation (i.e., each time-aware system receives time-synchronization information every sync interval). In AVB, in order to avoid gain peaking, the clocks are left free running, but the phase and frequency offsets are calculated, accumulated, and propagated through the network. You might consider using this method in your system (but it means calculating global time in your application on each node). You might be able to break your network into ten chains of five, connected by a 16 port transparent switch, for example. There have been studies (especially WRT AVB) on using long chains. I haven't really looked at this myself, but I have seen papers on the AVB working group's website. Have you looked at the white rabbit project? > Could we use a mechanism built on a ethernet hub or switch (regular switch, > not a IEEE1588 one because too expensive)? We’ll only use these links for > a synchronization purpose. Can we expect a constant delay with a store and > forward switch? Or should we use a hub? You can try a normal switch, but they will introduce variable packet delays. I have read about using a managed switch with prioritized PTP queues instead of a PTP switch. However, I expect that you will need special PTP hardware in order to meet your requirements. HTH, Richard |
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From: Julien H. <ju...@ya...> - 2013-08-12 09:02:14
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PTP outputs : BOARD 1 : [root@marctaSBC ~]# ptp4l -i p37p1 -m -P ptp4l[22915.242]: selected /dev/ptp5 as PTP clock ptp4l[22915.244]: failed to read out the clock frequency adjustment: Operation not supported ptp4l[22915.249]: port 1: INITIALIZING to LISTENING on INITIALIZE ptp4l[22915.249]: port 0: INITIALIZING to LISTENING on INITIALIZE ptp4l[22921.249]: port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES [root@marctaSBC linuxptp]# ./phc2sys -s p37p1 -O 0 -m phc2sys[23122.777]: phc offset -24005 s0 freq +0 delay 5644 phc2sys[23123.778]: phc offset -21394 s1 freq -34426 delay 5624 phc2sys[23124.778]: phc offset 98 s2 freq -34328 delay 5639 phc2sys[23125.779]: phc offset -8958 s2 freq -43354 delay 5635 phc2sys[23126.779]: phc offset 75 s2 freq -37009 delay 5625 phc2sys[23127.779]: phc offset 1537 s2 freq -35524 delay 5629 phc2sys[23128.780]: phc offset 54 s2 freq -36546 delay 5609 phc2sys[23129.780]: phc offset -4552 s2 freq -41136 delay 5645 phc2sys[23130.780]: phc offset -2171 s2 freq -40121 delay 5660 phc2sys[23131.781]: phc offset 5434 s2 freq -33167 delay 5619 phc2sys[23132.781]: phc offset 1234 s2 freq -35737 delay 5619 phc2sys[23133.781]: phc offset 2024 s2 freq -34577 delay 5609 phc2sys[23134.781]: phc offset -1298 s2 freq -37291 delay 5598 phc2sys[23135.781]: phc offset -5331 s2 freq -41714 delay 5634 phc2sys[23136.782]: phc offset 3452 s2 freq -34530 delay 5594 phc2sys[23137.782]: phc offset -4248 s2 freq -41194 delay 5619 phc2sys[23138.782]: phc offset -54 s2 freq -38275 delay 5644 phc2sys[23139.782]: phc offset 8843 s2 freq -29394 delay 5639 phc2sys[23140.783]: phc offset -7006 s2 freq -42590 delay 5630 phc2sys[23141.783]: phc offset 4072 s2 freq -33614 delay 5855 phc2sys[23142.783]: phc offset -1236 s2 freq -37700 delay 5649 phc2sys[23143.783]: phc offset 2287 s2 freq -34548 delay 5644 phc2sys[23144.784]: phc offset -1243 s2 freq -37392 delay 5629 ...... phc2sys[23739.928]: phc offset 6668 s2 freq -29655 delay 5603 phc2sys[23740.928]: phc offset -3730 s2 freq -38052 delay 5819 phc2sys[23741.928]: phc offset -640 s2 freq -36081 delay 5774 phc2sys[23742.928]: phc offset -9226 s2 freq -44859 delay 5615 phc2sys[23743.929]: phc offset -23 s2 freq -38424 delay 5639 phc2sys[23744.929]: phc offset 3002 s2 freq -35406 delay 5759 phc2sys[23745.929]: phc offset -70368744179916 s2 freq -500000 delay 5815 phc2sys[23746.929]: phc offset -70368743713845 s2 freq -500000 delay 5611 phc2sys[23747.930]: phc offset -70368743252576 s2 freq -500000 delay 5677 phc2sys[23748.930]: phc offset -70368742789004 s2 freq -500000 delay 5602 phc2sys[23749.930]: phc offset -70368742327066 s2 freq -500000 delay 5636 phc2sys[23750.931]: phc offset -70368741860621 s2 freq -500000 delay 5892 BOARD 2 : [root@marctaSBC linuxptp]# ptp4l -i p37p1 -m -P -s ptp4l[174464.513]: selected /dev/ptp5 as PTP clock ptp4l[174464.515]: failed to read out the clock frequency adjustment: Operation not supported ptp4l[174464.521]: port 1: INITIALIZING to LISTENING on INITIALIZE ptp4l[174464.522]: port 0: INITIALIZING to LISTENING on INITIALIZE ptp4l[174472.039]: port 1: new foreign master 002246.fffe.12838c-1 ptp4l[174476.039]: selected best master clock 002246.fffe.12838c ptp4l[174476.039]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE ptp4l[174477.041]: master offset 190119 s0 freq +0 path delay 770 ptp4l[174478.040]: master offset 202039 s1 freq +11920 path delay 770 ptp4l[174479.040]: master offset -4131 s2 freq +7789 path delay 769 ptp4l[174479.040]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[174480.040]: master offset 59 s2 freq +10740 path delay 769 ptp4l[174481.040]: master offset 1342 s2 freq +12040 path delay 767 ptp4l[174482.040]: master offset 1206 s2 freq +12307 path delay 769 ptp4l[174483.040]: master offset 823 s2 freq +12286 path delay 769 ptp4l[174484.040]: master offset 535 s2 freq +12245 path delay 769 ptp4l[174485.040]: master offset 205 s2 freq +12075 path delay 771 ptp4l[174486.040]: master offset 148 s2 freq +12080 path delay 771 ptp4l[174487.040]: master offset 55 s2 freq +12031 path delay 767 ptp4l[174488.040]: master offset -1 s2 freq +11991 path delay 767 ptp4l[174489.042]: master offset -4 s2 freq +11988 path delay 767 ptp4l[174490.040]: master offset -3 s2 freq +11988 path delay 765 ptp4l[174491.041]: master offset -2 s2 freq +11988 path delay 762 ptp4l[174492.041]: master offset 1 s2 freq +11990 path delay 758 ptp4l[174493.041]: master offset 1 s2 freq +11991 path delay 756 ptp4l[174494.041]: master offset 0 s2 freq +11990 path delay 756 ptp4l[174495.041]: master offset -2 s2 freq +11988 path delay 756 ptp4l[174496.041]: master offset -5 s2 freq +11984 path delay 758 ......................... ptp4l[175290.088]: master offset -29 s2 freq +11935 path delay 753 ptp4l[175291.088]: master offset -77 s2 freq +11879 path delay 751 ptp4l[175292.089]: master offset 9 s2 freq +11942 path delay 751 ptp4l[175293.088]: master offset 40 s2 freq +11975 path delay 751 ptp4l[175294.088]: master offset 31 s2 freq +11978 path delay 751 ptp4l[175295.089]: master offset -70368744177643 s2 freq -599999999 path delay 753 ptp4l[175296.088]: master offset -70368145816436 s2 freq -599999999 path delay 4701 ptp4l[175297.088]: master offset -70367546002731 s2 freq -599999999 path delay 8628 ptp4l[175298.088]: master offset -70366946185845 s2 freq -599999999 path delay 12574 ptp4l[175299.088]: master offset -70366346373840 s2 freq -599999999 path delay 16521 ptp4l[175300.090]: master offset -70365746557429 s2 freq -599999999 path delay 20782 ptp4l[175301.089]: master offset -70365146747351 s2 freq -599999999 path delay 24696 ptp4l[175302.089]: master offset -70364546918013 s2 freq -599999999 path delay 28662 [root@marctaSBC linuxptp]# ./phc2sys -s /dev/ptp5 -c /dev/ptp4 -m -O 0 phc2sys[174550.979]: failed to read out the clock frequency adjustment: Operation not supported phc2sys[174551.981]: phc offset 141058 s0 freq +0 delay 10880 phc2sys[174552.981]: phc offset 143298 s1 freq +2238 delay 10808 phc2sys[174553.982]: phc offset -4053 s2 freq -1815 delay 10799 phc2sys[174554.983]: phc offset 49 s2 freq +1072 delay 10800 phc2sys[174555.983]: phc offset 1344 s2 freq +2381 delay 10919 phc2sys[174556.984]: phc offset 1057 s2 freq +2497 delay 10535 phc2sys[174557.985]: phc offset 1176 s2 freq +2934 delay 10839 phc2sys[174558.985]: phc offset 560 s2 freq +2670 delay 10919 phc2sys[174559.986]: phc offset 82 s2 freq +2360 delay 10919 phc2sys[174560.987]: phc offset 109 s2 freq +2412 delay 10919 phc2sys[174561.987]: phc offset -14 s2 freq +2322 delay 10959 phc2sys[174562.988]: phc offset 70 s2 freq +2401 delay 10879 phc2sys[174563.989]: phc offset -29 s2 freq +2323 delay 10799 phc2sys[174564.989]: phc offset -110 s2 freq +2234 delay 10919 phc2sys[174565.989]: phc offset 31 s2 freq +2342 delay 10879 phc2sys[174566.989]: phc offset -171 s2 freq +2149 delay 10415 phc2sys[174567.990]: phc offset 199 s2 freq +2468 delay 10879 phc2sys[174568.990]: phc offset 114 s2 freq +2442 delay 10919 phc2sys[174569.990]: phc offset -13 s2 freq +2350 delay 10879 phc2sys[174570.991]: phc offset -5 s2 freq +2354 delay 10839 phc2sys[174571.991]: phc offset 64 s2 freq +2421 delay 10839 ......................... phc2sys[175291.197]: phc offset 35 s2 freq +2327 delay 10839 phc2sys[175292.197]: phc offset 5 s2 freq +2308 delay 10879 phc2sys[175293.197]: phc offset -2 s2 freq +2302 delay 10959 phc2sys[175294.197]: phc offset -10 s2 freq +2294 delay 10879 phc2sys[175295.198]: phc offset -65055841 s2 freq -65053540 delay 10879 phc2sys[175296.198]: phc offset -599947449 s2 freq -599999999 delay 11630 phc2sys[175297.198]: phc offset -599989526 s2 freq -599999999 delay 17471 phc2sys[175298.199]: phc offset -600004949 s2 freq -599999999 delay 17343 phc2sys[175299.199]: phc offset -600020181 s2 freq -599999999 delay 17471 phc2sys[175300.199]: phc offset -600035608 s2 freq -599999999 delay 17471 phc2sys[175301.199]: phc offset -600051031 s2 freq -599999999 delay 17727 [root@marctaSBC linuxptp]# ptp4l -i p36p1 -m -P ptp4l[174595.636]: selected /dev/ptp4 as PTP clock ptp4l[174595.637]: failed to read out the clock frequency adjustment: Operation not supported ptp4l[174595.644]: port 1: INITIALIZING to LISTENING on INITIALIZE ptp4l[174595.646]: port 0: INITIALIZING to LISTENING on INITIALIZE ptp4l[174601.644]: port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES [root@marctaSBC linuxptp]# ./phc2sys -s p37p1 -O 0 -m phc2sys[174620.093]: phc offset 113271 s0 freq +0 delay 5474 phc2sys[174621.094]: phc offset 113264 s1 freq -38072 delay 5484 phc2sys[174622.094]: phc offset -28 s2 freq -38100 delay 5494 phc2sys[174623.095]: phc offset 40 s2 freq -38040 delay 5484 phc2sys[174624.095]: phc offset -75 s2 freq -38143 delay 5494 phc2sys[174625.095]: phc offset 35 s2 freq -38056 delay 5554 phc2sys[174626.095]: phc offset -20 s2 freq -38100 delay 5464 phc2sys[174627.095]: phc offset 134 s2 freq -37952 delay 5494 phc2sys[174628.096]: phc offset 49 s2 freq -37997 delay 5504 phc2sys[174629.096]: phc offset -113 s2 freq -38144 delay 5504 phc2sys[174630.096]: phc offset -13 s2 freq -38078 delay 5504 phc2sys[174631.096]: phc offset 8 s2 freq -38061 delay 5494 phc2sys[174632.097]: phc offset 0 s2 freq -38067 delay 5545 phc2sys[174633.097]: phc offset 9 s2 freq -38058 delay 5504 phc2sys[174634.097]: phc offset -42 s2 freq -38106 delay 5514 phc2sys[174635.097]: phc offset -89 s2 freq -38166 delay 5474 phc2sys[174636.098]: phc offset 24 s2 freq -38079 delay 5529 phc2sys[174637.098]: phc offset 19 s2 freq -38077 delay 5464 phc2sys[174638.098]: phc offset 47 s2 freq -38044 delay 5494 phc2sys[174639.098]: phc offset 16 s2 freq -38060 delay 5484 phc2sys[174640.098]: phc offset -25 s2 freq -38097 delay 5484 phc2sys[174641.099]: phc offset 80 s2 freq -37999 delay 5564 phc2sys[174642.099]: phc offset -4 s2 freq -38059 delay 5559 phc2sys[174643.099]: phc offset -47 s2 freq -38103 delay 5484 .......................... phc2sys[175291.248]: phc offset 14 s2 freq -38014 delay 5494 phc2sys[175292.248]: phc offset -138 s2 freq -38162 delay 5479 phc2sys[175293.248]: phc offset -14 s2 freq -38079 delay 5534 phc2sys[175294.249]: phc offset 45 s2 freq -38025 delay 5484 phc2sys[175295.249]: phc offset -95729399 s2 freq -500000 delay 5484 phc2sys[175296.249]: phc offset -695151138 s2 freq -500000 delay 5496 phc2sys[175297.249]: phc offset -1294563525 s2 freq -500000 delay 5497 phc2sys[175298.249]: phc offset -1893973598 s2 freq -500000 delay 5466 phc2sys[175299.250]: phc offset -2493408464 s2 freq -500000 delay 5466 phc2sys[175300.250]: phc offset -3092833604 s2 freq -500000 delay 5507 phc2sys[175301.250]: phc offset -3692242108 s2 freq -500000 delay 5511 BOARD 3 : [root@marctaSBC ~]# ptp4l -i p36p1 -m -P -s ptp4l[23024.269]: selected /dev/ptp3 as PTP clock ptp4l[23024.271]: failed to read out the clock frequency adjustment: Operation not supported ptp4l[23024.277]: port 1: INITIALIZING to LISTENING on INITIALIZE ptp4l[23024.277]: port 0: INITIALIZING to LISTENING on INITIALIZE ptp4l[23031.766]: port 1: new foreign master 002246.fffe.1283c7-1 ptp4l[23035.766]: selected best master clock 002246.fffe.1283c7 ptp4l[23035.767]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE ptp4l[23036.768]: master offset 93070 s0 freq +0 path delay 751 ptp4l[23037.769]: master offset 62384 s1 freq -30686 path delay 751 ptp4l[23038.768]: master offset -5272 s2 freq -35958 path delay 754 ptp4l[23038.768]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[23039.768]: master offset -35 s2 freq -32303 path delay 754 ptp4l[23040.769]: master offset 1422 s2 freq -30856 path delay 756 ptp4l[23041.768]: master offset 1486 s2 freq -30366 path delay 757 ptp4l[23042.768]: master offset 1110 s2 freq -30296 path delay 759 ptp4l[23043.768]: master offset 600 s2 freq -30473 path delay 759 ptp4l[23044.768]: master offset 340 s2 freq -30553 path delay 761 ptp4l[23045.769]: master offset 85 s2 freq -30706 path delay 764 ptp4l[23046.768]: master offset -159 s2 freq -30925 path delay 764 ptp4l[23047.768]: master offset 61 s2 freq -30752 path delay 762 ptp4l[23048.768]: master offset 62 s2 freq -30733 path delay 762 ptp4l[23049.768]: master offset 28 s2 freq -30748 path delay 762 ptp4l[23050.768]: master offset 40 s2 freq -30728 path delay 758 ptp4l[23051.768]: master offset 5 s2 freq -30751 path delay 758 ptp4l[23052.768]: master offset -87 s2 freq -30841 path delay 758 ptp4l[23053.769]: master offset -21 s2 freq -30802 path delay 758 ptp4l[23054.768]: master offset -53 s2 freq -30840 path delay 758 ptp4l[23055.768]: master offset 67 s2 freq -30736 path delay 760 ptp4l[23056.769]: master offset 131 s2 freq -30652 path delay 758 ptp4l[23057.768]: master offset -66 s2 freq -30809 path delay 760 ptp4l[23058.768]: master offset -37 s2 freq -30800 path delay 758 ptp4l[23059.768]: master offset -110 s2 freq -30884 path delay 758 ptp4l[23060.768]: master offset -50 s2 freq -30857 path delay 760 ................................. ptp4l[23719.791]: master offset -93 s2 freq -30892 path delay 768 ptp4l[23720.793]: master offset -30 s2 freq -30856 path delay 766 ptp4l[23721.792]: master offset -9 s2 freq -30844 path delay 766 ptp4l[23722.792]: master offset 13 s2 freq -30825 path delay 766 ptp4l[23723.791]: master offset -30626099 s2 freq -30656933 path delay 766 ptp4l[23724.791]: master offset -316853487 s2 freq -326072151 path delay 479 ptp4l[23725.792]: master offset -591085085 s2 freq -599999999 path delay -1810 ptp4l[23726.791]: master offset -591811507 s2 freq -599999999 path delay -1768 ptp4l[23727.792]: master offset -591864410 s2 freq -599999999 path delay -1724 ptp4l[23728.793]: master offset -591917378 s2 freq -599999999 path delay -1679 ptp4l[23729.792]: master offset -591970343 s2 freq -599999999 path delay -1637 ptp4l[23730.792]: master offset -592023184 s2 freq -599999999 path delay -1591 ptp4l[23731.792]: master offset -592076091 s2 freq -599999999 path delay -1543 [root@marctaSBC linuxptp]# ./phc2sys -s p36p1 -O 0 -m phc2sys[23107.224]: phc offset 305036 s0 freq +0 delay 6383 phc2sys[23108.225]: phc offset 305003 s1 freq -48438 delay 6293 phc2sys[23109.225]: phc offset 79 s2 freq -48359 delay 6365 phc2sys[23110.226]: phc offset 216 s2 freq -48198 delay 6323 phc2sys[23111.226]: phc offset 146 s2 freq -48203 delay 6357 phc2sys[23112.226]: phc offset 93 s2 freq -48213 delay 6353 phc2sys[23113.226]: phc offset -26 s2 freq -48304 delay 6293 phc2sys[23114.227]: phc offset -62 s2 freq -48348 delay 6405 phc2sys[23115.227]: phc offset -148 s2 freq -48452 delay 6357 phc2sys[23116.227]: phc offset -114 s2 freq -48463 delay 6293 phc2sys[23117.227]: phc offset -29 s2 freq -48412 delay 6293 phc2sys[23118.227]: phc offset 82 s2 freq -48309 delay 6353 phc2sys[23119.228]: phc offset 167 s2 freq -48200 delay 6356 phc2sys[23120.228]: phc offset 85 s2 freq -48232 delay 6353 phc2sys[23121.228]: phc offset 82 s2 freq -48209 delay 6293 phc2sys[23122.228]: phc offset 25 s2 freq -48242 delay 6353 phc2sys[23123.228]: phc offset -35 s2 freq -48294 delay 6353 phc2sys[23124.229]: phc offset 33 s2 freq -48237 delay 6372 phc2sys[23125.229]: phc offset -88 s2 freq -48348 delay 6357 phc2sys[23126.229]: phc offset -98 s2 freq -48384 delay 6406 phc2sys[23127.229]: phc offset -33 s2 freq -48349 delay 6353 phc2sys[23128.230]: phc offset -18 s2 freq -48343 delay 6292 phc2sys[23129.230]: phc offset 50 s2 freq -48281 delay 6353 phc2sys[23130.230]: phc offset -8 s2 freq -48324 delay 6417 phc2sys[23131.230]: phc offset -26 s2 freq -48344 delay 6537 phc2sys[23132.230]: phc offset 22 s2 freq -48304 delay 6356 phc2sys[23133.231]: phc offset -5 s2 freq -48324 delay 6447 phc2sys[23134.231]: phc offset 21 s2 freq -48300 delay 6413 phc2sys[23135.231]: phc offset 188 s2 freq -48127 delay 6356 phc2sys[23136.231]: phc offset 82 s2 freq -48176 delay 6353 phc2sys[23137.232]: phc offset -88 s2 freq -48322 delay 6293 phc2sys[23138.232]: phc offset -259 s2 freq -48519 delay 6383 phc2sys[23139.232]: phc offset -51 s2 freq -48389 delay 6361 phc2sys[23140.232]: phc offset 169 s2 freq -48184 delay 6353 .............................. phc2sys[23719.363]: phc offset -14 s2 freq -48237 delay 6293 phc2sys[23720.363]: phc offset -95 s2 freq -48322 delay 6342 phc2sys[23721.363]: phc offset 14 s2 freq -48242 delay 6357 phc2sys[23722.363]: phc offset -2 s2 freq -48253 delay 6357 phc2sys[23723.364]: phc offset -11 s2 freq -48263 delay 6293 phc2sys[23724.364]: phc offset -17523658 s2 freq -500000 delay 6293 phc2sys[23725.364]: phc offset -216745503 s2 freq -500000 delay 6296 phc2sys[23726.364]: phc offset -698745647 s2 freq -500000 delay 6360 phc2sys[23727.364]: phc offset -1298102527 s2 freq -500000 delay 6359 phc2sys[23728.365]: phc offset -1897535882 s2 freq -500000 delay 6344 phc2sys[23729.365]: phc offset -2496933568 s2 freq -500000 delay 6420 phc2sys[23730.365]: phc offset -3096290190 s2 freq -500000 delay 6296 phc2sys[23731.365]: phc offset -3695643149 s2 freq -500000 delay 6356 |
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From: David G. <dav...@po...> - 2013-08-12 08:40:19
|
On 08/12/2013 12:55 AM, Richard Cochran wrote: > On Sun, Aug 11, 2013 at 09:34:07PM -0700, David Gravereaux wrote: >> Once I set the 'transportSpecific' option to 1 that matched the packets >> being sent to me from the switch ptp4l tried attempting a sync, > > Can you please try it using the AV configuration file? > > ptp4l -f gPTP.cfg No luck with that. >> but now >> ptp4l spits these malformed packets according to wireshark. And I'm >> back to the switch complaining about 'bad headers' again. > > I guess wireshark is noticing the missing follow up information TLV. > Using the configuration file (or setting option follow_up_info) should > cure this. Yes and no. With follow_up_info=0, it attempts to sync. No attempt to sync without it. Guess I'll be doing more phone calls to Netgear tomorrow -- David Gravereaux <dav...@po...> |
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From: Richard C. <ric...@gm...> - 2013-08-12 07:55:46
|
On Sun, Aug 11, 2013 at 09:34:07PM -0700, David Gravereaux wrote: > Once I set the 'transportSpecific' option to 1 that matched the packets > being sent to me from the switch ptp4l tried attempting a sync, Can you please try it using the AV configuration file? ptp4l -f gPTP.cfg > but now > ptp4l spits these malformed packets according to wireshark. And I'm > back to the switch complaining about 'bad headers' again. I guess wireshark is noticing the missing follow up information TLV. Using the configuration file (or setting option follow_up_info) should cure this. Thanks, Richard |
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From: David G. <dav...@po...> - 2013-08-12 04:33:38
|
Once I set the 'transportSpecific' option to 1 that matched the packets being sent to me from the switch ptp4l tried attempting a sync, but now ptp4l spits these malformed packets according to wireshark. And I'm back to the switch complaining about 'bad headers' again. -- David Gravereaux <dav...@po...> |
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From: David G. <dav...@po...> - 2013-08-12 00:14:58
|
I built and installed 4.3 of igb, but no joy. Here's a few packets, it helps. The switch responds, but it appears that ptp4l doesn't hear it. -- David Gravereaux <dav...@po...> |
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From: David G. <dav...@po...> - 2013-08-11 23:26:32
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On 08/11/2013 03:22 PM, David Gravereaux wrote: > $ lsmod |grep ptp > ptp 18621 1 igb > pps_core 14080 1 ptp $ modinfo igb |grep -e ^version: version: 4.1.2-k Looks like the latest is 4.3 from https://downloadcenter.intel.com/Detail_Desc.aspx?DwnldID=13663 Is there a recommended PPA I should follow? -- David Gravereaux <dav...@po...> |
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From: David G. <dav...@po...> - 2013-08-11 22:21:57
|
Hi, I'm having trouble getting Linuxptp-1.3 to sync with my switch. switch: Netgear GS716Tv2 FW=5.4.1.13 with AVB (GS716TAV-10000S) license comp: Linux Mint 15 with Intel I210 NIC $ lspci |grep I210 02:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03) $ ethtool -T eth2 Time stamping parameters for eth2: Capabilities: hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE) hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE) hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE) PTP Hardware Clock: 0 Hardware Transmit Timestamp Modes: off (HWTSTAMP_TX_OFF) on (HWTSTAMP_TX_ON) Hardware Receive Filter Modes: none (HWTSTAMP_FILTER_NONE) all (HWTSTAMP_FILTER_ALL) $ lsmod |grep ptp ptp 18621 1 igb pps_core 14080 1 ptp =============== $ sudo ptp4l -mP2sl 7 -i eth2 ptp4l[162693.120]: selected /dev/ptp0 as PTP clock ptp4l[162693.121]: PI servo: sync interval 1.000 kp 0.700 ki 0.300000 ptp4l[162693.139]: driver changed our HWTSTAMP options ptp4l[162693.139]: tx_type 1 not 1 ptp4l[162693.139]: rx_filter 1 not 12 ptp4l[162693.139]: port 1: INITIALIZING to LISTENING on INITIALIZE ptp4l[162693.139]: port 0: INITIALIZING to LISTENING on INITIALIZE ptp4l[162693.266]: port 1: setting asCapable ptp4l[162694.139]: port 1: delay timeout ptp4l[162695.139]: port 1: delay timeout ptp4l[162696.139]: port 1: delay timeout ptp4l[162697.139]: port 1: delay timeout ptp4l[162698.140]: port 1: delay timeout ptp4l[162699.139]: port 1: announce timeout ptp4l[162699.153]: driver changed our HWTSTAMP options ptp4l[162699.153]: tx_type 1 not 1 ptp4l[162699.153]: rx_filter 1 not 12 ptp4l[162699.153]: selected best master clock a0369f.fffe.1cdd3b ptp4l[162699.153]: port 1: delay timeout ptp4l[162700.153]: port 1: delay timeout ptp4l[162701.153]: port 1: delay timeout ptp4l[162702.153]: port 1: delay timeout ptp4l[162703.153]: port 1: delay timeout ptp4l[162704.153]: port 1: delay timeout ptp4l[162705.139]: port 1: announce timeout ptp4l[162705.156]: driver changed our HWTSTAMP options ptp4l[162705.156]: tx_type 1 not 1 ptp4l[162705.156]: rx_filter 1 not 12 ptp4l[162705.156]: selected best master clock a0369f.fffe.1cdd3b ptp4l[162705.156]: port 1: delay timeout ^Cptp4l[162705.651]: caught signal 2 The line 'ptp4l[162693.139]: rx_filter 1 not 12' I think means HWTSTAMP_FILTER_PTP_V2_L2_EVENT is not a capability. Wireshark shows the switch responding, but apparently ptp4l isn't hearing it. Help walk me through debugging this. Tnks. -- David Gravereaux <dav...@po...> |
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From: Julien H. <ju...@ya...> - 2013-08-11 21:55:08
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Configuration : Linux 3.5.3 Intel 82574l with e1000e-2.3.2 drivers xenomai-2.6.2.1 Because of this message : « failed to read clock: Invalid argument » I had to modify phc2sys.c : The clock_gettime function return is no longer checked in read_phc() and update_sync_offset() Dear linuxptp users and developers, For the introduction (quite long) look at the end of the message. We have 50 computers (single board computers with 5 ethernet ports) which we would like to synchronize with a precision of less than one microsecond. The first solution we imagine is making a chain. We bought 3 boards and built the following setup : - port 5 (p37p1, ptp5) board 1 linked to port 5 (p37p1, ptp5) board 2 port 5 board 1 is master and port 5 board 2 is slave - port 4 (p36p1, ptp4) board 2 linked to port 4 (p36p1, ptp4) board 3 port 4 board 2 is master and port 4 board 3 is slave We launch : On board 1 : ptp4l -i p37p1 -m -P phc2sys -s p37p1 -O 0 -m On board 2 : ptp4l -i p37p1 -m -P -s phc2sys -s /dev/ptp5 -c /dev/ptp4 -m -O 0 ptp4l -i p36p1 -m -P phc2sys -s p37p1 -O 0 -m On board 3: ptp4l -i p36p1 -m -P -s phc2sys -s p36p1 -O 0 -m The ptp4l seems to work well on the 3 boards, the master offset converges to a few nanoseconds in a short time. First problem : But after a few minutes, the master offset prints very high values (you can have the details at the end of message): ptp4l[175293.088]: master offset 40 s2 freq +11975 path delay 751 ptp4l[175294.088]: master offset 31 s2 freq +11978 path delay 751 ptp4l[175295.089]: master offset -70368744177643 s2 freq -599999999 path delay 753 ptp4l[175296.088]: master offset -70368145816436 s2 freq -599999999 path delay 4701 ptp4l[175297.088]: master offset -70367546002731 s2 freq -599999999 path delay 8628 ptp4l[175298.088]: master offset -70366946185845 s2 freq -599999999 path delay 12574 I’ve got the same behaviour with phc2sys. Have you ever met this problem ? Second Problem : The rtc synchronization didn’t work well at the beginning on all the boards. I had irregular and quite high phc offsets between a ptp clock (master) and the CLOCK_REALTIME (slave): phc2sys[23132.781]: phc offset 1234 s2 freq -35737 delay 5619 phc2sys[23133.781]: phc offset 2024 s2 freq -34577 delay 5609 phc2sys[23134.781]: phc offset -1298 s2 freq -37291 delay 5598 phc2sys[23135.781]: phc offset -5331 s2 freq -41714 delay 5634 phc2sys[23136.782]: phc offset 3452 s2 freq -34530 delay 5594 phc2sys[23137.782]: phc offset -4248 s2 freq -41194 delay 5619 phc2sys[23138.782]: phc offset -54 s2 freq -38275 delay 5644 phc2sys[23139.782]: phc offset 8843 s2 freq -29394 delay 5639 phc2sys[23140.783]: phc offset -7006 s2 freq -42590 delay 5630 But, one day, I didn’t know how it happened, the results were much better (0 to few tens of ns) on one board. A few days after, the results became better on an other one. And they are still good now. Only the last one still has bad results (see at the end of message) (It’s not a problem coming from the boards because I tried on other hardwares and I had the same behaviour). Have you met this kind of issue ? General questions : What do you think of such a chain ? Do you think the offset between board 1 and board 50 will be acceptable (~ 1µs) ? Could we use a mechanism built on a ethernet hub or switch (regular switch, not a IEEE1588 one because too expensive) ? We’ll only use these links for a synchronization purpose. Can we expect a constant delay with a store and forward switch ? Or should we use a hub ? Thank you very much, Julien. Introduction : I'm in charge of the data acquisition for a gamma-ray telescope camera. The camera is made of 300 electronic boards, each one sends data through a 1 Gb ethernet link. These links are gathered in a stack of switches linked to a camera server via two 10 Gb ethernet links. When a board detects and interesting event, a trigger is sent to all the other boards. When a board receives this trigger, it generates a packet containing the data acquired and sends them on its gigabit link. Therefore, we have 300 packets sent exactly (almost) at the same time by the boards for each event. The average trigger rate is 10 kHz but could be much higher locally because of the poissonian distribution of the triggers. The two 10 Gb links are big enoughto evacuate the average flow but we need to bufferize in the switches for higher instantaneous rates. We would like to validate the switch stack and the whole acquisition chain (the boards won't be ready in a short term). That's why we wouldlike to build a simulator of a half camera, at first, providing 150 gigabit ports. The simulator must be as cheap as possible. We imagined a cluster of 50 small motherboads with 5 gigabit ports each (http://www.minipc.de/catalog/il/1637 + daughter board with 4 ports), using 3 ports for data transfer. We managed to reduce the deltaT between the sending of packets on each port to less than 1µs (deltaT between the first packet sent, on port 1 and the last packet sent on port 3) by using Xenomai and a modified Rtnet library and drivers. We modified the drivers in order to reduce the serialization to the descriptors adresses passing to the etnernet controllers. Now, we have to optimize the inter motherboards synchronization. We won't use any interrupt based synch because of a too large jitter on interrupt latency. We would like to synchronize the boards rtc with ptp and use a preset timing scenario common to all the motherboards. Each board would know when to send the next packet. The core dedicated to data sending would poll on the rtc (at least when approaching the next trigger, use of timers) and send the packet when the right date is reached. The other core could be dedicated to ptp synchronization. PTP outputs : BOARD 1 : [root@marctaSBC ~]# ptp4l -i p37p1 -m -P ptp4l[22915.242]: selected /dev/ptp5 as PTP clock ptp4l[22915.244]: failed to read out the clock frequency adjustment: Operation not supported ptp4l[22915.249]: port 1: INITIALIZING to LISTENING on INITIALIZE ptp4l[22915.249]: port 0: INITIALIZING to LISTENING on INITIALIZE ptp4l[22921.249]: port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES [root@marctaSBC linuxptp]# ./phc2sys -s p37p1 -O 0 -m phc2sys[23122.777]: phc offset -24005 s0 freq +0 delay 5644 phc2sys[23123.778]: phc offset -21394 s1 freq -34426 delay 5624 phc2sys[23124.778]: phc offset 98 s2 freq -34328 delay 5639 phc2sys[23125.779]: phc offset -8958 s2 freq -43354 delay 5635 phc2sys[23126.779]: phc offset 75 s2 freq -37009 delay 5625 phc2sys[23127.779]: phc offset 1537 s2 freq -35524 delay 5629 phc2sys[23128.780]: phc offset 54 s2 freq -36546 delay 5609 phc2sys[23129.780]: phc offset -4552 s2 freq -41136 delay 5645 phc2sys[23130.780]: phc offset -2171 s2 freq -40121 delay 5660 phc2sys[23131.781]: phc offset 5434 s2 freq -33167 delay 5619 phc2sys[23132.781]: phc offset 1234 s2 freq -35737 delay 5619 phc2sys[23133.781]: phc offset 2024 s2 freq -34577 delay 5609 phc2sys[23134.781]: phc offset -1298 s2 freq -37291 delay 5598 phc2sys[23135.781]: phc offset -5331 s2 freq -41714 delay 5634 phc2sys[23136.782]: phc offset 3452 s2 freq -34530 delay 5594 phc2sys[23137.782]: phc offset -4248 s2 freq -41194 delay 5619 phc2sys[23138.782]: phc offset -54 s2 freq -38275 delay 5644 phc2sys[23139.782]: phc offset 8843 s2 freq -29394 delay 5639 phc2sys[23140.783]: phc offset -7006 s2 freq -42590 delay 5630 phc2sys[23141.783]: phc offset 4072 s2 freq -33614 delay 5855 phc2sys[23142.783]: phc offset -1236 s2 freq -37700 delay 5649 phc2sys[23143.783]: phc offset 2287 s2 freq -34548 delay 5644 phc2sys[23144.784]: phc offset -1243 s2 freq -37392 delay 5629 ...... phc2sys[23739.928]: phc offset 6668 s2 freq -29655 delay 5603 phc2sys[23740.928]: phc offset -3730 s2 freq -38052 delay 5819 phc2sys[23741.928]: phc offset -640 s2 freq -36081 delay 5774 phc2sys[23742.928]: phc offset -9226 s2 freq -44859 delay 5615 phc2sys[23743.929]: phc offset -23 s2 freq -38424 delay 5639 phc2sys[23744.929]: phc offset 3002 s2 freq -35406 delay 5759 phc2sys[23745.929]: phc offset -70368744179916 s2 freq -500000 delay 5815 phc2sys[23746.929]: phc offset -70368743713845 s2 freq -500000 delay 5611 phc2sys[23747.930]: phc offset -70368743252576 s2 freq -500000 delay 5677 phc2sys[23748.930]: phc offset -70368742789004 s2 freq -500000 delay 5602 phc2sys[23749.930]: phc offset -70368742327066 s2 freq -500000 delay 5636 phc2sys[23750.931]: phc offset -70368741860621 s2 freq -500000 delay 5892 BOARD 2 : [root@marctaSBC linuxptp]# ptp4l -i p37p1 -m -P -s ptp4l[174464.513]: selected /dev/ptp5 as PTP clock ptp4l[174464.515]: failed to read out the clock frequency adjustment: Operation not supported ptp4l[174464.521]: port 1: INITIALIZING to LISTENING on INITIALIZE ptp4l[174464.522]: port 0: INITIALIZING to LISTENING on INITIALIZE ptp4l[174472.039]: port 1: new foreign master 002246.fffe.12838c-1 ptp4l[174476.039]: selected best master clock 002246.fffe.12838c ptp4l[174476.039]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE ptp4l[174477.041]: master offset 190119 s0 freq +0 path delay 770 ptp4l[174478.040]: master offset 202039 s1 freq +11920 path delay 770 ptp4l[174479.040]: master offset -4131 s2 freq +7789 path delay 769 ptp4l[174479.040]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[174480.040]: master offset 59 s2 freq +10740 path delay 769 ptp4l[174481.040]: master offset 1342 s2 freq +12040 path delay 767 ptp4l[174482.040]: master offset 1206 s2 freq +12307 path delay 769 ptp4l[174483.040]: master offset 823 s2 freq +12286 path delay 769 ptp4l[174484.040]: master offset 535 s2 freq +12245 path delay 769 ptp4l[174485.040]: master offset 205 s2 freq +12075 path delay 771 ptp4l[174486.040]: master offset 148 s2 freq +12080 path delay 771 ptp4l[174487.040]: master offset 55 s2 freq +12031 path delay 767 ptp4l[174488.040]: master offset -1 s2 freq +11991 path delay 767 ptp4l[174489.042]: master offset -4 s2 freq +11988 path delay 767 ptp4l[174490.040]: master offset -3 s2 freq +11988 path delay 765 ptp4l[174491.041]: master offset -2 s2 freq +11988 path delay 762 ptp4l[174492.041]: master offset 1 s2 freq +11990 path delay 758 ptp4l[174493.041]: master offset 1 s2 freq +11991 path delay 756 ptp4l[174494.041]: master offset 0 s2 freq +11990 path delay 756 ptp4l[174495.041]: master offset -2 s2 freq +11988 path delay 756 ptp4l[174496.041]: master offset -5 s2 freq +11984 path delay 758 ......................... ptp4l[175290.088]: master offset -29 s2 freq +11935 path delay 753 ptp4l[175291.088]: master offset -77 s2 freq +11879 path delay 751 ptp4l[175292.089]: master offset 9 s2 freq +11942 path delay 751 ptp4l[175293.088]: master offset 40 s2 freq +11975 path delay 751 ptp4l[175294.088]: master offset 31 s2 freq +11978 path delay 751 ptp4l[175295.089]: master offset -70368744177643 s2 freq -599999999 path delay 753 ptp4l[175296.088]: master offset -70368145816436 s2 freq -599999999 path delay 4701 ptp4l[175297.088]: master offset -70367546002731 s2 freq -599999999 path delay 8628 ptp4l[175298.088]: master offset -70366946185845 s2 freq -599999999 path delay 12574 ptp4l[175299.088]: master offset -70366346373840 s2 freq -599999999 path delay 16521 ptp4l[175300.090]: master offset -70365746557429 s2 freq -599999999 path delay 20782 ptp4l[175301.089]: master offset -70365146747351 s2 freq -599999999 path delay 24696 ptp4l[175302.089]: master offset -70364546918013 s2 freq -599999999 path delay 28662 [root@marctaSBC linuxptp]# ./phc2sys -s /dev/ptp5 -c /dev/ptp4 -m -O 0 phc2sys[174550.979]: failed to read out the clock frequency adjustment: Operation not supported phc2sys[174551.981]: phc offset 141058 s0 freq +0 delay 10880 phc2sys[174552.981]: phc offset 143298 s1 freq +2238 delay 10808 phc2sys[174553.982]: phc offset -4053 s2 freq -1815 delay 10799 phc2sys[174554.983]: phc offset 49 s2 freq +1072 delay 10800 phc2sys[174555.983]: phc offset 1344 s2 freq +2381 delay 10919 phc2sys[174556.984]: phc offset 1057 s2 freq +2497 delay 10535 phc2sys[174557.985]: phc offset 1176 s2 freq +2934 delay 10839 phc2sys[174558.985]: phc offset 560 s2 freq +2670 delay 10919 phc2sys[174559.986]: phc offset 82 s2 freq +2360 delay 10919 phc2sys[174560.987]: phc offset 109 s2 freq +2412 delay 10919 phc2sys[174561.987]: phc offset -14 s2 freq +2322 delay 10959 phc2sys[174562.988]: phc offset 70 s2 freq +2401 delay 10879 phc2sys[174563.989]: phc offset -29 s2 freq +2323 delay 10799 phc2sys[174564.989]: phc offset -110 s2 freq +2234 delay 10919 phc2sys[174565.989]: phc offset 31 s2 freq +2342 delay 10879 phc2sys[174566.989]: phc offset -171 s2 freq +2149 delay 10415 phc2sys[174567.990]: phc offset 199 s2 freq +2468 delay 10879 phc2sys[174568.990]: phc offset 114 s2 freq +2442 delay 10919 phc2sys[174569.990]: phc offset -13 s2 freq +2350 delay 10879 phc2sys[174570.991]: phc offset -5 s2 freq +2354 delay 10839 phc2sys[174571.991]: phc offset 64 s2 freq +2421 delay 10839 ......................... phc2sys[175291.197]: phc offset 35 s2 freq +2327 delay 10839 phc2sys[175292.197]: phc offset 5 s2 freq +2308 delay 10879 phc2sys[175293.197]: phc offset -2 s2 freq +2302 delay 10959 phc2sys[175294.197]: phc offset -10 s2 freq +2294 delay 10879 phc2sys[175295.198]: phc offset -65055841 s2 freq -65053540 delay 10879 phc2sys[175296.198]: phc offset -599947449 s2 freq -599999999 delay 11630 phc2sys[175297.198]: phc offset -599989526 s2 freq -599999999 delay 17471 phc2sys[175298.199]: phc offset -600004949 s2 freq -599999999 delay 17343 phc2sys[175299.199]: phc offset -600020181 s2 freq -599999999 delay 17471 phc2sys[175300.199]: phc offset -600035608 s2 freq -599999999 delay 17471 phc2sys[175301.199]: phc offset -600051031 s2 freq -599999999 delay 17727 [root@marctaSBC linuxptp]# ptp4l -i p36p1 -m -P ptp4l[174595.636]: selected /dev/ptp4 as PTP clock ptp4l[174595.637]: failed to read out the clock frequency adjustment: Operation not supported ptp4l[174595.644]: port 1: INITIALIZING to LISTENING on INITIALIZE ptp4l[174595.646]: port 0: INITIALIZING to LISTENING on INITIALIZE ptp4l[174601.644]: port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES [root@marctaSBC linuxptp]# ./phc2sys -s p37p1 -O 0 -m phc2sys[174620.093]: phc offset 113271 s0 freq +0 delay 5474 phc2sys[174621.094]: phc offset 113264 s1 freq -38072 delay 5484 phc2sys[174622.094]: phc offset -28 s2 freq -38100 delay 5494 phc2sys[174623.095]: phc offset 40 s2 freq -38040 delay 5484 phc2sys[174624.095]: phc offset -75 s2 freq -38143 delay 5494 phc2sys[174625.095]: phc offset 35 s2 freq -38056 delay 5554 phc2sys[174626.095]: phc offset -20 s2 freq -38100 delay 5464 phc2sys[174627.095]: phc offset 134 s2 freq -37952 delay 5494 phc2sys[174628.096]: phc offset 49 s2 freq -37997 delay 5504 phc2sys[174629.096]: phc offset -113 s2 freq -38144 delay 5504 phc2sys[174630.096]: phc offset -13 s2 freq -38078 delay 5504 phc2sys[174631.096]: phc offset 8 s2 freq -38061 delay 5494 phc2sys[174632.097]: phc offset 0 s2 freq -38067 delay 5545 phc2sys[174633.097]: phc offset 9 s2 freq -38058 delay 5504 phc2sys[174634.097]: phc offset -42 s2 freq -38106 delay 5514 phc2sys[174635.097]: phc offset -89 s2 freq -38166 delay 5474 phc2sys[174636.098]: phc offset 24 s2 freq -38079 delay 5529 phc2sys[174637.098]: phc offset 19 s2 freq -38077 delay 5464 phc2sys[174638.098]: phc offset 47 s2 freq -38044 delay 5494 phc2sys[174639.098]: phc offset 16 s2 freq -38060 delay 5484 phc2sys[174640.098]: phc offset -25 s2 freq -38097 delay 5484 phc2sys[174641.099]: phc offset 80 s2 freq -37999 delay 5564 phc2sys[174642.099]: phc offset -4 s2 freq -38059 delay 5559 phc2sys[174643.099]: phc offset -47 s2 freq -38103 delay 5484 .......................... phc2sys[175291.248]: phc offset 14 s2 freq -38014 delay 5494 phc2sys[175292.248]: phc offset -138 s2 freq -38162 delay 5479 phc2sys[175293.248]: phc offset -14 s2 freq -38079 delay 5534 phc2sys[175294.249]: phc offset 45 s2 freq -38025 delay 5484 phc2sys[175295.249]: phc offset -95729399 s2 freq -500000 delay 5484 phc2sys[175296.249]: phc offset -695151138 s2 freq -500000 delay 5496 phc2sys[175297.249]: phc offset -1294563525 s2 freq -500000 delay 5497 phc2sys[175298.249]: phc offset -1893973598 s2 freq -500000 delay 5466 phc2sys[175299.250]: phc offset -2493408464 s2 freq -500000 delay 5466 phc2sys[175300.250]: phc offset -3092833604 s2 freq -500000 delay 5507 phc2sys[175301.250]: phc offset -3692242108 s2 freq -500000 delay 5511 BOARD 3 : [root@marctaSBC ~]# ptp4l -i p36p1 -m -P -s ptp4l[23024.269]: selected /dev/ptp3 as PTP clock ptp4l[23024.271]: failed to read out the clock frequency adjustment: Operation not supported ptp4l[23024.277]: port 1: INITIALIZING to LISTENING on INITIALIZE ptp4l[23024.277]: port 0: INITIALIZING to LISTENING on INITIALIZE ptp4l[23031.766]: port 1: new foreign master 002246.fffe.1283c7-1 ptp4l[23035.766]: selected best master clock 002246.fffe.1283c7 ptp4l[23035.767]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE ptp4l[23036.768]: master offset 93070 s0 freq +0 path delay 751 ptp4l[23037.769]: master offset 62384 s1 freq -30686 path delay 751 ptp4l[23038.768]: master offset -5272 s2 freq -35958 path delay 754 ptp4l[23038.768]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[23039.768]: master offset -35 s2 freq -32303 path delay 754 ptp4l[23040.769]: master offset 1422 s2 freq -30856 path delay 756 ptp4l[23041.768]: master offset 1486 s2 freq -30366 path delay 757 ptp4l[23042.768]: master offset 1110 s2 freq -30296 path delay 759 ptp4l[23043.768]: master offset 600 s2 freq -30473 path delay 759 ptp4l[23044.768]: master offset 340 s2 freq -30553 path delay 761 ptp4l[23045.769]: master offset 85 s2 freq -30706 path delay 764 ptp4l[23046.768]: master offset -159 s2 freq -30925 path delay 764 ptp4l[23047.768]: master offset 61 s2 freq -30752 path delay 762 ptp4l[23048.768]: master offset 62 s2 freq -30733 path delay 762 ptp4l[23049.768]: master offset 28 s2 freq -30748 path delay 762 ptp4l[23050.768]: master offset 40 s2 freq -30728 path delay 758 ptp4l[23051.768]: master offset 5 s2 freq -30751 path delay 758 ptp4l[23052.768]: master offset -87 s2 freq -30841 path delay 758 ptp4l[23053.769]: master offset -21 s2 freq -30802 path delay 758 ptp4l[23054.768]: master offset -53 s2 freq -30840 path delay 758 ptp4l[23055.768]: master offset 67 s2 freq -30736 path delay 760 ptp4l[23056.769]: master offset 131 s2 freq -30652 path delay 758 ptp4l[23057.768]: master offset -66 s2 freq -30809 path delay 760 ptp4l[23058.768]: master offset -37 s2 freq -30800 path delay 758 ptp4l[23059.768]: master offset -110 s2 freq -30884 path delay 758 ptp4l[23060.768]: master offset -50 s2 freq -30857 path delay 760 ................................. ptp4l[23719.791]: master offset -93 s2 freq -30892 path delay 768 ptp4l[23720.793]: master offset -30 s2 freq -30856 path delay 766 ptp4l[23721.792]: master offset -9 s2 freq -30844 path delay 766 ptp4l[23722.792]: master offset 13 s2 freq -30825 path delay 766 ptp4l[23723.791]: master offset -30626099 s2 freq -30656933 path delay 766 ptp4l[23724.791]: master offset -316853487 s2 freq -326072151 path delay 479 ptp4l[23725.792]: master offset -591085085 s2 freq -599999999 path delay -1810 ptp4l[23726.791]: master offset -591811507 s2 freq -599999999 path delay -1768 ptp4l[23727.792]: master offset -591864410 s2 freq -599999999 path delay -1724 ptp4l[23728.793]: master offset -591917378 s2 freq -599999999 path delay -1679 ptp4l[23729.792]: master offset -591970343 s2 freq -599999999 path delay -1637 ptp4l[23730.792]: master offset -592023184 s2 freq -599999999 path delay -1591 ptp4l[23731.792]: master offset -592076091 s2 freq -599999999 path delay -1543 [root@marctaSBC linuxptp]# ./phc2sys -s p36p1 -O 0 -m phc2sys[23107.224]: phc offset 305036 s0 freq +0 delay 6383 phc2sys[23108.225]: phc offset 305003 s1 freq -48438 delay 6293 phc2sys[23109.225]: phc offset 79 s2 freq -48359 delay 6365 phc2sys[23110.226]: phc offset 216 s2 freq -48198 delay 6323 phc2sys[23111.226]: phc offset 146 s2 freq -48203 delay 6357 phc2sys[23112.226]: phc offset 93 s2 freq -48213 delay 6353 phc2sys[23113.226]: phc offset -26 s2 freq -48304 delay 6293 phc2sys[23114.227]: phc offset -62 s2 freq -48348 delay 6405 phc2sys[23115.227]: phc offset -148 s2 freq -48452 delay 6357 phc2sys[23116.227]: phc offset -114 s2 freq -48463 delay 6293 phc2sys[23117.227]: phc offset -29 s2 freq -48412 delay 6293 phc2sys[23118.227]: phc offset 82 s2 freq -48309 delay 6353 phc2sys[23119.228]: phc offset 167 s2 freq -48200 delay 6356 phc2sys[23120.228]: phc offset 85 s2 freq -48232 delay 6353 phc2sys[23121.228]: phc offset 82 s2 freq -48209 delay 6293 phc2sys[23122.228]: phc offset 25 s2 freq -48242 delay 6353 phc2sys[23123.228]: phc offset -35 s2 freq -48294 delay 6353 phc2sys[23124.229]: phc offset 33 s2 freq -48237 delay 6372 phc2sys[23125.229]: phc offset -88 s2 freq -48348 delay 6357 phc2sys[23126.229]: phc offset -98 s2 freq -48384 delay 6406 phc2sys[23127.229]: phc offset -33 s2 freq -48349 delay 6353 phc2sys[23128.230]: phc offset -18 s2 freq -48343 delay 6292 phc2sys[23129.230]: phc offset 50 s2 freq -48281 delay 6353 phc2sys[23130.230]: phc offset -8 s2 freq -48324 delay 6417 phc2sys[23131.230]: phc offset -26 s2 freq -48344 delay 6537 phc2sys[23132.230]: phc offset 22 s2 freq -48304 delay 6356 phc2sys[23133.231]: phc offset -5 s2 freq -48324 delay 6447 phc2sys[23134.231]: phc offset 21 s2 freq -48300 delay 6413 phc2sys[23135.231]: phc offset 188 s2 freq -48127 delay 6356 phc2sys[23136.231]: phc offset 82 s2 freq -48176 delay 6353 phc2sys[23137.232]: phc offset -88 s2 freq -48322 delay 6293 phc2sys[23138.232]: phc offset -259 s2 freq -48519 delay 6383 phc2sys[23139.232]: phc offset -51 s2 freq -48389 delay 6361 phc2sys[23140.232]: phc offset 169 s2 freq -48184 delay 6353 .............................. phc2sys[23719.363]: phc offset -14 s2 freq -48237 delay 6293 phc2sys[23720.363]: phc offset -95 s2 freq -48322 delay 6342 phc2sys[23721.363]: phc offset 14 s2 freq -48242 delay 6357 phc2sys[23722.363]: phc offset -2 s2 freq -48253 delay 6357 phc2sys[23723.364]: phc offset -11 s2 freq -48263 delay 6293 phc2sys[23724.364]: phc offset -17523658 s2 freq -500000 delay 6293 phc2sys[23725.364]: phc offset -216745503 s2 freq -500000 delay 6296 phc2sys[23726.364]: phc offset -698745647 s2 freq -500000 delay 6360 phc2sys[23727.364]: phc offset -1298102527 s2 freq -500000 delay 6359 phc2sys[23728.365]: phc offset -1897535882 s2 freq -500000 delay 6344 phc2sys[23729.365]: phc offset -2496933568 s2 freq -500000 delay 6420 phc2sys[23730.365]: phc offset -3096290190 s2 freq -500000 delay 6296 phc2sys[23731.365]: phc offset -3695643149 s2 freq -500000 delay 6356 |
|
From: Richard C. <ric...@gm...> - 2013-08-07 08:16:09
|
On Wed, Aug 07, 2013 at 09:43:45AM +0300, Alex Gavrilov wrote:
>
> I use assembler code like this to read time registers:
>
> .model large
>
> test_data segment "FAR_DATA" public use16
You are running this program under DOS?
If so, why?
> ================================================================================
>
> This is output from software mode:
>
> [root@lab32 linuxptp-1.3]# ./ptp4l -i p16p1 -m -s -2 -S
^^^^^
Why does this interface name look so strange?
> ptp4l[3662.740]: port 1: INITIALIZING to LISTENING on INITIALIZE
> ptp4l[3662.740]: port 0: INITIALIZING to LISTENING on INITIALIZE
> ptp4l[3663.635]: port 1: new foreign master ece555.fffe.2de639-2
> ptp4l[3667.295]: selected best master clock ece555.fffe.2de639
> ptp4l[3667.295]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
> ptp4l[3667.433]: port 1: minimum delay request interval 2^3
> ptp4l[3674.614]: master offset -3600882843951 s0 freq +0 path delay 19917808
Path delay is estimated at 20 milliseconds! Are your packets going
through a router?
> ptp4l[3675.529]: master offset -3600965414318 s0 freq +0 path delay 19917808
> ptp4l[3676.444]: master offset -3601047983089 s0 freq +0 path delay 19917808
> ptp4l[3677.359]: master offset -3601130555972 s0 freq +0 path delay 19917808
> ptp4l[3678.274]: master offset -3601213123527 s0 freq +0 path delay 19917808
> ptp4l[3679.189]: master offset -3601295694079 s0 freq +0 path delay 19917808
> ptp4l[3680.104]: master offset -3601378264480 s0 freq +0 path delay 19917808
> ptp4l[3681.019]: master offset -3601460837143 s0 freq +0 path delay 19917808
> ptp4l[3681.934]: master offset -3601543405035 s0 freq +0 path delay 19917808
> ptp4l[3682.849]: master offset -3601617688457 s0 freq +0 path delay 11630558
> ptp4l[3683.889]: master offset -3601575495165 s0 freq +0 path delay 11630558
> ptp4l[3684.970]: master offset -3601491859633 s0 freq +0 path delay 11630558
> ptp4l[3686.051]: master offset -3601408225417 s0 freq +0 path delay 11630558
> ptp4l[3687.132]: master offset -3601324587614 s0 freq +0 path delay 11630558
> ptp4l[3688.213]: master offset -3601240952059 s0 freq +0 path delay 11630558
> ptp4l[3689.294]: master offset -3601157315298 s0 freq +0 path delay 11630558
> ptp4l[3690.376]: master offset -3601073679242 s0 freq +0 path delay 11630558
> ptp4l[3691.457]: master offset -3600990048190 s1 freq -499999 path delay 11630558
The frequency offset is greater than 500 ppm. What is your system
clock? Can it really be so badly out of tune?
> ptp4l[3692.538]: master offset 83635426 s2 freq +499999 path delay 11630558
> ptp4l[3692.538]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
> ptp4l[3693.618]: master offset 166278466 s2 freq +499999 path delay 11630558
> ptp4l[3694.698]: master offset 248915872 s2 freq +499999 path delay 11630558
> ptp4l[3695.778]: master offset 331556238 s2 freq +499999 path delay 11630558
> ptp4l[3696.858]: master offset 414192925 s2 freq +499999 path delay 11630558
> ptp4l[3697.939]: master offset 496831388 s2 freq +499999 path delay 11630558
> ptp4l[3699.019]: master offset 579467338 s2 freq +499999 path delay 11630558
The offset keeps growing, and the frequency adjustment is maxed
out. This means one (or more) of the following:
- The network delay and jitter are huge.
- The local time stamps are broken (can't think how this could
happen with SW time stamps).
- The remote time stamps are broken (master is broken).
- The local oscillator is unusable.
Are you able to synchronize this system using ntp? radclock? ptpd?
Is this system running as a guest in a virtual machine?
Thanks,
Richard
|
|
From: Richard C. <ric...@gm...> - 2013-08-07 07:50:11
|
On Tue, Aug 06, 2013 at 10:10:19PM +0300, Alex Gavrilov wrote:
>
> > 1. Make sure you are using the latest version (ptp4l -v).
> Yes, i compiled the latest version 1.3, but command "ptp4l -v" say nothing
> (version 1.0 say "1.0") - is this normal?
No, it is not normal. Something is terribly wrong. What happens when
you recompile? Do you see output like this?
gcc -Wall -DVER=1.3 -I/lib/modules/3.7.10-00002-gfc74603/build/usr/include -c -o ptp4l.o ptp4l.c
^^^^^^^^^
What is the output of: ./version.sh ?
gcc -v ?
> > Are you running another program that sends PTP messages at the same
> time as ptp4l?
> Running nothing, and wireshark shows only input packets from switch and
> output packets from 82676, according to work of process ptp4l.
And no other programs are reading the registers of your PCIe card,
bypassing the driver?
> I try to use ptp4l in software mode - he shows big master offset (i set
> difference between current system time and time in switch of one day), and
> this offset does not decrease with time - any clock (realtime, /dev/ptp0)
> not synchronized with time from switch. I try to set little difference -
> but synchronization does not occur.
Looking at the output from your other mail, something in your system
seems to be totally broken. The estimated frequency offset is way too
large. Can it be that your oscillator is so badly off? What
architecture is the machine that are you running?
Thanks,
Richard
|
|
From: Alex G. <al....@gm...> - 2013-08-07 06:43:53
|
> How are you doing this? Some other program running along side? or just
using a register read tool like ethregs, ethtool, or your own custom
one?
I use assembler code like this to read time registers:
.model large
test_data segment "FAR_DATA" public use16
BASE_Ethernet dd 0CE8E0000h
buffer dd 1000 dup (055555555h)
test_data ends
assume ds:test_data
.code
P386
PUBLIC _read
_read proc C far
mov ax, test_data
mov ds, ax
xor ax, ax
mov gs, ax
;precion time
mov EBX, BASE_Ethernet
;read vendor and device id
mov eax, 00
mov edx, dword ptr[GS:EBX+EAX]
mov eax, 10h
mov edx, dword ptr[GS:EBX+EAX]
mov eax, 0B638h
mov edx, dword ptr[GS:EBX+EAX]
mov eax, 0B608h
mov edx, 01000001h
mov dword ptr[GS:EBX+EAX], edx
// System time register low
mov eax, 0B600h
mov edx, dword ptr[GS:EBX+EAX]
// System time register high
mov eax, 0B604h
mov ecx, dword ptr[GS:EBX+EAX]
mov buffer+0, edx
mov buffer+4, ecx
xor ax, ax
mov ah, 86h
mov cx, 00E4h
mov dx, 0E1C0h
int 15h
mov eax, 0B600h
mov edx, dword ptr[GS:EBX+EAX]
mov eax, 0B604h
mov ecx, dword ptr[GS:EBX+EAX]
mov buffer+8, edx
mov buffer+12, ecx
mov ax, 2100h
int 21h
_read endp
================================================================================
This is output from software mode:
[root@lab32 linuxptp-1.3]# ./ptp4l -i p16p1 -m -s -2 -S
ptp4l[3662.740]: port 1: INITIALIZING to LISTENING on INITIALIZE
ptp4l[3662.740]: port 0: INITIALIZING to LISTENING on INITIALIZE
ptp4l[3663.635]: port 1: new foreign master ece555.fffe.2de639-2
ptp4l[3667.295]: selected best master clock ece555.fffe.2de639
ptp4l[3667.295]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l[3667.433]: port 1: minimum delay request interval 2^3
ptp4l[3674.614]: master offset -3600882843951 s0 freq +0 path delay
19917808
ptp4l[3675.529]: master offset -3600965414318 s0 freq +0 path delay
19917808
ptp4l[3676.444]: master offset -3601047983089 s0 freq +0 path delay
19917808
ptp4l[3677.359]: master offset -3601130555972 s0 freq +0 path delay
19917808
ptp4l[3678.274]: master offset -3601213123527 s0 freq +0 path delay
19917808
ptp4l[3679.189]: master offset -3601295694079 s0 freq +0 path delay
19917808
ptp4l[3680.104]: master offset -3601378264480 s0 freq +0 path delay
19917808
ptp4l[3681.019]: master offset -3601460837143 s0 freq +0 path delay
19917808
ptp4l[3681.934]: master offset -3601543405035 s0 freq +0 path delay
19917808
ptp4l[3682.849]: master offset -3601617688457 s0 freq +0 path delay
11630558
ptp4l[3683.889]: master offset -3601575495165 s0 freq +0 path delay
11630558
ptp4l[3684.970]: master offset -3601491859633 s0 freq +0 path delay
11630558
ptp4l[3686.051]: master offset -3601408225417 s0 freq +0 path delay
11630558
ptp4l[3687.132]: master offset -3601324587614 s0 freq +0 path delay
11630558
ptp4l[3688.213]: master offset -3601240952059 s0 freq +0 path delay
11630558
ptp4l[3689.294]: master offset -3601157315298 s0 freq +0 path delay
11630558
ptp4l[3690.376]: master offset -3601073679242 s0 freq +0 path delay
11630558
ptp4l[3691.457]: master offset -3600990048190 s1 freq -499999 path delay
11630558
ptp4l[3692.538]: master offset 83635426 s2 freq +499999 path delay
11630558
ptp4l[3692.538]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
ptp4l[3693.618]: master offset 166278466 s2 freq +499999 path delay
11630558
ptp4l[3694.698]: master offset 248915872 s2 freq +499999 path delay
11630558
ptp4l[3695.778]: master offset 331556238 s2 freq +499999 path delay
11630558
ptp4l[3696.858]: master offset 414192925 s2 freq +499999 path delay
11630558
ptp4l[3697.939]: master offset 496831388 s2 freq +499999 path delay
11630558
ptp4l[3699.019]: master offset 579467338 s2 freq +499999 path delay
11630558
ptp4l[3699.547]: negative path delay -20170126
ptp4l[3699.547]: path_delay = (t2 - t3) + (t4 - t1)
ptp4l[3699.547]: t2 - t3 = -527626340
ptp4l[3699.547]: t4 - t1 = +487286088
ptp4l[3699.547]: c1 0
ptp4l[3699.547]: c2 0
ptp4l[3699.547]: c3 0
ptp4l[3700.099]: master offset 672708283 s2 freq +499999 path delay
1030330
ptp4l[3701.179]: master offset 755347634 s2 freq +499999 path delay
1030330
ptp4l[3702.259]: master offset 837984697 s2 freq +499999 path delay
1030330
ptp4l[3703.339]: master offset 920619941 s2 freq +499999 path delay
1030330
ptp4l[3704.419]: master offset 1003256503 s2 freq +499999 path delay
1030330
ptp4l[3705.499]: master offset 1085896816 s2 freq +499999 path delay
1030330
ptp4l[3706.580]: master offset 1168532970 s2 freq +499999 path delay
1030330
ptp4l[3707.660]: master offset 1251172248 s2 freq +499999 path delay
1030330
ptp4l[3707.780]: negative path delay -4575009
ptp4l[3707.780]: path_delay = (t2 - t3) + (t4 - t1)
ptp4l[3707.780]: t2 - t3 = -119839683
ptp4l[3707.780]: t4 - t1 = +110689664
ptp4l[3707.780]: c1 0
ptp4l[3707.780]: c2 0
ptp4l[3707.780]: c3 0
ptp4l[3708.740]: master offset 1335211571 s2 freq +499999 path delay
-371004
ptp4l[3709.820]: master offset 1417849294 s2 freq +499999 path delay
-371004
ptp4l[3710.900]: master offset 1500486714 s2 freq +499999 path delay
-371004
ptp4l[3711.980]: master offset 1583127615 s2 freq +499999 path delay
-371004
ptp4l[3712.437]: negative path delay -17447934
ptp4l[3712.437]: path_delay = (t2 - t3) + (t4 - t1)
ptp4l[3712.437]: t2 - t3 = -456377356
ptp4l[3712.437]: t4 - t1 = +421481488
ptp4l[3712.437]: c1 0
ptp4l[3712.437]: c2 0
ptp4l[3712.437]: c3 0
ptp4l[3713.060]: master offset 1669178480 s2 freq +499999 path delay
-3786390
ptp4l[3714.141]: master offset 1751818940 s2 freq +499999 path delay
-3786390
ptp4l[3715.221]: master offset 1834452210 s2 freq +499999 path delay
-3786390
ptp4l[3716.301]: master offset 1917090475 s2 freq +499999 path delay
-3786390
..................
ptp4l[3748.588]: master offset 4291761715 s2 freq +499999 path delay
-16421545
ptp4l[3749.502]: master offset 4208194235 s2 freq +499999 path delay
-16421545
ptp4l[3750.416]: master offset 4124624400 s2 freq +499999 path delay
-16421545
ptp4l[3751.330]: master offset 4041058127 s2 freq +499999 path delay
-16421545
ptp4l[3752.244]: master offset 3957487906 s2 freq +499999 path delay
-16421545
ptp4l[3753.158]: master offset 3871178456 s2 freq +499999 path delay
-13679959
ptp4l[3754.072]: master offset 3787610419 s2 freq +499999 path delay
-13679959
ptp4l[3754.986]: master offset 3704042098 s2 freq +499999 path delay
-13679959
ptp4l[3755.899]: master offset 3620471338 s2 freq +499999 path delay
-13679959
ptp4l[3756.813]: master offset 3536907176 s2 freq +499999 path delay
-13679959
ptp4l[3757.727]: master offset 3453337347 s2 freq +499999 path delay
-13679959
ptp4l[3758.641]: master offset 3369769030 s2 freq +499999 path delay
-13679959
ptp4l[3759.555]: master offset 3286198208 s2 freq +499999 path delay
-13679959
ptp4l[3760.469]: master offset 3202632841 s2 freq +499999 path delay
-13679959
ptp4l[3761.383]: master offset 3119062093 s2 freq +499999 path delay
-13679959
ptp4l[3762.297]: master offset 3037484098 s2 freq +499999 path delay
-15669616
ptp4l[3763.211]: master offset 2953914687 s2 freq +499999 path delay
-15669616
ptp4l[3764.125]: master offset 2870344300 s2 freq +499999 path delay
-15669616
ptp4l[3765.039]: master offset 2786777817 s2 freq +499999 path delay
-15669616
ptp4l[3765.953]: master offset 2703207832 s2 freq +499999 path delay
-15669616
// Now i set the system time 3 minutes later
ptp4l[3766.867]: master offset -184373487503 s2 freq -499999 path delay
-15669616
ptp4l[3767.782]: master offset -244904123137 s2 freq -499999 path delay
-15669616
ptp4l[3768.697]: master offset -244986692808 s2 freq -499999 path delay
-15669616
ptp4l[3769.611]: master offset -245069524049 s2 freq -499999 path delay
-15409219
ptp4l[3770.526]: master offset -245152095532 s2 freq -499999 path delay
-15409219
ptp4l[3771.441]: master offset -245234667781 s2 freq -499999 path delay
-15409219
ptp4l[3772.356]: master offset -245317238846 s2 freq -499999 path delay
-15409219
ptp4l[3773.271]: master offset -245399809517 s2 freq -499999 path delay
-15409219
ptp4l[3774.186]: master offset -245482380317 s2 freq -499999 path delay
-15409219
ptp4l[3775.101]: master offset -245564950736 s2 freq -499999 path delay
-15409219
ptp4l[3776.016]: master offset -245651797025 s2 freq -499999 path delay
-11138069
ptp4l[3776.931]: master offset -245734364095 s2 freq -499999 path delay
-11138069
ptp4l[3777.846]: master offset -245816936362 s2 freq -499999 path delay
-11138069
ptp4l[3778.761]: master offset -245899506317 s2 freq -499999 path delay
-11138069
ptp4l[3779.676]: master offset -245982076996 s2 freq -499999 path delay
-11138069
ptp4l[3780.591]: master offset -246064649662 s2 freq -499999 path delay
-11138069
ptp4l[3781.506]: master offset -246147219442 s2 freq -499999 path delay
-11138069
ptp4l[3782.421]: master offset -246229789738 s2 freq -499999 path delay
-11138069
ptp4l[3783.335]: master offset -246312361277 s2 freq -499999 path delay
-11138069
ptp4l[3784.250]: master offset -246394935192 s2 freq -499999 path delay
-11138069
ptp4l[3785.165]: master offset -246477503182 s2 freq -499999 path delay
-11138069
ptp4l[3786.080]: master offset -246560075063 s2 freq -499999 path delay
-11138069
ptp4l[3786.995]: master offset -246642643873 s2 freq -499999 path delay
-11138069
ptp4l[3787.910]: master offset -246726552120 s2 freq -499999 path delay
-9801273
ptp4l[3788.825]: master offset -246809116029 s2 freq -499999 path delay
-9801273
ptp4l[3789.740]: master offset -246891694912 s2 freq -499999 path delay
-9801273
ptp4l[3790.655]: master offset -246974266288 s2 freq -499999 path delay
-9801273
ptp4l[3791.570]: master offset -247056836091 s2 freq -499999 path delay
-9801273
ptp4l[3792.485]: master offset -247139407748 s2 freq -499999 path delay
-9801273
ptp4l[3793.400]: master offset -247221976743 s2 freq -499999 path delay
-9801273
ptp4l[3794.315]: master offset -247304547766 s2 freq -499999 path delay
-9801273
ptp4l[3795.230]: master offset -247387119374 s2 freq -499999 path delay
-9801273
ptp4l[3796.145]: master offset -247469691472 s2 freq -499999 path delay
-9801273
ptp4l[3797.060]: master offset -247552261826 s2 freq -499999 path delay
-9801273
ptp4l[3797.974]: master offset -247634828784 s2 freq -499999 path delay
-9801273
ptp4l[3798.889]: master offset -247717403809 s2 freq -499999 path delay
-9801273
ptp4l[3799.804]: master offset -247803975548 s2 freq -499999 path delay
-5799605
ptp4l[3800.719]: master offset -247886547571 s2 freq -499999 path delay
-5799605
ptp4l[3801.634]: master offset -247972786822 s2 freq -499999 path delay
-2131630
ptp4l[3802.549]: master offset -248055356849 s2 freq -499999 path delay
-2131630
ptp4l[3803.464]: master offset -248137926479 s2 freq -499999 path delay
-2131630
ptp4l[3804.379]: master offset -248220500692 s2 freq -499999 path delay
-2131630
ptp4l[3805.294]: master offset -248303066839 s2 freq -499999 path delay
-2131630
ptp4l[3806.209]: master offset -248385640426 s2 freq -499999 path delay
-2131630
ptp4l[3807.124]: master offset -248468210352 s2 freq -499999 path delay
-2131630
ptp4l[3808.039]: master offset -248550776956 s2 freq -499999 path delay
-2131630
ptp4l[3808.954]: master offset -248633349754 s2 freq -499999 path delay
-2131630
ptp4l[3809.869]: master offset -248715922523 s2 freq -499999 path delay
-2131630
ptp4l[3810.783]: master offset -248798492430 s2 freq -499999 path delay
-2131630
ptp4l[3811.698]: master offset -248881065214 s2 freq -499999 path delay
-2131630
ptp4l[3812.613]: master offset -248963638033 s2 freq -499999 path delay
-2131630
ptp4l[3813.529]: master offset -249046207387 s2 freq -499999 path delay
-2131630
ptp4l[3814.443]: master offset -249128775858 s2 freq -499999 path delay
-2131630
ptp4l[3815.358]: master offset -249216564776 s2 freq -499999 path delay
3084008
ptp4l[3816.273]: master offset -249305384629 s2 freq -499999 path delay
9329309
ptp4l[3817.188]: master offset -249387951398 s2 freq -499999 path delay
9329309
ptp4l[3818.103]: master offset -249470515958 s2 freq -499999 path delay
9329309
ptp4l[3819.018]: master offset -249553090712 s2 freq -499999 path delay
9329309
ptp4l[3819.933]: master offset -249635661793 s2 freq -499999 path delay
9329309
ptp4l[3820.848]: master offset -249718235879 s2 freq -499999 path delay
9329309
ptp4l[3821.763]: master offset -249804313381 s2 freq -499999 path delay
12839243
ptp4l[3822.678]: master offset -249886885945 s2 freq -499999 path delay
12839243
ptp4l[3823.593]: master offset -249969454960 s2 freq -499999 path delay
12839243
ptp4l[3824.508]: master offset -250052027757 s2 freq -499999 path delay
12839243
ptp4l[3825.422]: master offset -250134594992 s2 freq -499999 path delay
12839243
ptp4l[3826.337]: master offset -250217170036 s2 freq -499999 path delay
12839243
ptp4l[3827.252]: master offset -250299737141 s2 freq -499999 path delay
12839243
ptp4l[3828.167]: master offset -250382311667 s2 freq -499999 path delay
12839243
ptp4l[3829.082]: master offset -250464879632 s2 freq -499999 path delay
12839243
ptp4l[3829.997]: master offset -250549709940 s2 freq -499999 path delay
15094493
ptp4l[3830.912]: master offset -250632276312 s2 freq -499999 path delay
15094493
ptp4l[3831.827]: master offset -250714849892 s2 freq -499999 path delay
15094493
ptp4l[3832.742]: master offset -250797421715 s2 freq -499999 path delay
15094493
ptp4l[3833.657]: master offset -250879992478 s2 freq -499999 path delay
15094493
ptp4l[3834.572]: master offset -250962561110 s2 freq -499999 path delay
15094493
ptp4l[3835.487]: master offset -251045133506 s2 freq -499999 path delay
15094493
ptp4l[3836.402]: master offset -251127704238 s2 freq -499999 path delay
15094493
ptp4l[3837.317]: master offset -251210276836 s2 freq -499999 path delay
15094493
ptp4l[3838.232]: master offset -251292839652 s2 freq -499999 path delay
15094493
ptp4l[3839.147]: master offset -251377298486 s2 freq -499999 path delay
16974996
ptp4l[3840.061]: master offset -251459869458 s2 freq -499999 path delay
16974996
ptp4l[3840.976]: master offset -251542443888 s2 freq -499999 path delay
16974996
ptp4l[3841.891]: master offset -251623961572 s2 freq -499999 path delay
15924128
ptp4l[3842.806]: master offset -251706532240 s2 freq -499999 path delay
15924128
..................
Sincerely, Alexander.
|
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From: Alex G. <al....@gm...> - 2013-08-06 19:10:25
|
> It still appears to be running version 1.0 Yes, it was one of the first experiments, on version 1. I am currently using version 1.3, but there is no improvement. > 1. Make sure you are using the latest version (ptp4l -v). Yes, i compiled the latest version 1.3, but command "ptp4l -v" say nothing (version 1.0 say "1.0") - is this normal? > 2. Set tx_timestamp_timeout to 1000. Set, no changes. > 3. Set fault_reset_interval to ASAP. Set, faster recovering after errors. > 4. If the above steps do not yield reasonable results, then recompile the driver, changing IGB_PTP_TX_TIMEOUT from (HZ * 15) to (HZ). Ok, i try this tomorrow. > Are you running another program that sends PTP messages at the same time as ptp4l? Running nothing, and wireshark shows only input packets from switch and output packets from 82676, according to work of process ptp4l. I subscribed to E1000-devel mailing list, but still not received confirmation letter... I try to use ptp4l in software mode - he shows big master offset (i set difference between current system time and time in switch of one day), and this offset does not decrease with time - any clock (realtime, /dev/ptp0) not synchronized with time from switch. I try to set little difference - but synchronization does not occur. Also i found "Ptpd" project (worked only in software mode) - but i can not get it to work (may be, i need to exactly select the parameters of its command-line). Richard and Jake, thank you. Sincerely, Alexander. |
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From: Keller, J. E <jac...@in...> - 2013-08-06 17:12:33
|
On Mon, 2013-08-05 at 10:30 +0300, Гаврилов Александр wrote: > Hello! > > And more thing: > on my card 82676 i can read time registers directly in DOS - it work > fine. But in linux this causes an error "tx timestamp timeout". > > Sincerely, Alexander. How are you doing this? Some other program running along side? or just using a register read tool like ethregs, ethtool, or your own custom one? You should not interfere with registers of a device while it is in operation. Especially not the 1588 registers. The Tx time stamp registers read-once to unlatch. After they are read, the flag which indicates that there is a time stamp available for the driver is cleared and the hardware is free to take a new time stamp. Effectively you trying to read directly from the registers interferes with how the driver has to behave to function correctly!!! Please explain what you are trying to do and why. Maybe we can find a better way to do what you want. I am almost certain this is why you are having a problem.... Thanks, Jake |
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From: Keller, J. E <jac...@in...> - 2013-08-06 17:07:20
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I agree with Richard's suggestions. Could you also obtain a dmesg log as well to go along with this when you re-test using those changes. Thanks, Jake On Tue, 2013-08-06 at 09:43 +0200, Richard Cochran wrote: > On Mon, Aug 05, 2013 at 09:56:23AM +0300, Гаврилов Александр wrote: > > Hello! > > > > Here is an example of the log where synchronization occured: > > This is interesting... > > > ptp4l -2 -i p16p1 -m -H -s > > ptp4l[17534.938]: selected /dev/ptp0 as PTP clock > > ptp4l[17534.957]: port 1: INITIALIZING to LISTENING on INITIALIZE > > ptp4l[17534.957]: port 0: INITIALIZING to LISTENING on INITIALIZE > > ptp4l[17536.761]: port 1: new foreign master ece555.fffe.2de639-2 > > ptp4l[17540.751]: selected best master clock ece555.fffe.2de639 > > ptp4l[17540.751]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE > > ptp4l[17542.696]: port 1: minimum delay request interval 2^3 > > The average delay request interval is eight seconds. > > > ptp4l[17542.746]: master offset 50001478246023551 s0 adj +0 path delay 1276 > > ptp4l[17543.744]: master offset 50001478246021573 s0 adj +0 path delay 974 > > ptp4l[17544.741]: master offset 50001478246019277 s0 adj +0 path delay 974 > > ptp4l[17545.739]: master offset 50001478246016997 s1 adj +0 path delay 974 > > ptp4l[17546.736]: master offset -5048 s2 adj -5048 path delay 974 > > ptp4l[17546.736]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED > > ptp4l[17547.734]: master offset -2323 s2 adj -3837 path delay 974 > > ptp4l[17548.732]: master offset -789 s2 adj -3000 path delay 974 > > ptp4l[17549.729]: master offset -95 s2 adj -2543 path delay 974 > > ptp4l[17550.726]: master offset 123 s2 adj -2354 path delay 974 > > ptp4l[17551.724]: master offset 110 s2 adj -2330 path delay 974 > > ptp4l[17552.721]: master offset 106 s2 adj -2301 path delay 974 > > ptp4l[17553.719]: master offset 109 s2 adj -2266 path delay 974 > > ptp4l[17554.716]: master offset 104 s2 adj -2238 path delay 974 > > ptp4l[17555.714]: master offset -27 s2 adj -2338 path delay 974 > > ptp4l[17556.711]: master offset -48 s2 adj -2367 path delay 974 > > ptp4l[17557.709]: master offset -53 s2 adj -2386 path delay 974 > > ptp4l[17558.706]: master offset 45 s2 adj -2304 path delay 974 > > Looking at the last column (moving average of the path delay), you > have two successful path delay measurements ... > > > ptp4l[17559.704]: master offset 275 s2 adj -2061 path delay 716 > > ... now three ... > > > ptp4l[17560.701]: master offset 9 s2 adj -2244 path delay 716 > > ptp4l[17561.699]: master offset -131 s2 adj -2382 path delay 716 > > ptp4l[17562.696]: master offset -176 s2 adj -2466 path delay 716 > > ptp4l[17563.694]: master offset -102 s2 adj -2445 path delay 716 > > ptp4l[17564.691]: master offset -28 s2 adj -2401 path delay 716 > > ptp4l[17565.689]: master offset 47 s2 adj -2335 path delay 716 > > ptp4l[17566.686]: master offset 2 s2 adj -2366 path delay 716 > > ptp4l[17567.684]: master offset -27 s2 adj -2394 path delay 716 > > ptp4l[17568.681]: master offset 40 s2 adj -2335 path delay 716 > > ptp4l[17569.679]: master offset -13 s2 adj -2376 path delay 716 > > ptp4l[17570.676]: master offset 69 s2 adj -2298 path delay 589 > > ... and now four ... > > > ptp4l[17571.674]: master offset 9 s2 adj -2337 path delay 589 > > ptp4l[17572.671]: master offset -52 s2 adj -2396 path delay 589 > > ptp4l[17572.955]: recvmsg tx timestamp failed: Resource temporarily unavailable > > ptp4l[17572.955]: port 1: send delay request failed > > ... and the fifth one fails. > > > ptp4l[17572.955]: port 1: SLAVE to FAULTY on FAULT_DETECTED > > ptp4l[17591.068]: port 1: FAULTY to LISTENING on FAULT_CLEARED > > ptp4l[17592.622]: port 1: new foreign master ece555.fffe.2de639-2 > > ptp4l[17596.612]: selected best master clock ece555.fffe.2de639 > > ptp4l[17596.612]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE > > ptp4l[17597.609]: master offset 1492 s2 adj -867 path delay 589 > > ptp4l[17597.609]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED > > ptp4l[17597.654]: recvmsg tx timestamp failed: Resource temporarily unavailable > > ptp4l[17597.654]: port 1: send delay request failed > > ptp4l[17597.654]: port 1: SLAVE to FAULTY on FAULT_DETECTED > > In order to get the best out of the 82576, I recommend: > > 1. Make sure you are using the latest version (ptp4l -v). > > 2. Set tx_timestamp_timeout to 1000. > > 3. Set fault_reset_interval to ASAP. > > 4. If the above steps do not yield reasonable results, then recompile > the driver, changing IGB_PTP_TX_TIMEOUT from (HZ * 15) to (HZ). > > It appears that the hardware is sometimes missing or dropping the Tx > time stamp on the delay request messages. Changing IGB_PTP_TX_TIMEOUT > will clear the driver's Tx time stamp timer more often. This might > make the card more responsive in the presence of time stamp loss. > > Good luck, > Richard > |
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From: Ledda W. E. <Wil...@it...> - 2013-08-06 12:14:28
|
Thanks Richard. I can therefore conclude that if I have support for PHC means that the interface supports time stamping hardware (on MAC or PHY)? Sorry if I insist on this, maybe the question is stupid, but I cannot have doubts about. Thanks a lot. William -----Original Message----- From: Richard Cochran [mailto:ric...@gm...] Sent: 06 August 2013 09:18 To: Ledda William EXT Cc: lin...@li... Subject: Re: [Linuxptp-users] Clarification about Driver Compatibility Matrix On Mon, Aug 05, 2013 at 04:32:14PM +0000, Ledda William EXT wrote: > Sorry Richard, but I'm stiil a bit confused about the meaning of the > PHY column. Let me make an example, I have a i350 that has the igb > driver. I read from the table the following table: > > Driver Hardware SOTS PHC PHY VER > igb Intel 82576, 82580 RAW Y NA 3.5 > > In this case, this means that I have a PTP-capable PHY attached to PTP-capable MAC? The PHY column reads "NA" meaning "Not Applicable." Even if you attach a PTP capable PHY (like the National Semiconductor PHYTER) to your i350 MAC, still you will never get any time stamps from the PHY, as the MAC driver will intercept the SIOCSHWTSTAMP ioctl. HTH, Richard |
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From: Richard C. <ric...@gm...> - 2013-08-06 07:45:58
|
On Mon, Aug 05, 2013 at 10:30:22AM +0300, Гаврилов Александр wrote: > Hello! > > And more thing: > on my card 82676 i can read time registers directly in DOS - it work > fine. But in linux this causes an error "tx timestamp timeout". Are you running another program that sends PTP messages at the same time as ptp4l? If so, then this would explain the missing Tx time stamps. Thanks, Richard |
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From: Richard C. <ric...@gm...> - 2013-08-06 07:43:57
|
On Mon, Aug 05, 2013 at 09:56:23AM +0300, Гаврилов Александр wrote: > Hello! > > Here is an example of the log where synchronization occured: This is interesting... > ptp4l -2 -i p16p1 -m -H -s > ptp4l[17534.938]: selected /dev/ptp0 as PTP clock > ptp4l[17534.957]: port 1: INITIALIZING to LISTENING on INITIALIZE > ptp4l[17534.957]: port 0: INITIALIZING to LISTENING on INITIALIZE > ptp4l[17536.761]: port 1: new foreign master ece555.fffe.2de639-2 > ptp4l[17540.751]: selected best master clock ece555.fffe.2de639 > ptp4l[17540.751]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE > ptp4l[17542.696]: port 1: minimum delay request interval 2^3 The average delay request interval is eight seconds. > ptp4l[17542.746]: master offset 50001478246023551 s0 adj +0 path delay 1276 > ptp4l[17543.744]: master offset 50001478246021573 s0 adj +0 path delay 974 > ptp4l[17544.741]: master offset 50001478246019277 s0 adj +0 path delay 974 > ptp4l[17545.739]: master offset 50001478246016997 s1 adj +0 path delay 974 > ptp4l[17546.736]: master offset -5048 s2 adj -5048 path delay 974 > ptp4l[17546.736]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED > ptp4l[17547.734]: master offset -2323 s2 adj -3837 path delay 974 > ptp4l[17548.732]: master offset -789 s2 adj -3000 path delay 974 > ptp4l[17549.729]: master offset -95 s2 adj -2543 path delay 974 > ptp4l[17550.726]: master offset 123 s2 adj -2354 path delay 974 > ptp4l[17551.724]: master offset 110 s2 adj -2330 path delay 974 > ptp4l[17552.721]: master offset 106 s2 adj -2301 path delay 974 > ptp4l[17553.719]: master offset 109 s2 adj -2266 path delay 974 > ptp4l[17554.716]: master offset 104 s2 adj -2238 path delay 974 > ptp4l[17555.714]: master offset -27 s2 adj -2338 path delay 974 > ptp4l[17556.711]: master offset -48 s2 adj -2367 path delay 974 > ptp4l[17557.709]: master offset -53 s2 adj -2386 path delay 974 > ptp4l[17558.706]: master offset 45 s2 adj -2304 path delay 974 Looking at the last column (moving average of the path delay), you have two successful path delay measurements ... > ptp4l[17559.704]: master offset 275 s2 adj -2061 path delay 716 ... now three ... > ptp4l[17560.701]: master offset 9 s2 adj -2244 path delay 716 > ptp4l[17561.699]: master offset -131 s2 adj -2382 path delay 716 > ptp4l[17562.696]: master offset -176 s2 adj -2466 path delay 716 > ptp4l[17563.694]: master offset -102 s2 adj -2445 path delay 716 > ptp4l[17564.691]: master offset -28 s2 adj -2401 path delay 716 > ptp4l[17565.689]: master offset 47 s2 adj -2335 path delay 716 > ptp4l[17566.686]: master offset 2 s2 adj -2366 path delay 716 > ptp4l[17567.684]: master offset -27 s2 adj -2394 path delay 716 > ptp4l[17568.681]: master offset 40 s2 adj -2335 path delay 716 > ptp4l[17569.679]: master offset -13 s2 adj -2376 path delay 716 > ptp4l[17570.676]: master offset 69 s2 adj -2298 path delay 589 ... and now four ... > ptp4l[17571.674]: master offset 9 s2 adj -2337 path delay 589 > ptp4l[17572.671]: master offset -52 s2 adj -2396 path delay 589 > ptp4l[17572.955]: recvmsg tx timestamp failed: Resource temporarily unavailable > ptp4l[17572.955]: port 1: send delay request failed ... and the fifth one fails. > ptp4l[17572.955]: port 1: SLAVE to FAULTY on FAULT_DETECTED > ptp4l[17591.068]: port 1: FAULTY to LISTENING on FAULT_CLEARED > ptp4l[17592.622]: port 1: new foreign master ece555.fffe.2de639-2 > ptp4l[17596.612]: selected best master clock ece555.fffe.2de639 > ptp4l[17596.612]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE > ptp4l[17597.609]: master offset 1492 s2 adj -867 path delay 589 > ptp4l[17597.609]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED > ptp4l[17597.654]: recvmsg tx timestamp failed: Resource temporarily unavailable > ptp4l[17597.654]: port 1: send delay request failed > ptp4l[17597.654]: port 1: SLAVE to FAULTY on FAULT_DETECTED In order to get the best out of the 82576, I recommend: 1. Make sure you are using the latest version (ptp4l -v). 2. Set tx_timestamp_timeout to 1000. 3. Set fault_reset_interval to ASAP. 4. If the above steps do not yield reasonable results, then recompile the driver, changing IGB_PTP_TX_TIMEOUT from (HZ * 15) to (HZ). It appears that the hardware is sometimes missing or dropping the Tx time stamp on the delay request messages. Changing IGB_PTP_TX_TIMEOUT will clear the driver's Tx time stamp timer more often. This might make the card more responsive in the presence of time stamp loss. Good luck, Richard |
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From: Richard C. <ric...@gm...> - 2013-08-06 07:24:22
|
On Mon, Aug 05, 2013 at 02:58:12PM +0300, Гаврилов Александр wrote: > Hello!. > > Intel® 82576 Gigabit Ethernet Controller Datasheet: > "On both transmit and receive sides the timestamp values are locked in registers until values are read by > software. As a result if a new PTP packet that requires time stamp arrives before software access it is > not time stamped. In some cases in the receive path a packet that was timestamped might be lost and > not reach the host. To avoid a deadlock condition on the time stamp registers the software should keep > a watch dog timer to clear locking of the time stamp register. The interval counted by such a timer > should be at least higher then the expected interval between two Sync or Delay_Req packets depends > on the node state (Master or Slave)." > > How should I modify the source code of igb driver (or ptp4l) to use > the timer? The timer is already implemented in the driver. Moreover, the text you quote is about the *receive* path. You issue is occurring on the *transmit* path. Thanks, Richard |
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