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PTP IEEE 1588 stack for Linux
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From: Richard C. <ric...@gm...> - 2016-02-09 22:47:47
|
On Tue, Feb 09, 2016 at 02:13:50PM +0530, Rayagond Kokatanur wrote: > Is there any option to run both the clock on either UTC/TAI timescale ? For SW time stamping, there is no PHC, and thus we use UTC. For HW time stamping (PHC), there is no reason at all to use UTC. If a ptp4l node with a PHC becomes slave to a UTC master, then it applies the correction automatically. > No, I am not running phc2sys on MASTER. But if I run phy2sys on master > side (phy2sys -s /dev/ptp0 -w), then, Try it like this on the master: phc2sys -a -r -r Note the two 'r' flags. And on the slave: phc2sys -a -r See also the phc2sys man page. Thanks, Richard |
From: Rayagond K. <ray...@gm...> - 2016-02-09 08:43:57
|
On 9 February 2016 at 13:35, Richard Cochran <ric...@gm...> wrote: > On Tue, Feb 09, 2016 at 12:34:05PM +0530, Rayagond Kokatanur wrote: >> I also verified that there is no difference between >> MASTER PHC and MASTER system time,. > > There should be a difference. Your master's system time is in the UTC > timescale, but your master's PHC time is in the TAI timescale. Oh, is it expected behavior ? Is there any option to run both the clock on either UTC/TAI timescale ? > > Are you using phc2sys on the master side? If so, how? No, I am not running phc2sys on MASTER. But if I run phy2sys on master side (phy2sys -s /dev/ptp0 -w), then, a. Both MASTER and SLAVE system time will synchronize but I am seeing same 25-30sec difference between PHC and SYSTEM time on both MASTER and SLAVE. b. Both MASTER and SLAVE PHC are in sync. Thanks, Rayagond > > Thanks, > Richard |
From: Richard C. <ric...@gm...> - 2016-02-09 08:05:51
|
On Tue, Feb 09, 2016 at 12:34:05PM +0530, Rayagond Kokatanur wrote: > I also verified that there is no difference between > MASTER PHC and MASTER system time,. There should be a difference. Your master's system time is in the UTC timescale, but your master's PHC time is in the TAI timescale. Are you using phc2sys on the master side? If so, how? Thanks, Richard |
From: Rayagond K. <ray...@gm...> - 2016-02-09 07:04:12
|
Hi All, I am facing an issue where SLAVE system time is off by around 25-30sec wrt MASTER system time. Following is test setup, a. I have connected two DUT's back to back which supports HARDWARE timestamping. b. Changed the date and time on both the side and c. Ran ptp4l command (ptp4l -i eth0 -p /dev/ptp0 -m) on both sides. After ptp4l command, one DUT becomes SLAVE and other becomes GRANDMASTER. Both are able to exchange the ptp messages. I am able to verify that SLAVE PHC is getting synchronized to GRANDMASTER PHC. I also verified that there is no difference between MASTER PHC and MASTER system time,. d. But when I run phc2sys (phc2sys -s /dev/ptp0 -w) on SLAVE side, I could see that SLAVE system time is behind MASTER system time by 25-30sec. Is this issue due to phcsys command ? or anything related to driver. Please lets me know if any other points should be verified. Any other pointers in resolving the issue would be appreciated. Thanks and Regards, Rayagond |
From: Richard C. <ric...@gm...> - 2016-01-28 09:05:15
|
On Thu, Jan 28, 2016 at 04:10:44PM +0800, Pengfei zhao wrote: > We see, in ptpStack code, there is one definition of MAX_PORTS as > 8. It is basing on performance consideration? If we want to increase > it, for example 24, what is the potential impact? The value was only meant as a reasonable default. You can increase it to 24 without worry. FWIW, the hard coded limit was removed in v1.5. HTH Richard |
From: Pengfei z. <zha...@ms...> - 2016-01-28 08:10:52
|
Hi All, We see, in ptpStack code, there is one definition of MAX_PORTS as 8.It is basing on performance consideration? If we want to increase it, for example 24, what is the potential impact? thanks. BR,Simon |
From: Namit A. <nam...@gm...> - 2016-01-26 10:33:53
|
Namit Agrawal <namitagrawal88@...> writes: But the widely varying residence time can be taken care of in a simple (t2 - t1) and (t4 - t3). Because no matter what, the difference will always tell you the time it took to propagate including the residence time. I think the point that nobody explains to user is that when you are calculating the delay and offset by just dividing them by 2, you are assuming that propagation on both sides is the same which is not. So you cannot take average of something which is not equal on both sides. That's why you have to take into consideration the residence time. But this leads me to another question which is regarding the calculation done in the appendices of the IEEE Std. 1588 paper from page 201 to 219. Q. How and why is assumed mean path delay equal to calculated mean path delay?? Q. Why do we have to calculate separately mean path delay when a simple assumed mean path delay is giving us the answer?? |
From: Richard C. <ric...@gm...> - 2016-01-26 08:38:50
|
On Tue, Jan 26, 2016 at 04:31:47AM +0000, Namit Agrawal wrote: > Why are we separately building TCs and BCs to calculate residence times ?? Because each and every message will have its own widely varying residence time. > What is the use of that?? To correct for the variation by removing it. HTH Richard |
From: Namit A. <nam...@gm...> - 2016-01-26 04:32:02
|
Hi All, My question is not related to linuxptp, but its rather a general question about PTP protocol. In the IEEE Std paper of 1588 protocol, from page 201 to 219, there is an appendix in which they have given examples for use of TCs, BCs and OCs. One thing to notice is that the mean path delay calculated by means of residence time correction, asymmetry correction etc. comes out to be the same as the assumed mean path delay. Then why exactly do we take into consideration all this residence time, asymmetry etc. into our calculations?? Also, what exactly is the residence time because according to my understanding difference of the time from master to slave and vice versa will automatically give you the time (including residence time) it took to propagate from one end to other. For eg. Suppose the path is like this : Master -----------> Router1 -----------> Slave 5s 1s 5s (residence time) So suppose the packet started at t1 = 9:00 AM and reached slave at t2 = 9:02 and 11 seconds. So master and slave clocks have an offset of 2 minutes. But t2 - t1 ultimately takes into consideration the residence time also. Similarly on the other way: Slave -----------> Router1 -------> Router2 -----------> Slave 5s 1s 2s 5s (residence time) t4 - t3 will give us 13 seconds difference even if we do not calculate residence times separately. Why are we separately building TCs and BCs to calculate residence times ?? What is the use of that?? |
From: Richard C. <ric...@gm...> - 2016-01-24 19:42:28
|
On Sun, Jan 24, 2016 at 03:42:51PM +0000, Namit Agrawal wrote: > Hi All, > I am running linuxptp in software mode. This is the command that > I gave: > ptp4l -i eth0 -m -S > ptp4l[2562.960]: port 1: INITIALIZING to LISTENING on INITIALIZE > ptp4l[2562.961]: port 0: INITIALIZING to LISTENING on INITIALIZE > ptp4l[2569.982]: port 1: LISTENING to MASTER on > ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES > ptp4l[2569.982]: selected best master clock 080027.fffe.907de9 > ptp4l[2569.982]: assuming the grand master role > > It is stuck at this point. Is there any solution for this?? There is no problem that I can see. This is the expected output when your PC is the only PTP node in your network. Add another PTP node into your network, and something more interesting will happen, namely one node will begin synchronizing to the other one. > Also, can you explain me who is master, grandmaster and slave here. My > guess is system clock is slave, eth0 is master and ptp4l is grandmaster. > Am I right or wrong?? No, these terms having nothing to do with the system clock. Instead, they describe the role of a single port in the PTP state machine. Your port has progressed through the followings states: INITIALIZING -> LISTENING -> MASTER It did this because no better master was discovered in your network. (In fact, no other master at all is present.) HTH Richard |
From: Richard C. <ric...@gm...> - 2016-01-24 19:35:05
|
On Sun, Jan 24, 2016 at 03:40:50PM +0000, Namit Agrawal wrote: > This is the output of the following 2 commands: > ethtool -i eth0 > driver: e1000 ... > 00:03.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 02) Right, so this device doesn't have any HW timestamping abilities, and neither the igb nor the ixgbe drivers are useful here. (More info in my reply to your other post...) Thanks, Richard |
From: Namit A. <nam...@gm...> - 2016-01-24 15:45:12
|
Hi All, I am running linuxptp in software mode. This is the command that I gave: ptp4l -i eth0 -m -S ptp4l[2562.960]: port 1: INITIALIZING to LISTENING on INITIALIZE ptp4l[2562.961]: port 0: INITIALIZING to LISTENING on INITIALIZE ptp4l[2569.982]: port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES ptp4l[2569.982]: selected best master clock 080027.fffe.907de9 ptp4l[2569.982]: assuming the grand master role It is stuck at this point. Is there any solution for this?? Also, can you explain me who is master, grandmaster and slave here. My guess is system clock is slave, eth0 is master and ptp4l is grandmaster. Am I right or wrong?? |
From: Namit A. <nam...@gm...> - 2016-01-24 15:41:05
|
This is the output of the following 2 commands: ethtool -i eth0 driver: e1000 version: 7.3.21-k8-NAPI firmware-version: bus-info: 0000:00:03.0 supports-statistics: yes supports-test: yes supports-eeprom-access: yes supports-register-dump: yes supports-priv-flags: no lspci 00:00.0 Host bridge: Intel Corporation 440FX - 82441FX PMC [Natoma] (rev 02) 00:01.0 ISA bridge: Intel Corporation 82371SB PIIX3 ISA [Natoma/Triton II] 00:01.1 IDE interface: Intel Corporation 82371AB/EB/MB PIIX4 IDE (rev 01) 00:02.0 VGA compatible controller: InnoTek Systemberatung GmbH VirtualBox Graphics Adapter 00:03.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 02) 00:04.0 System peripheral: InnoTek Systemberatung GmbH VirtualBox Guest Service 00:05.0 Multimedia audio controller: Intel Corporation 82801AA AC'97 Audio Controller (rev 01) 00:06.0 USB controller: Apple Inc. KeyLargo/Intrepid USB 00:07.0 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 08) 00:0d.0 SATA controller: Intel Corporation 82801HM/HEM (ICH8M/ICH8M-E) SATA Controller [AHCI mode] (rev 02) |
From: Richard C. <ric...@gm...> - 2016-01-22 09:37:38
|
On Fri, Jan 22, 2016 at 05:22:00AM +0000, Namit wrote: > I installed ixgbe driver also. But still no results. > Also I tried to install igb driver but it is not compatible with the current > kernel. Those two drivers are for two completely different cards. First off, you need to find out what hardware you have for eth0. What do the following two commands tell you? 1. ethtool -i eth0 2. lspci Thanks, Richard |
From: Namit <nam...@gm...> - 2016-01-22 05:25:14
|
Hi, For the past week, I am trying to run linuxptp-1.6 but it is giving errors. I give the following command- "ptp4l -i eth0 -m" The error is "the device eth0 does not have timestamping capability". Also when I run ethtool -i eth0 it gives that \ PTP Hardware Clock : none Hardware Transmit Timestamp Modes : none Hardware receive Filter Modes : none I installed ixgbe driver also. But still no results. Also I tried to install igb driver but it is not compatible with the current kernel. My question is : "How do I enable hardware timestamping and PTP clock hardware in ubuntu 14.04??" Also, I try to run the code testptp.c but it is also throwing several errors like: storage value of desc not defined undeclared n_pins etc. etc. Please help me out.. |
From: Miroslav L. <mli...@re...> - 2016-01-21 16:25:59
|
On Wed, Jan 20, 2016 at 10:13:33PM +0100, Richard Cochran wrote: > Rich Schmidt sent me this photo he had already made. > > http://linuxptp.sourceforge.net/i210/i210-SDPs.jpg > > The "Software Defined Pins" (SDP) are on the right side of the 6 pin > header. On the left side you have one 3.3V pin and two ground pins. > > The signal level is CMOS, and there is no ESD protection at all. > Be careful! Great, thanks for the information. I'll see if I can get an i210 and connect a GPS PPS signal to it. The PPS is at the TTL level so I guess I just need a voltage divider. -- Miroslav Lichvar |
From: Richard C. <ric...@gm...> - 2016-01-20 21:13:45
|
On Wed, Jan 20, 2016 at 02:13:35PM +0100, Richard Cochran wrote: > On Wed, Jan 20, 2016 at 12:13:13PM +0100, Miroslav Lichvar wrote: > > I would like to try this. I don't have an i210 card nearby, but I > > assume it requires some soldering. Do you have any pictures that show > > where the connection should go and how big is the pad? > > The card has a 6 pin header, so no soldering is required. I couldn't > find any documentation, and so I ohm'ed the pins out to the chip. > I'll post a photo and my notes. Rich Schmidt sent me this photo he had already made. http://linuxptp.sourceforge.net/i210/i210-SDPs.jpg The "Software Defined Pins" (SDP) are on the right side of the 6 pin header. On the left side you have one 3.3V pin and two ground pins. The signal level is CMOS, and there is no ESD protection at all. Be careful! The SDPs can be programmed as inputs (time stamps on signal edges) or as outputs (periodic signals). You can do some interesting things with them. I once made a BC with 3 cards on one mother board, letting the "lead" card send a 1 PPS to the other two, using the external time stamps to lock to the lead card. HTH, Richard |
From: Keller, J. E <jac...@in...> - 2016-01-20 17:23:24
|
These should be documented in the data sheet. But I believe what's in the kernel is correct. Regards, Jake On Wed, 2016-01-20 at 14:13 +0100, Richard Cochran wrote: > On Wed, Jan 20, 2016 at 12:13:13PM +0100, Miroslav Lichvar wrote: > > I would like to try this. I don't have an i210 card nearby, but I > > assume it requires some soldering. Do you have any pictures that > > show > > where the connection should go and how big is the pad? > > The card has a 6 pin header, so no soldering is required. I couldn't > find any documentation, and so I ohm'ed the pins out to the chip. > I'll post a photo and my notes. > > Thanks, > Richard > > > > ------------------------------------------------------------------- > ----------- > Site24x7 APM Insight: Get Deep Visibility into Application > Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > Linuxptp-users mailing list > Lin...@li... > https://lists.sourceforge.net/lists/listinfo/linuxptp-users |
From: Richard C. <ric...@gm...> - 2016-01-20 13:13:46
|
On Wed, Jan 20, 2016 at 12:13:13PM +0100, Miroslav Lichvar wrote: > I would like to try this. I don't have an i210 card nearby, but I > assume it requires some soldering. Do you have any pictures that show > where the connection should go and how big is the pad? The card has a 6 pin header, so no soldering is required. I couldn't find any documentation, and so I ohm'ed the pins out to the chip. I'll post a photo and my notes. Thanks, Richard |
From: Miroslav L. <mli...@re...> - 2016-01-20 11:13:21
|
On Wed, Jan 20, 2016 at 11:56:31AM +0100, Richard Cochran wrote: > Yes, that is the idea. The i210 has two input pins at CMOS level, and > the most recent Linux kernels support time stamps of external signals > in the i210 driver. I would like to try this. I don't have an i210 card nearby, but I assume it requires some soldering. Do you have any pictures that show where the connection should go and how big is the pad? -- Miroslav Lichvar |
From: Richard C. <ric...@gm...> - 2016-01-20 10:56:42
|
On Wed, Jan 20, 2016 at 02:35:26PM +0530, Aniket Hendre wrote: > So you want to say that instead of steer phy clock of master to synchronize > with its system clock, it is better to steer phy clock by using direct PPS > feeding through intel i210 card. So I don't need to feed PPS to my master > machine through serial port (correct me if i am wrong). Yes, that is the idea. The i210 has two input pins at CMOS level, and the most recent Linux kernels support time stamps of external signals in the i210 driver. (It does not solve your 2/20 km problem, though.) Thanks, Richard |
From: Richard C. <ric...@gm...> - 2016-01-19 16:12:25
|
On Tue, Jan 19, 2016 at 05:30:10PM +0530, Aniket Hendre wrote: > *phc2sys -s CLOCK_REALTIME -c eth1 -m -O -35 * FYI, you should be aware that this method reads time stamps over the PCIe interface. Because of the delay and uncertainty in reading single values over PCIe, this introduces a time error on the order of microseconds. You can avoid this error by directly feeding the 1-PPS into PTP card that supports external time stamps (like the Intel i210). Then you can write a little servo to discipline the PTP card to the GPS clock. > I mean to say that I am observing offset at slave side and noticed that the > offset from master is large for large distance between master and slave. Not sure what you mean. Can you post the client side ptp4l logs for both cases? Thanks, Richard |
From: Richard C. <ric...@gm...> - 2016-01-19 09:38:39
|
On Tue, Jan 19, 2016 at 09:47:40AM +0530, Aniket Hendre wrote: > Richard I have a server class machine (Dell R720) which is locked to my > GPS10RBN frequency and time standards unit using Network Time Protocol > (NTP). Simultaneously I have 1PPS out from GPS10RBN which I have connected > to my server class machine. NTP daemon has been configured on server class > machine to use this 1PPS by adding following line in /etc/ntp.conf. > > server 127.127.22.0 minpoll 4 maxpoll 4 > fudge 127.127.22.0 refid PPS flag3 1 flag4 1 time1 -0.060 Do you have a GPS at the master and at the slaves nodes, or only at the master? > So I do believe that my Dell R720 is now behaving like a PTP grandmaster. > (correct me if I am wrong). Well, NTP will correct the Linux system time, but not the time in your PHC device. What MAC/PHY hardware are you using? How have you configured ptp4l and phc2sys on each node? > I am now trying to first synchronise two PHY clock by running ptp4l, where > I have observed offset changes w.r.t distance. What do you mean by "observed offset changes"? Do you mean perhaps the observed jitter? ptp4l will always reduce the observed offset to zero, even in the presence of asymmetry. Thanks, Richard |
From: Xavier B. <xav...@fr...> - 2016-01-18 13:34:22
|
Hi Aniket, Le vendredi 15 janvier 2016 à 15:51 +0530, aniket a écrit : > Hi...very good afternoon to all. > > Myself Aniket Hendre, project engineer C from National Centre for Radio > Astrophysics, India. > > I am synchronising two boundary clocks using ptp4l. I found that the > offset at the slave PHY clock from master PHY clock varies with respect > to distance between these clocks. > > In my first experiment, master and slave are 2 Km away from each other. > In this case I got offset at slave PHY clock around 50 nano second. Over such a distance you may be interested in https://en.wikipedia.org/wiki/The_White_Rabbit_Project Regards, Xav |
From: Keller, J. E <jac...@in...> - 2016-01-15 23:57:37
|
On Fri, 2016-01-15 at 19:40 +0000, Daniel Le wrote: > Hi Jake, > > Because my hardware NIC is not 1588 capable and that would require > FPGA change, however I'm hoping to get better timestamp accuracy from > the hardware clock that is tuned to the host system clock in software > timestamping mode (which I understand it's in the reverse direction > of LinuxPTP hardware timestamping configuration where the system > clock synchronizes to the PHC clock instead). > > Daniel If you have a hardware clock which you can slew, and the ability to take hardware timestamps I am failing to see how you are unable to implement the PHC subsystem calls? I suspect however you are converting the timestamps taken by hardware is incorrect, and we can't help you with that easily. This is the first place I would look for an issue, especially if you can confirm that your software timestamps without the special ethernet driver work as expected. Regards, Jake |