From: Mike F. <va...@ge...> - 2004-06-27 22:29:37
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On Saturday 26 June 2004 05:15 pm, Michael Robinson wrote: > Interestingly enough we don't need them, all they are is simple > logic to isolate the IDE bus from the parallel port and select which way > the data can flow, they can be implemented with logic in the Xilinx. yeah, i know they're just simple logic chips, but my strength lies in higher languages, so i didnt think too much of reworking the design ... at least not until i got the thing built ;) > We may be able to improve the operation speed too if we use the 7.5 ns > version of the Xilinx versus the 15 ns version Kiyoshi used. That's > half of the delay of Kiyoshi's version. I'm going to try integrating > all of the logic into the Xilinx that way I can play around with it and > add extra logic so you can use multiple devices, etc. that'd be awesome ... at this point though, i see any hd interface as being a billion times better than trying to develop over a nfs root ;) > I'll put the > datasheets for the parts I found up in case anyone needs them. Also, > about the programmer, you can build one for about $10.00 from the > parallel programmer schematic in Xilinx's JTAG manual, I'll post that > too for anyone whois interested. Good luck. i bought a programmer on ebay (managed to get lucky) but i'd like to get the documents you refer to ... i can post them on the linuxdc site under the dcext page ... -mike |