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[Linuxconsole-commit]CVS: ruby/linux/arch/ppc/platforms k2_setup.c,NONE,1.1 lopec_setup.c,NONE,1.1 mcpn765_setup.c,NONE,1.1 menf1_setup.c,NONE,1.1 mvme5100_setup.c,NONE,1.1 pcore_setup.c,NONE,1.1 prpmc750_setup.c,NONE,1.1 prpmc800_setup.c,NONE,1.1 sandpoint_setup.c,1.5,1.6 spruce_setup.c,1.3,1.4 chrp_setup.c,1.7,1.8 pmac_setup.c,1.5,1.6 pplus_setup.c,1.4,1.5 prep_setup.c,1.7,1.8 apus_setup.c,1.1,NONE
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From: James S. <jsi...@us...> - 2002-11-23 00:56:22
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Update of /cvsroot/linuxconsole/ruby/linux/arch/ppc/platforms
In directory sc8-pr-cvs1:/tmp/cvs-serv1514/linux/arch/ppc/platforms
Modified Files:
chrp_setup.c pmac_setup.c pplus_setup.c prep_setup.c
Added Files:
k2_setup.c lopec_setup.c mcpn765_setup.c menf1_setup.c
mvme5100_setup.c pcore_setup.c prpmc750_setup.c
prpmc800_setup.c sandpoint_setup.c spruce_setup.c
Removed Files:
apus_setup.c
Log Message:
Synced to 2.5.49 console BK tree.
--- NEW FILE: k2_setup.c ---
/*
* arch/ppc/platforms/k2_setup.c
*
* Board setup routines for SBS K2
*
* Author: Matt Porter <mp...@mv...>
*
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/major.h>
#include <linux/blk.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/irq.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/time.h>
#include <asm/i8259.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#include "k2.h"
extern void k2_setup_hoses(void);
extern unsigned long loops_per_jiffy;
static unsigned int cpu_7xx[16] = {
0, 15, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
};
static unsigned int cpu_6xx[16] = {
0, 0, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 0, 12, 7, 0
};
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
/* IDE functions */
static void __init
k2_ide_init_hwif_ports (hw_regs_t *hw, ide_ioreg_t data_port,
ide_ioreg_t ctrl_port, int *irq)
{
ide_ioreg_t reg = data_port;
int i = 8;
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw->io_ports[i] = reg;
reg += 1;
}
if (ctrl_port)
hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
else
hw->io_ports[IDE_CONTROL_OFFSET] =
hw->io_ports[IDE_DATA_OFFSET] + 0x206;
if (irq != NULL)
*irq = 0;
}
#endif
static int
k2_get_bus_speed(void)
{
int bus_speed;
unsigned char board_id;
board_id = *(unsigned char *)K2_BOARD_ID_REG;
switch( K2_BUS_SPD(board_id) ) {
case 0:
default:
bus_speed = 100000000;
break;
case 1:
bus_speed = 83333333;
break;
case 2:
bus_speed = 75000000;
break;
case 3:
bus_speed = 66666666;
break;
}
return bus_speed;
}
static int
k2_get_cpu_speed(void)
{
unsigned long hid1;
int cpu_speed;
hid1 = mfspr(HID1) >> 28;
if ((mfspr(PVR) >> 16) == 8)
hid1 = cpu_7xx[hid1];
else
hid1 = cpu_6xx[hid1];
cpu_speed = k2_get_bus_speed()*hid1/2;
return cpu_speed;
}
static void __init
k2_calibrate_decr(void)
{
int freq, divisor = 4;
/* determine processor bus speed */
freq = k2_get_bus_speed();
tb_ticks_per_jiffy = freq / HZ / divisor;
tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
}
static int
k2_show_cpuinfo(struct seq_file *m)
{
unsigned char k2_geo_bits, k2_system_slot;
seq_printf(m, "vendor\t\t: SBS\n");
seq_printf(m, "machine\t\t: K2\n");
seq_printf(m, "cpu speed\t: %dMhz\n", k2_get_cpu_speed()/1000000);
seq_printf(m, "bus speed\t: %dMhz\n", k2_get_bus_speed()/1000000);
seq_printf(m, "memory type\t: SDRAM\n");
k2_geo_bits = readb(K2_MSIZ_GEO_REG) & K2_GEO_ADR_MASK;
k2_system_slot = !(readb(K2_MISC_REG) & K2_SYS_SLOT_MASK);
seq_printf(m, "backplane\t: %s slot board",
k2_system_slot ? "System" : "Non system");
seq_printf(m, "with geographical address %x\n", k2_geo_bits);
return 0;
}
extern char cmd_line[];
TODC_ALLOC();
static void __init
k2_setup_arch(void)
{
unsigned int cpu;
/* Setup TODC access */
TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
ioremap(K2_RTC_BASE_ADDRESS, K2_RTC_SIZE),
8);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridges */
k2_setup_hoses();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDC1;
#endif
/* Identify the system */
printk("System Identification: SBS K2 - PowerPC 750 @ %d Mhz\n", k2_get_cpu_speed()/1000000);
printk("SBS K2 port (C) 2001 MontaVista Software, Inc. (so...@mv...)\n");
/* Identify the CPU manufacturer */
cpu = PVR_REV(mfspr(PVR));
printk("CPU manufacturer: %s [rev=%04x]\n", (cpu & (1<<15)) ? "IBM" :
"Motorola", cpu);
}
static void
k2_restart(char *cmd)
{
local_irq_disable();
/* SRR0 has system reset vector, SRR1 has default MSR value */
/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
__asm__ __volatile__
("lis 3,0xfff0\n\t"
"ori 3,3,0x0100\n\t"
"mtspr 26,3\n\t"
"li 3,0\n\t"
"mtspr 27,3\n\t"
"rfi\n\t");
for(;;);
}
static void
k2_power_off(void)
{
for(;;);
}
static void
k2_halt(void)
{
k2_restart(NULL);
}
/*
* Set BAT 3 to map PCI32 I/O space.
*/
static __inline__ void
k2_set_bat(void)
{
unsigned long bat3u, bat3l;
static int mapping_set = 0;
if (!mapping_set)
{
__asm__ __volatile__
("lis %0,0x8000\n\t"
"ori %1,%0,0x002a\n\t"
"ori %0,%0,0x1ffe\n\t"
"mtspr 0x21e,%0\n\t"
"mtspr 0x21f,%1\n\t"
"isync\n\t"
"sync\n\t"
: "=r" (bat3u), "=r" (bat3l));
mapping_set = 1;
}
return;
}
static unsigned long __init
k2_find_end_of_memory(void)
{
unsigned long total;
unsigned char msize = 7; /* Default to 128MB */
k2_set_bat();
msize = K2_MEM_SIZE(readb(K2_MSIZ_GEO_REG));
switch (msize)
{
case 2:
/*
* This will break without a lowered
* KERNELBASE or CONFIG_HIGHMEM on.
* It seems non 1GB builds exist yet,
* though.
*/
total = K2_MEM_SIZE_1GB;
break;
case 3:
case 4:
total = K2_MEM_SIZE_512MB;
break;
case 5:
case 6:
total = K2_MEM_SIZE_256MB;
break;
case 7:
total = K2_MEM_SIZE_128MB;
break;
default:
printk("K2: Invalid memory size detected, defaulting to 128MB\n");
total = K2_MEM_SIZE_128MB;
break;
}
return total;
}
static void __init
k2_map_io(void)
{
io_block_mapping(K2_PCI32_IO_BASE,
K2_PCI32_IO_BASE,
0x00200000,
_PAGE_IO);
io_block_mapping(0xff000000,
0xff000000,
0x01000000,
_PAGE_IO);
}
static void __init
k2_init_irq(void)
{
int i;
for ( i = 0 ; i < 16 ; i++ )
irq_desc[i].handler = &i8259_pic;
i8259_init(NULL);
}
static int
k2_get_irq(struct pt_regs *regs)
{
return i8259_poll();
}
void __init platform_init(unsigned long r3, unsigned long r4,
unsigned long r5, unsigned long r6, unsigned long r7)
{
parse_bootinfo((struct bi_record *) (r3 + KERNELBASE));
isa_io_base = K2_ISA_IO_BASE;
isa_mem_base = K2_ISA_MEM_BASE;
pci_dram_offset = K2_PCI32_SYS_MEM_BASE;
ppc_md.setup_arch = k2_setup_arch;
ppc_md.show_cpuinfo = k2_show_cpuinfo;
ppc_md.init_IRQ = k2_init_irq;
ppc_md.get_irq = k2_get_irq;
ppc_md.find_end_of_memory = k2_find_end_of_memory;
ppc_md.setup_io_mappings = k2_map_io;
ppc_md.restart = k2_restart;
ppc_md.power_off = k2_power_off;
ppc_md.halt = k2_halt;
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.calibrate_decr = k2_calibrate_decr;
ppc_md.nvram_read_val = todc_direct_read_val;
ppc_md.nvram_write_val = todc_direct_write_val;
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
ppc_ide_md.ide_init_hwif = k2_ide_init_hwif_ports;
#endif
}
--- NEW FILE: lopec_setup.c ---
/*
* arch/ppc/platforms/lopec_setup.c
*
* Setup routines for the Motorola LoPEC.
*
* Author: Dan Cox
* da...@mv...
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/config.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/pci_ids.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <linux/seq_file.h>
#include <linux/blk.h>
#include <linux/root_dev.h>
#include <asm/io.h>
#include <asm/open_pic.h>
#include <asm/i8259.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#include <asm/mpc10x.h>
#include <asm/hw_irq.h>
#include <asm/prep_nvram.h>
extern char saved_command_line[];
extern void lopec_find_bridges(void);
/*
* Define all of the IRQ senses and polarities. Taken from the
* LoPEC Programmer's Reference Guide.
*/
static u_char lopec_openpic_initsenses[16] __initdata = {
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 0 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 1 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 2 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 3 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 4 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 5 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 6 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 7 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 8 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 9 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 10 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 11 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 12 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 13 */
(IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ 14 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* IRQ 15 */
};
static int
lopec_show_cpuinfo(struct seq_file *m)
{
seq_printf(m, "machine\t\t: Motorola LoPEC\n");
return 0;
}
static u32
lopec_irq_cannonicalize(u32 irq)
{
if (irq == 2)
return 9;
else
return irq;
}
static void
lopec_restart(char *cmd)
{
#define LOPEC_SYSSTAT1 0xffe00000
/* force a hard reset, if possible */
unsigned char reg = *((unsigned char *) LOPEC_SYSSTAT1);
reg |= 0x80;
*((unsigned char *) LOPEC_SYSSTAT1) = reg;
local_irq_disable();
while(1);
#undef LOPEC_SYSSTAT1
}
static void
lopec_halt(void)
{
local_irq_disable();
while(1);
}
static void
lopec_power_off(void)
{
lopec_halt();
}
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
int lopec_ide_ports_known = 0;
static ide_ioreg_t lopec_ide_regbase[MAX_HWIFS];
static ide_ioreg_t lopec_ide_ctl_regbase[MAX_HWIFS];
static ide_ioreg_t lopec_idedma_regbase;
static void
lopec_ide_probe(void)
{
struct pci_dev *dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
PCI_DEVICE_ID_WINBOND_82C105,
NULL);
lopec_ide_ports_known = 1;
if (dev) {
lopec_ide_regbase[0] = dev->resource[0].start;
lopec_ide_regbase[1] = dev->resource[2].start;
lopec_ide_ctl_regbase[0] = dev->resource[1].start;
lopec_ide_ctl_regbase[1] = dev->resource[3].start;
lopec_idedma_regbase = dev->resource[4].start;
}
}
static int
lopec_ide_default_irq(ide_ioreg_t base)
{
if (lopec_ide_ports_known == 0)
lopec_ide_probe();
if (base == lopec_ide_regbase[0])
return 14;
else if (base == lopec_ide_regbase[1])
return 15;
else
return 0;
}
static ide_ioreg_t
lopec_ide_default_io_base(int index)
{
if (lopec_ide_ports_known == 0)
lopec_ide_probe();
return lopec_ide_regbase[index];
}
static void __init
lopec_ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data,
ide_ioreg_t ctl, int *irq)
{
ide_ioreg_t reg = data;
uint alt_status_base;
int i;
for(i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
hw->io_ports[i] = reg++;
if (data == lopec_ide_regbase[0]) {
alt_status_base = lopec_ide_ctl_regbase[0] + 2;
hw->irq = 14;
}
else if (data == lopec_ide_regbase[1]) {
alt_status_base = lopec_ide_ctl_regbase[1] + 2;
hw->irq = 15;
}
else {
alt_status_base = 0;
hw->irq = 0;
}
if (ctl)
hw->io_ports[IDE_CONTROL_OFFSET] = ctl;
else
hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
if (irq != NULL)
*irq = hw->irq;
}
#endif /* BLK_DEV_IDE */
static void __init
lopec_init_IRQ(void)
{
int i;
/*
* Provide the open_pic code with the correct table of interrupts.
*/
OpenPIC_InitSenses = lopec_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(lopec_openpic_initsenses);
/*
* We need to tell openpic_set_sources where things actually are.
* mpc10x_common will setup OpenPIC_Addr at ioremap(EUMB phys base +
* EPIC offset (0x40000)); The EPIC IRQ Register Address Map -
* Interrupt Source Configuration Registers gives these numbers
* as offsets starting at 0x50200, we need to adjust occordinly.
*/
/* Map serial interrupts 0-15 */
openpic_set_sources(0, 16, OpenPIC_Addr + 0x10200);
/* Skip reserved space and map i2c and DMA Ch[01] */
openpic_set_sources(16, 3, OpenPIC_Addr + 0x11020);
/* Skip reserved space and map Message Unit Interrupt (I2O) */
openpic_set_sources(19, 1, OpenPIC_Addr + 0x110C0);
openpic_init(NUM_8259_INTERRUPTS);
/* Map i8259 interrupts */
for(i = 0; i < NUM_8259_INTERRUPTS; i++)
irq_desc[i].handler = &i8259_pic;
/*
* The EPIC allows for a read in the range of 0xFEF00000 ->
* 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
*/
i8259_init(0xfef00000);
}
static int __init
lopec_request_io(void)
{
outb(0x00, 0x4d0);
outb(0xc0, 0x4d1);
request_region(0x00, 0x20, "dma1");
request_region(0x20, 0x20, "pic1");
request_region(0x40, 0x20, "timer");
request_region(0x80, 0x10, "dma page reg");
request_region(0xa0, 0x20, "pic2");
request_region(0xc0, 0x20, "dma2");
return 0;
}
device_initcall(lopec_request_io);
static void __init
lopec_map_io(void)
{
io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
io_block_mapping(0xb0000000, 0xb0000000, 0x10000000, _PAGE_IO);
}
static void __init
lopec_set_bat(void)
{
unsigned long batu, batl;
__asm__ __volatile__(
"lis %0,0xf800\n \
ori %1,%0,0x002a\n \
ori %0,%0,0x0ffe\n \
mtspr 0x21e,%0\n \
mtspr 0x21f,%1\n \
isync\n \
sync "
: "=r" (batu), "=r" (batl));
}
#ifdef CONFIG_SERIAL_TEXT_DEBUG
#include <linux/serial.h>
#include <linux/serialP.h>
#include <linux/serial_reg.h>
#include <asm/serial.h>
static struct serial_state rs_table[RS_TABLE_SIZE] = {
SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
};
volatile unsigned char *com_port;
volatile unsigned char *com_port_lsr;
static void
serial_writechar(char c)
{
while ((*com_port_lsr & UART_LSR_THRE) == 0)
;
*com_port = c;
}
void
lopec_progress(char *s, unsigned short hex)
{
volatile char c;
com_port = (volatile unsigned char *) rs_table[0].port;
com_port_lsr = com_port + UART_LSR;
while ((c = *s++) != 0)
serial_writechar(c);
/* Most messages don't have a newline in them */
serial_writechar('\n');
serial_writechar('\r');
}
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
TODC_ALLOC();
static void __init
lopec_setup_arch(void)
{
TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
ioremap(0xffe80000, 0x8000), 8);
loops_per_jiffy = 100000000/HZ;
lopec_find_bridges();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#elif defined(CONFIG_ROOT_NFS)
ROOT_DEV = Root_NFS;
#elif defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
ROOT_DEV = Root_HDA1;
#else
ROOT_DEV = Root_SDA1;
#endif
#ifdef CONFIG_PPCBUG_NVRAM
/* Read in NVRAM data */
init_prep_nvram();
/* if no bootargs, look in NVRAM */
if ( cmd_line[0] == '\0' ) {
char *bootargs;
bootargs = prep_nvram_get_var("bootargs");
if (bootargs != NULL) {
strcpy(cmd_line, bootargs);
/* again.. */
strcpy(saved_command_line, cmd_line);
}
}
#endif
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
lopec_set_bat();
isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
ISA_DMA_THRESHOLD = 0x00ffffff;
DMA_MODE_READ = 0x44;
DMA_MODE_WRITE = 0x48;
ppc_md.setup_arch = lopec_setup_arch;
ppc_md.show_cpuinfo = lopec_show_cpuinfo;
ppc_md.irq_cannonicalize = lopec_irq_cannonicalize;
ppc_md.init_IRQ = lopec_init_IRQ;
ppc_md.get_irq = openpic_get_irq;
ppc_md.restart = lopec_restart;
ppc_md.power_off = lopec_power_off;
ppc_md.halt = lopec_halt;
ppc_md.setup_io_mappings = lopec_map_io;
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.calibrate_decr = todc_calibrate_decr;
ppc_md.nvram_read_val = todc_direct_read_val;
ppc_md.nvram_write_val = todc_direct_write_val;
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_ID_MODULE)
ppc_ide_md.default_irq = lopec_ide_default_irq;
ppc_ide_md.default_io_base = lopec_ide_default_io_base;
ppc_ide_md.ide_init_hwif = lopec_ide_init_hwif_ports;
#endif
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = lopec_progress;
#endif
}
--- NEW FILE: mcpn765_setup.c ---
/*
* arch/ppc/platforms/mcpn765_setup.c
*
* Board setup routines for the Motorola MCG MCPN765 cPCI Board.
*
* Author: Mark A. Greer
* mg...@mv...
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/*
* This file adds support for the Motorola MCG MCPN765.
*/
#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/blk.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/ide.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/time.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/prom.h>
#include <asm/smp.h>
#include <asm/open_pic.h>
#include <asm/i8259.h>
#include <asm/todc.h>
#include <asm/pci-bridge.h>
#include <asm/bootinfo.h>
#include <asm/pplus.h>
#include "mcpn765.h"
static u_char mcpn765_openpic_initsenses[] __initdata = {
0, /* 16: i8259 cascade (active high) */
1, /* 17: COM1,2,3,4 */
1, /* 18: Enet 1 (front panel) */
1, /* 19: HAWK WDT XXXX */
1, /* 20: 21554 PCI-PCI bridge */
1, /* 21: cPCI INTA# */
1, /* 22: cPCI INTB# */
1, /* 23: cPCI INTC# */
1, /* 24: cPCI INTD# */
1, /* 25: PMC1 INTA#, PMC2 INTB# */
1, /* 26: PMC1 INTB#, PMC2 INTC# */
1, /* 27: PMC1 INTC#, PMC2 INTD# */
1, /* 28: PMC1 INTD#, PMC2 INTA# */
1, /* 29: Enet 2 (connected to J3) */
1, /* 30: Abort Switch */
1, /* 31: RTC Alarm */
};
extern u_int openpic_irq(void);
extern char cmd_line[];
int use_of_interrupt_tree = 0;
static void mcpn765_halt(void);
TODC_ALLOC();
static void __init
mcpn765_setup_arch(void)
{
struct pci_controller *hose;
if ( ppc_md.progress )
ppc_md.progress("mcpn765_setup_arch: enter", 0);
loops_per_jiffy = 50000000 / HZ;
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_SDA2;
#endif
if ( ppc_md.progress )
ppc_md.progress("mcpn765_setup_arch: find_bridges", 0);
/* Lookup PCI host bridges */
mcpn765_find_bridges();
hose = pci_bus_to_hose(0);
isa_io_base = (ulong)hose->io_base_virt;
TODC_INIT(TODC_TYPE_MK48T37,
(MCPN765_PHYS_NVRAM_AS0 - isa_io_base),
(MCPN765_PHYS_NVRAM_AS1 - isa_io_base),
(MCPN765_PHYS_NVRAM_DATA - isa_io_base),
8);
OpenPIC_InitSenses = mcpn765_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(mcpn765_openpic_initsenses);
printk("Motorola MCG MCPN765 cPCI Non-System Board\n");
printk("MCPN765 port (MontaVista Software, Inc. (so...@mv...))\n");
if ( ppc_md.progress )
ppc_md.progress("mcpn765_setup_arch: exit", 0);
return;
}
/*
* Initialize the VIA 82c586b.
*/
static void __init
mcpn765_setup_via_82c586b(void)
{
struct pci_dev *dev;
u_char c;
if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_82C586_1,
NULL)) == NULL) {
printk("No VIA ISA bridge found\n");
mcpn765_halt();
/* NOTREACHED */
}
/*
* PPCBug doesn't set the enable bits for the IDE device.
* Turn them on now.
*/
pci_read_config_byte(dev, 0x40, &c);
c |= 0x03;
pci_write_config_byte(dev, 0x40, c);
return;
}
static void __init
mcpn765_init2(void)
{
/* Do MCPN765 board specific initialization. */
mcpn765_setup_via_82c586b();
request_region(0x00,0x20,"dma1");
request_region(0x20,0x20,"pic1");
request_region(0x40,0x20,"timer");
request_region(0x80,0x10,"dma page reg");
request_region(0xa0,0x20,"pic2");
request_region(0xc0,0x20,"dma2");
return;
}
/*
* Interrupt setup and service.
* Have MPIC on HAWK and cascaded 8259s on VIA 82586 cascaded to MPIC.
*/
static void __init
mcpn765_init_IRQ(void)
{
int i;
if ( ppc_md.progress )
ppc_md.progress("init_irq: enter", 0);
openpic_init(1, NUM_8259_INTERRUPTS, NULL, -1);
for(i=0; i < NUM_8259_INTERRUPTS; i++)
irq_desc[i].handler = &i8259_pic;
i8259_init(NULL);
if ( ppc_md.progress )
ppc_md.progress("init_irq: exit", 0);
return;
}
static u32
mcpn765_irq_cannonicalize(u32 irq)
{
if (irq == 2)
return 9;
else
return irq;
}
static unsigned long __init
mcpn765_find_end_of_memory(void)
{
return pplus_get_mem_size(MCPN765_HAWK_SMC_BASE);
}
static void __init
mcpn765_map_io(void)
{
io_block_mapping(0xfe800000, 0xfe800000, 0x00800000, _PAGE_IO);
}
static void
mcpn765_reset_board(void)
{
local_irq_disable();
/* Set exception prefix high - to the firmware */
_nmask_and_or_msr(0, MSR_IP);
out_8((u_char *)MCPN765_BOARD_MODRST_REG, 0x01);
return;
}
static void
mcpn765_restart(char *cmd)
{
volatile ulong i = 10000000;
mcpn765_reset_board();
while (i-- > 0);
panic("restart failed\n");
}
static void
mcpn765_power_off(void)
{
mcpn765_halt();
/* NOTREACHED */
}
static void
mcpn765_halt(void)
{
local_irq_disable();
while (1);
/* NOTREACHED */
}
static int
mcpn765_show_cpuinfo(struct seq_file *m)
{
seq_printf(m, "vendor\t\t: Motorola MCG\n");
seq_printf(m, "machine\t\t: MCPN765\n");
return 0;
}
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
/*
* IDE support.
*/
static int mcpn765_ide_ports_known = 0;
static ide_ioreg_t mcpn765_ide_regbase[MAX_HWIFS];
static ide_ioreg_t mcpn765_ide_ctl_regbase[MAX_HWIFS];
static ide_ioreg_t mcpn765_idedma_regbase;
static void
mcpn765_ide_probe(void)
{
struct pci_dev *pdev = pci_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_82C586_1,
NULL);
if(pdev) {
mcpn765_ide_regbase[0]=pdev->resource[0].start;
mcpn765_ide_regbase[1]=pdev->resource[2].start;
mcpn765_ide_ctl_regbase[0]=pdev->resource[1].start;
mcpn765_ide_ctl_regbase[1]=pdev->resource[3].start;
mcpn765_idedma_regbase=pdev->resource[4].start;
}
mcpn765_ide_ports_known = 1;
return;
}
static int
mcpn765_ide_default_irq(ide_ioreg_t base)
{
if (mcpn765_ide_ports_known == 0)
mcpn765_ide_probe();
if (base == mcpn765_ide_regbase[0])
return 14;
else if (base == mcpn765_ide_regbase[1])
return 14;
else
return 0;
}
static ide_ioreg_t
mcpn765_ide_default_io_base(int index)
{
if (mcpn765_ide_ports_known == 0)
mcpn765_ide_probe();
return mcpn765_ide_regbase[index];
}
static void __init
mcpn765_ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port,
ide_ioreg_t ctrl_port, int *irq)
{
ide_ioreg_t reg = data_port;
uint alt_status_base;
int i;
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw->io_ports[i] = reg++;
}
if (data_port == mcpn765_ide_regbase[0]) {
alt_status_base = mcpn765_ide_ctl_regbase[0] + 2;
hw->irq = 14;
} else if (data_port == mcpn765_ide_regbase[1]) {
alt_status_base = mcpn765_ide_ctl_regbase[1] + 2;
hw->irq = 14;
} else {
alt_status_base = 0;
hw->irq = 0;
}
if (ctrl_port)
hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
else
hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
if (irq != NULL)
*irq = hw->irq;
return;
}
#endif
/*
* Set BAT 3 to map 0xf0000000 to end of physical memory space.
*/
static __inline__ void
mcpn765_set_bat(void)
{
unsigned long bat3u, bat3l;
static int mapping_set = 0;
if (!mapping_set) {
__asm__ __volatile__(
" lis %0,0xf000\n \
ori %1,%0,0x002a\n \
ori %0,%0,0x1ffe\n \
mtspr 0x21e,%0\n \
mtspr 0x21f,%1\n \
isync\n \
sync "
: "=r" (bat3u), "=r" (bat3l));
mapping_set = 1;
}
return;
}
#ifdef CONFIG_SERIAL_TEXT_DEBUG
#include <linux/serialP.h>
#include <linux/serial_reg.h>
#include <asm/serial.h>
static struct serial_state rs_table[RS_TABLE_SIZE] = {
SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
};
static void
mcpn765_progress(char *s, unsigned short hex)
{
volatile char c;
volatile unsigned long com_port;
u16 shift;
com_port = rs_table[0].port;
shift = rs_table[0].iomem_reg_shift;
while ((c = *s++) != 0) {
while ((*((volatile unsigned char *)com_port +
(UART_LSR << shift)) & UART_LSR_THRE) == 0)
;
*(volatile unsigned char *)com_port = c;
if (c == '\n') {
while ((*((volatile unsigned char *)com_port +
(UART_LSR << shift)) & UART_LSR_THRE) == 0)
;
*(volatile unsigned char *)com_port = '\r';
}
}
}
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
/* Map in board regs, etc. */
mcpn765_set_bat();
isa_mem_base = MCPN765_ISA_MEM_BASE;
pci_dram_offset = MCPN765_PCI_DRAM_OFFSET;
ISA_DMA_THRESHOLD = 0x00ffffff;
DMA_MODE_READ = 0x44;
DMA_MODE_WRITE = 0x48;
ppc_md.setup_arch = mcpn765_setup_arch;
ppc_md.show_cpuinfo = mcpn765_show_cpuinfo;
ppc_md.irq_cannonicalize = mcpn765_irq_cannonicalize;
ppc_md.init_IRQ = mcpn765_init_IRQ;
ppc_md.get_irq = openpic_get_irq;
ppc_md.init = mcpn765_init2;
ppc_md.restart = mcpn765_restart;
ppc_md.power_off = mcpn765_power_off;
ppc_md.halt = mcpn765_halt;
ppc_md.find_end_of_memory = mcpn765_find_end_of_memory;
ppc_md.setup_io_mappings = mcpn765_map_io;
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.calibrate_decr = todc_calibrate_decr;
ppc_md.nvram_read_val = todc_m48txx_read_val;
ppc_md.nvram_write_val = todc_m48txx_write_val;
ppc_md.heartbeat = NULL;
ppc_md.heartbeat_reset = 0;
ppc_md.heartbeat_count = 0;
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = mcpn765_progress;
#else /* !CONFIG_SERIAL_TEXT_DEBUG */
ppc_md.progress = NULL;
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
ppc_ide_md.default_irq = mcpn765_ide_default_irq;
ppc_ide_md.default_io_base = mcpn765_ide_default_io_base;
ppc_ide_md.ide_init_hwif = mcpn765_ide_init_hwif_ports;
#endif
return;
}
--- NEW FILE: menf1_setup.c ---
/*
* arch/ppc/platforms/menf1_setup.c
* Board setup routines for MEN F1
*
* Author: Matt Porter <mp...@mv...>
*
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/major.h>
#include <linux/blk.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/irq.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/time.h>
#include <asm/i8259.h>
#include <asm/mpc10x.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#include "menf1.h"
extern void menf1_find_bridges(void);
extern unsigned long loops_per_jiffy;
/* Dummy variable to satisfy mpc10x_common.o */
void *OpenPIC_Addr;
static int
menf1_show_cpuinfo(struct seq_file *m)
{
seq_printf(m, "machine\t\t: MEN F1\n");
return 0;
}
static void __init
menf1_setup_arch(void)
{
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Lookup PCI host bridges */
menf1_find_bridges();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA2;
#endif
printk("MEN F1 port (C) 2001 MontaVista Software, Inc. (so...@mv...)\n");
}
static void
menf1_restart(char *cmd)
{
int picr1;
struct pci_dev *pdev;
local_irq_disable();
/*
* Firmware doesn't like re-entry using Map B (CHRP), so make sure the
* PCI bridge is using MAP A (PReP).
*/
pdev = pci_find_slot(0, PCI_DEVFN(0,0));
while(pdev == NULL); /* paranoia */
pci_read_config_dword(pdev, MPC10X_CFG_PICR1_REG, &picr1);
picr1 = (picr1 & ~MPC10X_CFG_PICR1_ADDR_MAP_MASK) |
MPC10X_CFG_PICR1_ADDR_MAP_A;
pci_write_config_dword(pdev, MPC10X_CFG_PICR1_REG, picr1);
asm volatile("sync");
/* SRR0 has system reset vector, SRR1 has default MSR value */
/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
__asm__ __volatile__
("\n\
lis 3,0xfff0
ori 3,3,0x0100
mtspr 26,3
li 3,0
mtspr 27,3
rfi
");
while(1);
}
static void
menf1_halt(void)
{
local_irq_disable();
while (1);
}
static void
menf1_power_off(void)
{
menf1_halt();
}
static void __init
menf1_init_IRQ(void)
{
int i;
for ( i = 0 ; i < NUM_8259_INTERRUPTS ; i++ )
irq_desc[i].handler = &i8259_pic;
i8259_init(NULL);
}
static int menf1_get_irq(struct pt_regs *regs)
{
return i8259_poll();
}
/*
* Set BAT 3 to map 0xF0000000.
*/
static __inline__ void
menf1_set_bat(void)
{
static int mapping_set = 0;
if (!mapping_set)
{
/* wait for all outstanding memory accesses to complete */
mb();
/* setup DBATs */
mtspr(DBAT3U, 0xf0001ffe);
mtspr(DBAT3L, 0xf000002a);
/* wait for updates */
mb();
mapping_set = 1;
}
return;
}
static unsigned long __init
menf1_find_end_of_memory(void)
{
/* Cover the I/O with a BAT */
menf1_set_bat();
/* Read the memory size from the MPC107 SMC */
return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
}
static void __init
menf1_map_io(void)
{
io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
}
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
/* IDE functions */
static void __init
menf1_ide_init_hwif_ports (hw_regs_t *hw, ide_ioreg_t data_port,
ide_ioreg_t ctrl_port, int *irq)
{
ide_ioreg_t reg = data_port;
int i = 8;
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw->io_ports[i] = reg;
reg += 1;
}
if (ctrl_port)
hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
else
hw->io_ports[IDE_CONTROL_OFFSET] =
hw->io_ports[IDE_DATA_OFFSET] + 0x206;
if (irq != NULL)
*irq = 0;
}
static int
menf1_ide_default_irq(ide_ioreg_t base)
{
if (base == MENF1_IDE0_BASE_ADDR)
return 14;
else if (base == MENF1_IDE1_BASE_ADDR)
return 15;
else
return 0;
}
static ide_ioreg_t
menf1_ide_default_io_base(int index)
{
if (index == 0)
return MENF1_IDE0_BASE_ADDR;
else if (index == 1)
return MENF1_IDE1_BASE_ADDR;
else
return 0;
}
#endif
TODC_ALLOC();
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
ppc_md.setup_arch = menf1_setup_arch;
ppc_md.show_cpuinfo = menf1_show_cpuinfo;
ppc_md.init_IRQ = menf1_init_IRQ;
ppc_md.get_irq = menf1_get_irq;
ppc_md.find_end_of_memory = menf1_find_end_of_memory;
ppc_md.setup_io_mappings = menf1_map_io;
ppc_md.restart = menf1_restart;
ppc_md.power_off = menf1_power_off;
ppc_md.halt = menf1_halt;
TODC_INIT(TODC_TYPE_MK48T59,
MENF1_NVRAM_AS0,
MENF1_NVRAM_AS1,
MENF1_NVRAM_DATA,
7);
ppc_md.time_init = todc_time_init;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.calibrate_decr = todc_calibrate_decr;
ppc_md.nvram_read_val = todc_m48txx_read_val;
ppc_md.nvram_write_val = todc_m48txx_write_val;
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
ppc_ide_md.default_io_base = menf1_ide_default_io_base;
ppc_ide_md.default_irq = menf1_ide_default_irq;
ppc_ide_md.ide_init_hwif = menf1_ide_init_hwif_ports;
#endif
}
--- NEW FILE: mvme5100_setup.c ---
/*
* arch/ppc/platforms/mvme5100_setup.c
*
* Board setup routines for the Motorola MVME5100.
*
* Author: Matt Porter <mp...@mv...>
*
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/blk.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/ide.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/time.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/prom.h>
#include <asm/smp.h>
#include <asm/open_pic.h>
#include <asm/i8259.h>
#include <platforms/mvme5100.h>
#include <asm/todc.h>
#include <asm/pci-bridge.h>
#include <asm/bootinfo.h>
#include <asm/pplus.h>
extern char cmd_line[];
static u_char mvme5100_openpic_initsenses[] __initdata = {
0, /* 16: i8259 cascade (active high) */
1, /* 17: TL16C550 UART 1,2 */
1, /* 18: Enet 1 (front panel or P2) */
1, /* 19: Hawk Watchdog 1,2 */
1, /* 20: DS1621 thermal alarm */
1, /* 21: Universe II LINT0# */
1, /* 22: Universe II LINT1# */
1, /* 23: Universe II LINT2# */
1, /* 24: Universe II LINT3# */
1, /* 25: PMC1 INTA#, PMC2 INTB# */
1, /* 26: PMC1 INTB#, PMC2 INTC# */
1, /* 27: PMC1 INTC#, PMC2 INTD# */
1, /* 28: PMC1 INTD#, PMC2 INTA# */
1, /* 29: Enet 2 (front panel) */
1, /* 30: Abort Switch */
1, /* 31: RTC Alarm */
};
static void __init
mvme5100_setup_arch(void)
{
if ( ppc_md.progress )
ppc_md.progress("mvme5100_setup_arch: enter", 0);
loops_per_jiffy = 50000000 / HZ;
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_SDA2;
#endif
if ( ppc_md.progress )
ppc_md.progress("mvme5100_setup_arch: find_bridges", 0);
/* Setup PCI host bridge */
mvme5100_setup_bridge();
/* Find and map our OpenPIC */
pplus_mpic_init(MVME5100_PCI_MEM_OFFSET);
OpenPIC_InitSenses = mvme5100_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(mvme5100_openpic_initsenses);
printk("MVME5100 port (C) 2001 MontaVista Software, Inc. (so...@mv...)\n");
if ( ppc_md.progress )
ppc_md.progress("mvme5100_setup_arch: exit", 0);
return;
}
static void __init
mvme5100_init2(void)
{
#ifdef CONFIG_MVME5100_IPMC761_PRESENT
request_region(0x00,0x20,"dma1");
request_region(0x20,0x20,"pic1");
request_region(0x40,0x20,"timer");
request_region(0x80,0x10,"dma page reg");
request_region(0xa0,0x20,"pic2");
request_region(0xc0,0x20,"dma2");
#endif
return;
}
/*
* Interrupt setup and service.
* Have MPIC on HAWK and cascaded 8259s on Winbond cascaded to MPIC.
*/
static void __init
mvme5100_init_IRQ(void)
{
#ifdef CONFIG_MVME5100_IPMC761_PRESENT
int i;
#endif
if ( ppc_md.progress )
ppc_md.progress("init_irq: enter", 0);
#ifdef CONFIG_MVME5100_IPMC761_PRESENT
openpic_init(1, NUM_8259_INTERRUPTS, NULL, -1);
for(i=0; i < NUM_8259_INTERRUPTS; i++)
irq_desc[i].handler = &i8259_pic;
i8259_init(NULL);
#else
openpic_init(1, 0, NULL, -1);
#endif
if ( ppc_md.progress )
ppc_md.progress("init_irq: exit", 0);
return;
}
/*
* Set BAT 3 to map 0xf0000000 to end of physical memory space.
*/
static __inline__ void
mvme5100_set_bat(void)
{
unsigned long bat3u, bat3l;
static int mapping_set = 0;
if (!mapping_set) {
__asm__ __volatile__(
" lis %0,0xf000\n \
ori %1,%0,0x002a\n \
ori %0,%0,0x1ffe\n \
mtspr 0x21e,%0\n \
mtspr 0x21f,%1\n \
isync\n \
sync "
: "=r" (bat3u), "=r" (bat3l));
mapping_set = 1;
}
return;
}
static unsigned long __init
mvme5100_find_end_of_memory(void)
{
mvme5100_set_bat();
return pplus_get_mem_size(MVME5100_HAWK_SMC_BASE);
}
static void __init
mvme5100_map_io(void)
{
io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
ioremap_base = 0xfe000000;
}
static void
mvme5100_reset_board(void)
{
local_irq_disable();
/* Set exception prefix high - to the firmware */
_nmask_and_or_msr(0, MSR_IP);
out_8((u_char *)MVME5100_BOARD_MODRST_REG, 0x01);
return;
}
static void
mvme5100_restart(char *cmd)
{
volatile ulong i = 10000000;
mvme5100_reset_board();
while (i-- > 0);
panic("restart failed\n");
}
static void
mvme5100_halt(void)
{
local_irq_disable();
while (1);
}
static void
mvme5100_power_off(void)
{
mvme5100_halt();
}
static int
mvme5100_show_cpuinfo(struct seq_file *m)
{
seq_printf(m, "vendor\t\t: Motorola\n");
seq_printf(m, "machine\t\t: MVME5100\n");
return 0;
}
TODC_ALLOC();
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
isa_io_base = MVME5100_ISA_IO_BASE;
isa_mem_base = MVME5100_ISA_MEM_BASE;
pci_dram_offset = MVME5100_PCI_DRAM_OFFSET;
ppc_md.setup_arch = mvme5100_setup_arch;
ppc_md.show_cpuinfo = mvme5100_show_cpuinfo;
ppc_md.init_IRQ = mvme5100_init_IRQ;
ppc_md.get_irq = openpic_get_irq;
ppc_md.init = mvme5100_init2;
ppc_md.restart = mvme5100_restart;
ppc_md.power_off = mvme5100_power_off;
ppc_md.halt = mvme5100_halt;
ppc_md.find_end_of_memory = mvme5100_find_end_of_memory;
ppc_md.setup_io_mappings = mvme5100_map_io;
TODC_INIT(TODC_TYPE_MK48T37,
MVME5100_NVRAM_AS0,
MVME5100_NVRAM_AS1,
MVME5100_NVRAM_DATA,
8);
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.calibrate_decr = todc_calibrate_decr;
ppc_md.nvram_read_val = todc_m48txx_read_val;
ppc_md.nvram_write_val = todc_m48txx_write_val;
ppc_md.progress = NULL;
}
--- NEW FILE: pcore_setup.c ---
/*
* arch/ppc/platforms/pcore_setup.c
*
* Setup routines for Force PCORE boards
*
* Author: Matt Porter <mp...@mv...>
*
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/major.h>
#include <linux/blk.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/seq_file.h>
#include <linux/ide.h>
#include <linux/root_dev.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/time.h>
#include <asm/i8259.h>
#include <asm/mpc10x.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#include "pcore.h"
extern int pcore_find_bridges(void);
extern unsigned long loops_per_jiffy;
static int board_type;
/* Dummy variable to satisfy mpc10x_common.o */
void *OpenPIC_Addr;
static int
pcore_show_cpuinfo(struct seq_file *m)
{
seq_printf(m, "vendor\t\t: Force Computers\n");
if (board_type == PCORE_TYPE_6750)
seq_printf(m, "machine\t\t: PowerCore 6750\n");
else /* PCORE_TYPE_680 */
seq_printf(m, "machine\t\t: PowerCore 680\n");
seq_printf(m, "L2\t\t: " );
if (board_type == PCORE_TYPE_6750)
switch (readb(PCORE_DCCR_REG) & PCORE_DCCR_L2_MASK)
{
case PCORE_DCCR_L2_0KB:
seq_printf(m, "nocache");
break;
case PCORE_DCCR_L2_256KB:
seq_printf(m, "256KB");
break;
case PCORE_DCCR_L2_1MB:
seq_printf(m, "1MB");
break;
case PCORE_DCCR_L2_512KB:
seq_printf(m, "512KB");
break;
default:
seq_printf(m, "error");
break;
}
else /* PCORE_TYPE_680 */
switch (readb(PCORE_DCCR_REG) & PCORE_DCCR_L2_MASK)
{
case PCORE_DCCR_L2_2MB:
seq_printf(m, "2MB");
break;
case PCORE_DCCR_L2_256KB:
seq_printf(m, "reserved");
break;
case PCORE_DCCR_L2_1MB:
seq_printf(m, "1MB");
break;
case PCORE_DCCR_L2_512KB:
seq_printf(m, "512KB");
break;
default:
seq_printf(m, "error");
break;
}
seq_printf(m, "\n");
return 0;
}
static void __init
pcore_setup_arch(void)
{
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Lookup PCI host bridges */
board_type = pcore_find_bridges();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_SDA2;
#endif
printk("Force PCore port (C) 2001 MontaVista Software, Inc. (so...@mv...)\n");
}
static void
pcore_restart(char *cmd)
{
local_irq_disable();
/* Hard reset */
writeb(0x11, 0xfe000332);
while(1);
}
static void
pcore_halt(void)
{
local_irq_disable();
/* Turn off user LEDs */
writeb(0x00, 0xfe000300);
while (1);
}
static void
pcore_power_off(void)
{
pcore_halt();
}
static void __init
pcore_init_IRQ(void)
{
int i;
for ( i = 0 ; i < 16 ; i++ )
irq_desc[i].handler = &i8259_pic;
i8259_init(0);
}
/*
* Set BAT 3 to map 0xf0000000 to end of physical memory space.
*/
static __inline__ void
pcore_set_bat(void)
{
unsigned long bat3u, bat3l;
__asm__ __volatile__(
" lis %0,0xf000\n \
ori %1,%0,0x002a\n \
ori %0,%0,0x1ffe\n \
mtspr 0x21e,%0\n \
mtspr 0x21f,%1\n \
isync\n \
sync "
: "=r" (bat3u), "=r" (bat3l));
}
static unsigned long __init
pcore_find_end_of_memory(void)
{
/* Cover I/O space with a BAT */
/* yuck, better hope your ram size is a power of 2 -- paulus */
pcore_set_bat();
return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
}
static void __init
pcore_map_io(void)
{
io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
}
TODC_ALLOC();
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
ppc_md.setup_arch = pcore_setup_arch;
ppc_md.show_cpuinfo = pcore_show_cpuinfo;
ppc_md.init_IRQ = pcore_init_IRQ;
ppc_md.get_irq = i8259_irq;
ppc_md.find_end_of_memory = pcore_find_end_of_memory;
ppc_md.setup_io_mappings = pcore_map_io;
ppc_md.restart = pcore_restart;
ppc_md.power_off = pcore_power_off;
ppc_md.halt = pcore_halt;
TODC_INIT(TODC_TYPE_MK48T59,
PCORE_NVRAM_AS0,
PCORE_NVRAM_AS1,
PCORE_NVRAM_DATA,
8);
ppc_md.time_init = todc_time_init;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.calibrate_decr = todc_calibrate_decr;
ppc_md.nvram_read_val = todc_m48txx_read_val;
ppc_md.nvram_write_val = todc_m48txx_write_val;
}
--- NEW FILE: prpmc750_setup.c ---
/*
* arch/ppc/platforms/prpmc750_setup.c
*
* Board setup routines for Motorola PrPMC750
*
* Author: Matt Porter <mp...@mv...>
*
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/major.h>
#include <linux/blk.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/seq_file.h>
#include <linux/ide.h>
#include <linux/root_dev.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/time.h>
#include <platforms/prpmc750.h>
#include <asm/open_pic.h>
#include <asm/bootinfo.h>
#include <asm/pplus.h>
extern void prpmc750_find_bridges(void);
extern int mpic_init(void);
extern unsigned long loops_per_jiffy;
static u_char prpmc750_openpic_initsenses[] __initdata =
{
1, /* PRPMC750_INT_HOSTINT0 */
1, /* PRPMC750_INT_UART */
1, /* PRPMC750_INT_DEBUGINT */
1, /* PRPMC750_INT_HAWK_WDT */
1, /* PRPMC750_INT_UNUSED */
1, /* PRPMC750_INT_ABORT */
1, /* PRPMC750_INT_HOSTINT1 */
1, /* PRPMC750_INT_HOSTINT2 */
1, /* PRPMC750_INT_HOSTINT3 */
1, /* PRPMC750_INT_PMC_INTA */
1, /* PRPMC750_INT_PMC_INTB */
1, /* PRPMC750_INT_PMC_INTC */
1, /* PRPMC750_INT_PMC_INTD */
1, /* PRPMC750_INT_UNUSED */
1, /* PRPMC750_INT_UNUSED */
1, /* PRPMC750_INT_UNUSED */
};
static int
prpmc750_show_cpuinfo(struct seq_file *m)
{
seq_printf(m, "machine\t\t: PrPMC750\n");
return 0;
}
static void __init
prpmc750_setup_arch(void)
{
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Lookup PCI host bridges */
prpmc750_find_bridges();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_SDA2;
#endif
/* Find and map our OpenPIC */
pplus_mpic_init(PRPMC750_PCI_MEM_OFFSET);
OpenPIC_InitSenses = prpmc750_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(prpmc750_openpic_initsenses);
printk("PrPMC750 port (C) 2001 MontaVista Software, Inc. (so...@mv...)\n");
}
/*
* Compute the PrPMC750's bus speed using the baud clock as a
* reference.
*/
static unsigned long __init
prpmc750_get_bus_speed(void)
{
unsigned long tbl_start, tbl_end;
unsigned long current_state, old_state, bus_speed;
unsigned char lcr, dll, dlm;
int baud_divisor, count;
/* Read the UART's baud clock divisor */
lcr = readb(PRPMC750_SERIAL_0_LCR);
writeb(lcr | UART_LCR_DLAB, PRPMC750_SERIAL_0_LCR);
dll = readb(PRPMC750_SERIAL_0_DLL);
dlm = readb(PRPMC750_SERIAL_0_DLM);
writeb(lcr & ~UART_LCR_DLAB, PRPMC750_SERIAL_0_LCR);
baud_divisor = (dlm << 8) | dll;
/*
* Use the baud clock divisor and base baud clock
* to determine the baud rate and use that as
* the number of baud clock edges we use for
* the time base sample. Make it half the baud
* rate.
*/
count = PRPMC750_BASE_BAUD / (baud_divisor * 16);
/* Find the first edge of the baud clock */
old_state = readb(PRPMC750_STATUS_REG) & PRPMC750_BAUDOUT_MASK;
do {
current_state = readb(PRPMC750_STATUS_REG) &
PRPMC750_BAUDOUT_MASK;
} while(old_state == current_state);
old_state = current_state;
/* Get the starting time base value */
tbl_start = get_tbl();
/*
* Loop until we have found a number of edges equal
* to half the count (half the baud rate)
*/
do {
do {
current_state = readb(PRPMC750_STATUS_REG) &
PRPMC750_BAUDOUT_MASK;
} while(old_state == current_state);
old_state = current_state;
} while (--count);
/* Get the ending time base value */
tbl_end = get_tbl();
/* Compute bus speed */
bus_speed = (tbl_end-tbl_start)*128;
return bus_speed;
}
static void __init
prpmc750_calibrate_decr(void)
{
unsigned long freq;
int divisor = 4;
freq = prpmc750_get_bus_speed();
tb_ticks_per_jiffy = freq / (HZ * divisor);
tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
}
static void
prpmc750_restart(char *cmd)
{
local_irq_disable();
writeb(PRPMC750_MODRST_MASK, PRPMC750_MODRST_REG);
while(1);
}
static void
prpmc750_halt(void)
{
local_irq_disable();
while (1);
}
static void
prpmc750_power_off(void)
{
prpmc750_halt();
}
/* Resolves the open_pic.c build without including i8259.c */
int i8259_poll(void)
{
return 0;
}
static void __init
prpmc750_init_IRQ(void)
{
openpic_init(1, 0, 0, -1);
}
/*
* Set BAT 3 to map 0xf0000000 to end of physical memory space.
*/
static __inline__ void
prpmc750_set_bat(void)
{
unsigned long bat3u, bat3l;
static int mapping_set = 0;
if (!mapping_set)
{
__asm__ __volatile__(
" lis %0,0xf000\n \
ori %1,%0,0x002a\n \
ori %0,%0,0x1ffe\n \
mtspr 0x21e,%0\n \
mtspr 0x21f,%1\n \
isync\n \
sync "
: "=r" (bat3u), "=r" (bat3l));
mapping_set = 1;
}
return;
}
/*
* We need to read the Falcon/Hawk memory controller
* to properly determine this value
*/
static unsigned long __init
prpmc750_find_end_of_memory(void)
{
/* Cover the Hawk registers with a BAT */
prpmc750_set_bat();
/* Read the memory size from the Hawk SMC */
return pplus_get_mem_size(PRPMC750_HAWK_SMC_BASE);
}
static void __init
prpmc750_map_io(void)
{
io_block_mapping(0x80000000, 0x80000000, 0x10000000, _PAGE_IO);
io_block_mapping(0xf0000000, 0xc0000000, 0x08000000, _PAGE_IO);
io_block_mapping(0xf8000000, 0xf8000000, 0x08000000, _PAGE_IO);
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
isa_io_base = PRPMC750_ISA_IO_BASE;
isa_mem_base = PRPMC750_ISA_MEM_BASE;
pci_dram_offset = PRPMC750_SYS_MEM_BASE;
ppc_md.setup_arch = prpmc750_setup_arch;
ppc_md.show_cpuinfo = prpmc750_show_cpuinfo;
ppc_md.init_IRQ = prpmc750_init_IRQ;
ppc_md.get_irq = openpic_get_irq;
ppc_md.find_end_of_memory = prpmc750_find_end_of_memory;
ppc_md.setup_io_mappings = prpmc750_map_io;
ppc_md.restart = prpmc750_restart;
ppc_md.power_off = prpmc750_power_off;
ppc_md.halt = prpmc750_halt;
/* PrPMC750 has no timekeeper part */
ppc_md.time_init = NULL;
ppc_md.get_rtc_time = NULL;
ppc_md.set_rtc_time = NULL;
ppc_md.calibrate_decr = prpmc750_calibrate_decr;
}
--- NEW FILE: prpmc800_setup.c ---
/*
*
* Author: Dale Farnsworth <dal...@mv...>
*
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/major.h>
#include <linux/blk.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/seq_file.h>
#include <linux/ide.h>
#include <linux/root_dev.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/time.h>
#include <platforms/prpmc800.h>
#include <asm/open_pic.h>
#include <asm/bootinfo.h>
#include <asm/harrier.h>
#define HARRIER_REVI_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_REVI_OFF)
#define HARRIER_UCTL_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_UCTL_OFF)
#define HARRIER_MISC_CSR_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_MISC_CSR_OFF)
#define HARRIER_IFEVP_REG (PRPMC800_HARRIER_MPIC_BASE+HARRIER_MPIC_IFEVP_OFF)
#define HARRIER_IFEDE_REG (PRPMC800_HARRIER_MPIC_BASE+HARRIER_MPIC_IFEDE_OFF)
#define HARRIER_FEEN_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_FEEN_OFF)
#define HARRIER_FEMA_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_FEMA_OFF)
extern void prpmc800_find_bridges(void);
extern int mpic_init(void);
extern unsigned long loops_per_jiffy;
static u_char prpmc800_openpic_initsenses[] __initdata =
{
1, /* PRPMC800_INT_HOSTINT0 */
1, /* PRPMC800_INT_UNUSED */
1, /* PRPMC800_INT_DEBUGINT */
1, /* PRPMC800_INT_HARRIER_WDT */
1, /* PRPMC800_INT_UNUSED */
1, /* PRPMC800_INT_UNUSED */
1, /* PRPMC800_INT_HOSTINT1 */
1, /* PRPMC800_INT_HOSTINT2 */
1, /* PRPMC800_INT_HOSTINT3 */
1, /* PRPMC800_INT_PMC_INTA */
1, /* PRPMC800_INT_PMC_INTB */
1, /* PRPMC800_INT_PMC_INTC */
1, /* PRPMC800_INT_PMC_INTD */
1, /* PRPMC800_INT_UNUSED */
1, /* PRPMC800_INT_UNUSED */
1, /* PRPMC800_INT_UNUSED */
1, /* PRPMC800_INT_HARRIER_INT (UARTS, ABORT, DMA) */
};
static int
prpmc800_show_cpuinfo(struct seq_file *m)
{
seq_printf(m, "machine\t\t: PrPMC800\n");
return 0;
}
static void __init
prpmc800_setup_arch(void)
{
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Lookup PCI host bridges */
prpmc800_find_bridges();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_SDA2;
#endif
OpenPIC_InitSenses = prpmc800_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(prpmc800_openpic_initsenses);
printk("PrPMC800 port (C) 2001 MontaVista Software, Inc. (so...@mv...)\n");
}
/*
* Compute the PrPMC800's tbl frequency using the baud clock as a reference.
*/
static void __init
prpmc800_calibrate_decr(void)
{
unsigned long tbl_start, tbl_end;
unsigned long current_state, old_state, tb_ticks_per_second;
unsigned int count;
unsigned int harrier_revision;
harrier_revision = readb(HARRIER_REVI_REG);
if (harrier_revision < 2) {
/* XTAL64 was broken in harrier revision 1 */
printk("time_init: Harrier revision %d, assuming 100 Mhz bus\n",
harrier_revision);
tb_ticks_per_second = 100000000/4;
tb_ticks_per_jiffy = tb_ticks_per_second / HZ;
tb_to_us = mulhwu_scale_factor(tb_ticks_per_second, 1000000);
return;
}
/*
* The XTAL64 bit oscillates at the 1/64 the base baud clock
* Set count to XTAL64 cycles per second. Since we'll count
* half-cycles, we'll reach the count in half a second.
*/
count = PRPMC800_BASE_BAUD / 64;
/* Find the first edge of the baud clock */
old_state = readb(HARRIER_UCTL_REG) & HARRIER_XTAL64_MASK;
do {
current_state = readb(HARRIER_UCTL_REG) &
HARRIER_XTAL64_MASK;
} while(old_state == current_state);
old_state = current_state;
/* Get the starting time base value */
tbl_start = get_tbl();
/*
* Loop until we have found a number of edges (half-cycles)
* equal to the count (half a second)
*/
do {
do {
current_state = readb(HARRIER_UCTL_REG) &
HARRIER_XTAL64_MASK;
} while(old_state == current_state);
old_state = current_state;
} while (--count);
/* Get the ending time base value */
tbl_end = get_tbl();
/* We only counted for half a second, so double to get ticks/second */
tb_ticks_per_second = (tbl_end - tbl_start) * 2;
tb_ticks_per_jiffy = tb_ticks_per_second / HZ;
tb_to_us = mulhwu_scale_factor(tb_ticks_per_second, 1000000);
}
static void
prpmc800_restart(char *cmd)
{
local_irq_disable();
writeb(HARRIER_RSTOUT_MASK, HARRIER_MISC_CSR_REG);
while(1);
}
static void
prpmc800_halt(void)
{
local_irq_disable();
while (1);
}
static void
prpmc800_power_off(void)
{
prpmc800_halt();
}
/* Resolves the open_pic.c build without including i8259.c */
int i8259_poll()
{
return 0;
}
static void __init
prpmc800_init_IRQ(void)
{
openpic_init(1, 0, 0, -1);
#define PRIORITY 15
#define VECTOR 16
#define PROCESSOR 0
/* initialize the harrier's internal interrupt priority 15, irq 1 */
out_be32((u32 *)HARRIER_IFEVP_REG, (PRIORITY<<16) | VECTOR);
out_be32((u32 *)HARRIER_IFEDE_REG, (1<<PROCESSOR));
/* enable functional exceptions for uarts and abort */
out_8((u8 *)HARRIER_FEEN_REG, (HARRIER_FE_UA0|HARRIER_FE_UA1));
out_8((u8 *)HARRIER_FEMA_REG, ~(HARRIER_FE_UA0|HARRIER_FE_UA1));
}
/*
* Set BAT 3 to map 0xf0000000 to end of physical memory space.
*/
static __inline__ void
prpmc800_set_bat(void)
{
unsigned long bat3u, bat3l;
static int mapping_set = 0;
if (!mapping_set)
{
__asm__ __volatile__(
" lis %0,0xf000\n \
ori %1,%0,0x002a\n \
ori %0,%0,0x1ffe\n \
mtspr 0x21e,%0\n \
mtspr 0x21f,%1\n \
isync\n \
sync "
: "=r" (bat3u), "=r" (bat3l));
mapping_set = 1;
}
return;
}
#ifdef CONFIG_SERIAL_TEXT_DEBUG
#include <linux/serial.h>
#include <linux/serialP.h>
#include <linux/serial_reg.h>
#include <asm/serial.h>
static struct serial_state rs_table[RS_TABLE_SIZE] = {
SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
};
void
prpmc800_progress(char *s, unsigned short hex)
{
volatile char c;
volatile unsigned char *com_port;
volatile unsigned char *com_port_lsr;
com_port = (volatile unsigned char *) rs_table[0].port;
com_port_lsr = com_port + UART_LSR;
while ((c = *s++) != 0) {
while ((*com_port_lsr & UART_LSR_THRE) == 0)
;
*com_port = c;
if (c == '\n') {
while ((*com_port_lsr & UART_LSR_THRE) == 0)
;
*com_port = '\r';
}
}
}
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
/*
* We need to read the Harrier memory controller
* to properly determine this value
*/
static unsigned long __init
prpmc800_find_end_of_memory(void)
{
/* Cover the harrier registers with a BAT */
prpmc800_set_bat();
/* Read the memory size from the Harrier XCSR */
return harrier_get_mem_size(PRPMC800_HARRIER_XCSR_BASE);
}
static void __init
prpmc800_map_io(void)
{
io_block_mapping(0x80000000, 0x80000000, 0x10000000, _PAGE_IO);
io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
prpmc800_set_bat();
isa_io_base = PRPMC800_ISA_IO_BASE;
isa_mem_base = PRPMC800_ISA_MEM_BASE;
pci_dram_offset = PRPMC800_PCI_DRAM_OFFSET;
ppc_md.setup_arch = prpmc800_setup_arch;
ppc_md.show_cpuinfo = prpmc800_show_cpuinfo;
ppc_md.init_IRQ = prpmc800_init_IRQ;
ppc_md.get_irq = openpic_get_irq;
ppc_md.find_end_of_memory = prpmc800_find_end_of_memory;
ppc_md.setup_io_mappings = prpmc800_map_io;
ppc_md.restart = prpmc800_restart;
ppc_md.power_off = prpmc800_power_off;
ppc_md.halt = prpmc800_halt;
/* PrPMC800 has no timekeeper part */
ppc_md.time_init = NULL;
ppc_md.get_rtc_time = NULL;
ppc_md.set_rtc_time = NULL;
ppc_md.calibrate_decr = prpmc800_calibrate_decr;
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = prpmc800_progress;
#else /* !CONFIG_SERIAL_TEXT_DEBUG */
ppc_md.progress = NULL;
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
}
Index: chrp_setup.c
===================================================================
RCS file: /cvsroot/linuxconsole/ruby/linux/arch/ppc/platforms/chrp_setup.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- chrp_setup.c 23 Jul 2002 19:18:48 -0000 1.7
+++ chrp_setup.c 23 Nov 2002 00:55:48 -0000 1.8
@@ -1,7 +1,4 @@
/*
- * BK Id: %F% %I% %G% %U% %#%
- */
-/*
* arch/ppc/platforms/setup.c
*
* Copyright (C) 1995 Linus Torvalds
@@ -36,7 +33,6 @@
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/irq.h>
-#include <linux/console.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
@@ -68,7 +64,6 @@
void btext_progress(char *, unsigned short);
extern unsigned long pmac_find_end_of_memory(void);
-extern void select_adb_keyboard(void);
extern int of_show_percpuinfo(struct seq_file *, int);
extern kdev_t boot_dev;
@@ -430,22 +425,6 @@
...
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