Hi all,
I am writing a driver for the above mentioned controller and am =
experiencing some difficulties making it receive and transmit.
Using a protocol analyzer (Yokogawa9000) I can see that the link comes =
up and selfIDs get assigned, but some things seem not quite right:
- even though the selfId count shows some quadlets put into the selfId =
DMA buffer, there is nothing written to the buffer (that is it remains =
all zeros after selfId phase is over)
- when there is a bus reset issued by the analyzer, the appropriate =
receive context shows the event (code 9), but the context descriptor =
residue size/status field don't get updated.
This all makes me suspect that the chip doesn't access the addresses it =
is supposed to be using, but there is no way I can hook up a logic or =
PCI analyzer to the system to see what's going on. I wonder if these =
symptoms ring any other bell to anyone. If someone can share a logic =
analyzer trace of the chip initialization - I would be forvever grateful =
to get it.
Thanks in advance,
Vadim Bendebury
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