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[LV-kern-commit] CVS: kernel-2.4/arch/i386/kernel dmi_scan.c,1.2,1.3 pci-pc.c,1.2,1.3 setup.c,1.2,1.3 smp.c,1.2,1.3 smpboot.c,1.2,1.3
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From: Dave A. <ai...@us...> - 2003-06-10 01:15:24
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Update of /cvsroot/linux-vax/kernel-2.4/arch/i386/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv7538/arch/i386/kernel
Modified Files:
dmi_scan.c pci-pc.c setup.c smp.c smpboot.c
Log Message:
DA: sync with Marcelo 2.4.17
Index: dmi_scan.c
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/arch/i386/kernel/dmi_scan.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -r1.2 -r1.3
--- dmi_scan.c 10 Apr 2002 14:23:20 -0000 1.2
+++ dmi_scan.c 10 Jun 2003 01:13:14 -0000 1.3
@@ -523,6 +523,12 @@
MATCH(DMI_BIOS_DATE, "05/11/00"), NO_MATCH
} },
+ { swab_apm_power_in_minutes, "Sony VAIO", { /* Handle problems with APM on Sony Vaio PCG-Z600NE */
+ MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies LTD"),
+ MATCH(DMI_BIOS_VERSION, "WME01Z1"),
+ MATCH(DMI_BIOS_DATE, "08/11/00"), NO_MATCH
+ } },
+
{ swab_apm_power_in_minutes, "Sony VAIO", { /* Handle problems with APM on Sony Vaio PCG-Z505LS */
MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies LTD"),
MATCH(DMI_BIOS_VERSION, "R0203D0"),
@@ -562,6 +568,11 @@
{ broken_pirq, "l44GX Bios", { /* Bad $PIR */
MATCH(DMI_BIOS_VENDOR, "Intel Corporation"),
MATCH(DMI_BIOS_VERSION,"L440GX0.86B.0094.P10"),
+ NO_MATCH, NO_MATCH
+ } },
+ { broken_pirq, "l44GX Bios", { /* Bad $PIR */
+ MATCH(DMI_BIOS_VENDOR, "Intel Corporation"),
+ MATCH(DMI_BIOS_VERSION,"L440GX0.86B.0120.P12"),
NO_MATCH, NO_MATCH
} },
{ broken_pirq, "l44GX Bios", { /* Bad $PIR */
Index: pci-pc.c
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/arch/i386/kernel/pci-pc.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -r1.2 -r1.3
--- pci-pc.c 10 Apr 2002 14:23:21 -0000 1.2
+++ pci-pc.c 10 Jun 2003 01:13:14 -0000 1.3
@@ -30,7 +30,7 @@
* This interrupt-safe spinlock protects all accesses to PCI
* configuration space.
*/
-spinlock_t pci_config_lock = SPIN_LOCK_UNLOCKED;
+static spinlock_t pci_config_lock = SPIN_LOCK_UNLOCKED;
/*
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/arch/i386/kernel/setup.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -r1.2 -r1.3
--- setup.c 10 Apr 2002 14:23:21 -0000 1.2
+++ setup.c 10 Jun 2003 01:13:14 -0000 1.3
@@ -1280,9 +1280,27 @@
}
break;
- case 6: /* An Athlon/Duron. We can trust the BIOS probably */
- mcheck_init(c);
- break;
+ case 6: /* An Athlon/Duron */
+
+ /* Bit 15 of Athlon specific MSR 15, needs to be 0
+ * to enable SSE on Palomino/Morgan CPU's.
+ * If the BIOS didn't enable it already, enable it
+ * here.
+ */
+ if (c->x86_model == 6 || c->x86_model == 7) {
+ if (!test_bit(X86_FEATURE_XMM,
+ &c->x86_capability)) {
+ printk(KERN_INFO
+ "Enabling Disabled K7/SSE Support...\n");
+ rdmsr(MSR_K7_HWCR, l, h);
+ l &= ~0x00008000;
+ wrmsr(MSR_K7_HWCR, l, h);
+ set_bit(X86_FEATURE_XMM,
+ &c->x86_capability);
+ }
+ }
+ break;
+
}
display_cacheinfo(c);
@@ -1909,7 +1927,6 @@
c->x86_cache_size = (cc>>24)+(dd>>24);
}
sprintf( c->x86_model_id, "WinChip %s", name );
- mcheck_init(c);
break;
case 6:
@@ -2193,9 +2210,56 @@
if ( p )
strcpy(c->x86_model_id, p);
+
+#ifdef CONFIG_SMP
+ if (test_bit(X86_FEATURE_HT, &c->x86_capability)) {
+ extern int phys_proc_id[NR_CPUS];
+
+ u32 eax, ebx, ecx, edx;
+ int index_lsb, index_msb, tmp;
+ int initial_apic_id;
+ int cpu = smp_processor_id();
+
+ cpuid(1, &eax, &ebx, &ecx, &edx);
+ smp_num_siblings = (ebx & 0xff0000) >> 16;
+
+ if (smp_num_siblings == 1) {
+ printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
+ } else if (smp_num_siblings > 1 ) {
+ index_lsb = 0;
+ index_msb = 31;
+ /*
+ * At this point we only support two siblings per
+ * processor package.
+ */
+#define NR_SIBLINGS 2
+ if (smp_num_siblings != NR_SIBLINGS) {
+ printk(KERN_WARNING "CPU: Unsuppored number of the siblings %d", smp_num_siblings);
+ smp_num_siblings = 1;
+ goto too_many_siblings;
+ }
+ tmp = smp_num_siblings;
+ while ((tmp & 1) == 0) {
+ tmp >>=1 ;
+ index_lsb++;
+ }
+ tmp = smp_num_siblings;
+ while ((tmp & 0x80000000 ) == 0) {
+ tmp <<=1 ;
+ index_msb--;
+ }
+ if (index_lsb != index_msb )
+ index_msb++;
+ initial_apic_id = ebx >> 24 & 0xff;
+ phys_proc_id[cpu] = initial_apic_id >> index_msb;
- /* Enable MCA if available */
- mcheck_init(c);
+ printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
+ phys_proc_id[cpu]);
+ }
+
+ }
+too_many_siblings:
+#endif
}
void __init get_cpu_vendor(struct cpuinfo_x86 *c)
@@ -2575,7 +2639,7 @@
init_rise(c);
break;
}
-
+
printk(KERN_DEBUG "CPU: After vendor init, caps: %08x %08x %08x %08x\n",
c->x86_capability[0],
c->x86_capability[1],
@@ -2602,6 +2666,9 @@
/* Disable the PN if appropriate */
squash_the_stupid_serial_number(c);
+ /* Init Machine Check Exception if available. */
+ mcheck_init(c);
+
/* If the model name is still unset, do table lookup. */
if ( !c->x86_model_id[0] ) {
char *p;
@@ -2699,7 +2766,7 @@
"fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
"cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
"pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
- "fxsr", "sse", "sse2", "ss", NULL, "tm", "ia64", NULL,
+ "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
/* AMD-defined */
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
Index: smp.c
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/arch/i386/kernel/smp.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -r1.2 -r1.3
--- smp.c 10 Apr 2002 14:23:21 -0000 1.2
+++ smp.c 10 Jun 2003 01:13:14 -0000 1.3
@@ -17,6 +17,7 @@
#include <linux/smp_lock.h>
#include <linux/kernel_stat.h>
#include <linux/mc146818rtc.h>
+#include <linux/cache.h>
#include <asm/mtrr.h>
#include <asm/pgalloc.h>
@@ -102,7 +103,7 @@
*/
/* The 'big kernel lock' */
-spinlock_t kernel_flag = SPIN_LOCK_UNLOCKED;
+spinlock_t kernel_flag __cacheline_aligned_in_smp = SPIN_LOCK_UNLOCKED;
struct tlb_state cpu_tlbstate[NR_CPUS] = {[0 ... NR_CPUS-1] = { &init_mm, 0 }};
Index: smpboot.c
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/arch/i386/kernel/smpboot.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -r1.2 -r1.3
--- smpboot.c 10 Apr 2002 14:23:21 -0000 1.2
+++ smpboot.c 10 Jun 2003 01:13:14 -0000 1.3
@@ -56,6 +56,10 @@
/* Total count of live CPUs */
int smp_num_cpus = 1;
+/* Number of siblings per CPU package */
+int smp_num_siblings = 1;
+int __initdata phys_proc_id[NR_CPUS]; /* Package ID of each logical CPU */
+
/* Bitmask of currently online CPUs */
unsigned long cpu_online_map;
@@ -971,6 +975,8 @@
/* Where the IO area was mapped on multiquad, always 0 otherwise */
void *xquad_portio = NULL;
+int cpu_sibling_map[NR_CPUS] __cacheline_aligned;
+
void __init smp_boot_cpus(void)
{
int apicid, cpu, bit;
@@ -1162,6 +1168,34 @@
printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
Dprintk("Boot done.\n");
+ /*
+ * If Hyper-Threading is avaialble, construct cpu_sibling_map[], so
+ * that we can tell the sibling CPU efficiently.
+ */
+ if (test_bit(X86_FEATURE_HT, boot_cpu_data.x86_capability)
+ && smp_num_siblings > 1) {
+ for (cpu = 0; cpu < NR_CPUS; cpu++)
+ cpu_sibling_map[cpu] = NO_PROC_ID;
+
+ for (cpu = 0; cpu < smp_num_cpus; cpu++) {
+ int i;
+
+ for (i = 0; i < smp_num_cpus; i++) {
+ if (i == cpu)
+ continue;
+ if (phys_proc_id[cpu] == phys_proc_id[i]) {
+ cpu_sibling_map[cpu] = i;
+ printk("cpu_sibling_map[%d] = %d\n", cpu, cpu_sibling_map[cpu]);
+ break;
+ }
+ }
+ if (cpu_sibling_map[cpu] == NO_PROC_ID) {
+ smp_num_siblings = 1;
+ printk(KERN_WARNING "WARNING: No sibling found for CPU %d.\n", cpu);
+ }
+ }
+ }
+
#ifndef CONFIG_VISWS
/*
* Here we can be sure that there is an IO-APIC in the system. Let's
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