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[LV-kern-commit] CVS: kernel-2.4/drivers/net vaxsgec.h,NONE,1.1
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From: ? <uns...@us...> - 2002-05-23 16:33:16
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Update of /cvsroot/linux-vax/kernel-2.4/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv7294
Added Files:
vaxsgec.h
Log Message:
Split the #define's from vaxsgec.c off to a header file.
(From Richard Banks's latest version)
--- NEW FILE ---
/*
* vaxsgec.h - Header file for vaxsgec.c
*
* Created by Richard Banks
*
*/
#define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
#define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
/* SGEC bit definitions */
/* NICSR0: */
#define SG_NICSR0_IPL 0xc0000000 /* interrupt priority level: */
#define SG_NICSR0_IPL14 0x00000000 /* 0x14 */
#define SG_NICSR0_IPL15 0x40000000 /* 0x15 */
#define SG_NICSR0_IPL16 0x80000000 /* 0x16 */
#define SG_NICSR0_IPL17 0xc0000000 /* 0x17 */
#define SG_NICSR0_SA 0x20000000 /* sync(1)/async mode */
#define SG_NICSR0_MBO 0x1fff0003 /* must be set to one on write */
#define SG_NICSR0_IV_MASK 0x0000fffc /* bits for the interrupt vector */
/* NICSR1: */
#define SG_NICSR1_TXPD 0xffffffff /* transmit polling demand */
/* NICSR2: */
#define SG_NICSR2_RXPD 0xffffffff /* receive polling demand */
/* NICSR3: RX descriptor list address */
/* NICSR4: TX descriptor list address */
/* NICSR5: */
#define SG_NICSR5_ID 0x80000000 /* init done */
#define SG_NICSR5_SF 0x40000000 /* self-test failed */
#define SG_NICSR5_SS 0x3c000000 /* self-test status field */
#define SG_NICSR5_TS 0x03000000 /* transmission state: */
#define SG_NICSR5_TS_STOP 0x00000000 /* stopped */
#define SG_NICSR5_TS_RUN 0x01000000 /* running */
#define SG_NICSR5_TS_SUSP 0x02000000 /* suspended */
#define SG_NICSR5_RS 0x00c00000 /* reception state: */
#define SG_NICSR5_RS_STOP 0x00000000 /* stopped */
#define SG_NICSR5_RS_RUN 0x00400000 /* running */
#define SG_NICSR5_RS_SUSP 0x00800000 /* suspended */
#define SG_NICSR5_OM 0x00060000 /* operating mode: */
#define SG_NICSR5_OM_NORM 0x00000000 /* normal */
#define SG_NICSR5_OM_ILBK 0x00020000 /* internal loopback */
#define SG_NICSR5_OM_ELBK 0x00040000 /* external loopback */
#define SG_NICSR5_OM_DIAG 0x00060000 /* reserved for diags */
#define SG_NICSR5_DN 0x00010000 /* virtual CSR access done */
#define SG_NICSR5_MBO 0x0038ff00 /* must be one */
#define SG_NICSR5_BO 0x00000080 /* boot message received */
#define SG_NICSR5_TW 0x00000040 /* transmit watchdog timeout */
#define SG_NICSR5_RW 0x00000020 /* receive watchdog timeout */
#define SG_NICSR5_ME 0x00000010 /* memory error */
#define SG_NICSR5_RU 0x00000008 /* receive buffer unavailable */
#define SG_NICSR5_RI 0x00000004 /* receiver interrupt */
#define SG_NICSR5_TI 0x00000002 /* transmitter interrupt */
#define SG_NICSR5_IS 0x00000001 /* interrupt summary */
/* NICSR6: */
#define SG_NICSR6_RE 0x80000000 /* reset */
#define SG_NICSR6_IE 0x40000000 /* interrupt enable */
#define SG_NICSR6_MBO 0x01e7f000 /* must be one */
#define SG_NICSR6_BL 0x1e000000 /* burst limit mask */
#define SG_NICSR6_BL_8 0x10000000 /* 8 longwords */
#define SG_NICSR6_BL_4 0x08000000 /* 4 longwords */
#define SG_NICSR6_BL_2 0x04000000 /* 2 longwords */
#define SG_NICSR6_BL_1 0x02000000 /* 1 longword */
#define SG_NICSR6_BE 0x00100000 /* boot message enable */
#define SG_NICSR6_SE 0x00080000 /* single cycle enable */
#define SG_NICSR6_ST 0x00000800 /* start(1)/stop(0) transmission */
#define SG_NICSR6_SR 0x00000400 /* start(1)/stop(0) reception */
#define SG_NICSR6_OM 0x00000300 /* operating mode: */
#define SG_NICSR6_OM_NORM 0x00000000 /* normal */
#define SG_NICSR6_OM_ILBK 0x00000100 /* internal loopback */
#define SG_NICSR6_OM_ELBK 0x00000200 /* external loopback */
#define SG_NICSR6_OM_DIAG 0x00000300 /* reserved for diags */
#define SG_NICSR6_DC 0x00000080 /* disable data chaining */
#define SG_NICSR6_FC 0x00000040 /* force collision mode */
#define SG_NICSR6_PB 0x00000008 /* pass bad frames */
#define SG_NICSR6_AF 0x00000006 /* address filtering mode: */
#define SG_NICSR6_AF_NORM 0x00000000 /* normal filtering */
#define SG_NICSR6_AF_PROM 0x00000002 /* promiscuous mode */
#define SG_NICSR6_AF_ALLM 0x00000004 /* all multicasts */
/* NICSR7: system page table base address */
/* NICSR8: reserved */
/* NICSR9: */
#define SG_VNICSR9_RT 0xffff0000 /* receiver timeout, *1.6 us */
#define SG_VNICSR9_TT 0x0000ffff /* transmitter timeout */
/* NICSR10: */
#define SG_VNICSR10_RN 0x001f0000 /* SGEC version */
#define SG_VNICSR10_MFC 0x0000ffff /* missed frame counter */
/* NICSR11: boot message verification (low) (v) */
/* NICSR12: boot message verification (high) (v) */
/* NICSR13: boot message processor (v) */
/* NICSR14: diagnostic breakpoint (v) */
/* NICSR15: monitor command */
/* transmit descriptor flags */
#define SG_FR_OWN 0x8000 /* We own the descriptor */
#define SG_R0_ERR 0x8000 /* an error occurred */
#define SG_R0_LEN 0x4000 /* length error */
#define SG_R0_DAT 0x3000 /* data type (next 3 are subtypes) */
#define SG_R0_DAT_NORM 0x0000 /* normal frame */
#define SG_R0_DAT_INLB 0x1000 /* internal loop back */
#define SG_R0_DAT_EXLB 0x2000 /* external loop back */
#define SG_R0_FRA 0x0800 /* runt frame */
#define SG_R0_OFL 0x0400 /* buffer overflow */
#define SG_R0_FSG 0x0200 /* first segment */
#define SG_R0_LSG 0x0100 /* last segment */
#define SG_R0_LNG 0x0080 /* frame too long */
#define SG_R0_COL 0x0040 /* collision seen */
#define SG_R0_EFT 0x0020 /* etherenet frame type */
#define SG_R0_TNV 0x0008 /* address translation not valid */
#define SG_R0_DRB 0x0004 /* saw some dribbling bits */
#define SG_R0_CRC 0x0002 /* CRC error */
#define SG_R0_FFO 0x0001 /* fifo overflow */
#define SG_R1_CAD 0x80 /* chain address */
#define SG_R1_VAD 0x40 /* virtual address */
#define SG_R1_VPA 0x20 /* virtual/physical PTE address */
/* Receive descriptor bits */
#define SG_TDR_OWN 0x8000 /* SGEC owns this descriptor */
#define SG_TD0_ES 0x8000 /* an error has occurred */
#define SG_TD0_TO 0x4000 /* transmit watchdog timeout */
#define SG_TD0_LE 0x1000 /* length error */
#define SG_TD0_LO 0x0800 /* loss of carrier */
#define SG_TD0_NC 0x0400 /* no carrier */
#define SG_TD0_LC 0x0200 /* late collision */
#define SG_TD0_EC 0x0100 /* excessive collisions */
#define SG_TD0_HF 0x0080 /* heartbeat fail */
#define SG_TD0_CC 0x0078 /* collision count mask */
#define SG_TD0_TN 0x0004 /* address translation invalid */
#define SG_TD0_UF 0x0002 /* underflow */
#define SG_TD0_DE 0x0001 /* transmission deferred */
#define SG_TD1_CA 0x8000 /* chain address */
#define SG_TD1_VA 0x4000 /* virtual address */
#define SG_TD1_DT 0x3000 /* data type: */
#define SG_TD1_DT_NORM 0x0000 /* normal transmit frame */
#define SG_TD1_DT_SETUP 0x2000 /* setup frame */
#define SG_TD1_DT_DIAG 0x3000 /* diagnostic frame */
#define SG_TD1_AC 0x0800 /* CRC disable */
#define SG_TD1_FS 0x0400 /* first segment */
#define SG_TD1_LS 0x0200 /* last segment */
#define SG_TD1_POK 0x0600 /* packet OK to send - first and last segment set */
#define SG_TD1_IC 0x0100 /* interrupt on completion */
#define SG_TD1_VT 0x0080 /* virtual(1)/phys PTE address */
/*
* Adresses.
*/
/* The registers. */
#define SGECADDR 0x20008000
#define VXT_SGECADDR 0x20000000 /* 20008000 would probably work too due to address aliasing, but 20000000 is probably more "right" */
/* The IDPROM. */
#define QBUS_NISA_ROM 0x20084000 /* 3100/85 */
#define VSBUS_NISA_ROM 0x27800000 /* 3100/90 (?) */
#define VXT_NISA_ROM 0x200c4000 /* VXT2000 */
/* The interrupt vector. */
#define SGECVEC 0x41 /* 3100/85 */
#define OTHER_SGECVEC 0x108 /* 4000/60 (?) */
/* register offsets */
#define SG_CSR0 0
#define SG_CSR1 4
#define SG_CSR2 8
#define SG_CSR3 12
#define SG_CSR4 16
#define SG_CSR5 20
#define SG_CSR6 24
#define SG_CSR7 28
#define SG_CSR8 32
#define SG_CSR9 36
#define SG_CSR10 40
#define SG_CSR11 44
#define SG_CSR12 48
#define SG_CSR13 52
#define SG_CSR14 56
#define SG_CSR15 60
/* must be an even number of receive/transmit descriptors */
#define RXDESCS 30 /* no of receive descriptors */
#define TXDESCS 60 /* no of transmit descriptors */
#define TX_RING_SIZE 60
#define TX_RING_MOD_MASK 59
#define RX_RING_SIZE 30
#define RX_RING_MOD_MASK 29
#define PKT_BUF_SZ 1536
#define RX_BUFF_SIZE PKT_BUF_SZ
#define TX_BUFF_SIZE PKT_BUF_SZ
#define BUF_OFFSET_CPU (offsetof(struct sgec_shared_mem, rx_buf))
#define BUF_OFFSET_LNC BUF_OFFSET_CPU
/* SGEC CSRs */
struct sgec_regs {
unsigned long sg_nicsr0; /* vector address, IPL, sync mode */
unsigned long sg_nicsr1; /* TX poll demand */
unsigned long sg_nicsr2; /* RX poll demand */
unsigned long sg_nicsr3; /* RX descriptor list address */
unsigned long sg_nicsr4; /* TX descriptor list address */
unsigned long sg_nicsr5; /* SGEC status */
unsigned long sg_nicsr6; /* SGEC command/mode */
unsigned long sg_nicsr7; /* system page table base address */
unsigned long sg_nivcsr8; /* reserved virtual CSR */
unsigned long sg_nivcsr9; /* watchdog timers (virtual) */
unsigned long sg_nivcsr10; /* revision, missed frame count (v) */
unsigned long sg_nivcsr11; /* boot message verification (low) (v) */
unsigned long sg_nivcsr12; /* boot message verification (high) (v) */
unsigned long sg_nivcsr13; /* boot message processor (v) */
unsigned long sg_nivcsr14; /* diagnostic breakpoint (v) */
unsigned long sg_nicsr15; /* monitor command */
};
/* Receive descriptor */
struct sgec_rx_desc{
unsigned short flags0; /* descriptor flags */
unsigned short framelen; /* frame length */
unsigned char unused[3]; /* unused */
unsigned char flags1; /* more descriptor flags */
short page_offset; /* buffer page offset */
short bufsize; /* buffer size */
unsigned long bufaddr; /* buffer address */
};
/* Transmit descriptor */
struct sgec_tx_desc {
unsigned short flags0; /* descriptor flags */
unsigned short tx_err; /* Count of transmit errors (or TDR counter?) */
unsigned char unused[2]; /* unused */
unsigned short flags1; /* more descriptor flags */
short pageoffset; /* offset of buffer in page */
short bufsize; /* length of data buffer */
unsigned long bufaddr; /* address of data buffer */
};
/* This is how our shared memory block is laid out */
struct sgec_shared_mem {
char rx_buf[RX_RING_SIZE][RX_BUFF_SIZE]; /* packet storage */
char tx_buf[TX_RING_SIZE][TX_BUFF_SIZE]; /* packet storage */
u_int8_t setup_frame[128]; /* setup frame/packet */
};
struct sgec_private {
char *name;
volatile struct sgec_regs *regs; /* location of registers */
unsigned short mode; /* Pre-set mode (reg. 15) */
unsigned char phys_addr[6]; /* Physical ethernet address */
unsigned short filter[4]; /* Multicast filter. */
unsigned short rx_ptr; /* receive descriptor addr */
unsigned short rx_len; /* receive len and high addr */
unsigned short tx_ptr; /* transmit descriptor addr */
unsigned short tx_len; /* transmit len and high addr */
struct sgec_rx_desc rx_ring[RX_RING_SIZE];
struct sgec_tx_desc tx_ring[TX_RING_SIZE];
volatile struct sgec_shared_mem *card_mem; /* virtual addr of shared memory block */
unsigned char vsbus_int;
spinlock_t lock;
int rx_new, tx_new;
int rx_old, tx_old;
struct net_device_stats stats;
struct net_device *dev; /* Backpointer */
struct sgec_private *next_module;
struct timer_list multicast_timer;
};
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