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[LV-kern-commit] CVS: kernel-2.4/include/asm-ia64/sn/pci pciba.h,NONE,1.1 bridge.h,1.1.1.1,1.2 pci_bus_cvlink.h,1.1.1.1,1.2 pci_defs.h,1.1.1.1,1.2 pcibr.h,1.1.1.1,1.2 pcibr_private.h,1.1.1.1,1.2 pciio.h,1.1.1.1,1.2 pciio_private.h,1.1.1.1,1.2
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-ia64/sn/pci
Modified Files:
bridge.h pci_bus_cvlink.h pci_defs.h pcibr.h pcibr_private.h
pciio.h pciio_private.h
Added Files:
pciba.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/* $Id: pciba.h,v 1.1 2002/04/09 12:33:12 atp Exp $
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
* Copyright (C) 2000 by Colin Ngam
*/
#ifndef _ASM_SN_PCI_PCIBA_H
#define _ASM_SN_PCI_PCIBA_H
/*
* These are all the HACKS from ioccom.h ..
*/
#define IOCPARM_MASK 0xff /* parameters must be < 256 bytes */
#define IOC_VOID 0x20000000 /* no parameters */
/*
* The above needs to be modified and follow LINUX ...
*/
/* /hw/.../pci/[slot]/config accepts ioctls to read
* and write specific registers as follows:
*
* "t" is the native type (char, short, uint32, uint64)
* to read from CFG space; results will be arranged in
* byte significance (ie. first byte from PCI is lowest
* or last byte in result).
*
* "r" is the byte offset in PCI CFG space of the first
* byte of the register (it's least significant byte,
* in the little-endian PCI numbering). This can actually
* be as much as 16 bits wide, and is intended to match
* the layout of a "Type 1 Configuration Space" address:
* the register number in the low eight bits, then three
* bits for the function number and five bits for the
* slot number.
*/
#define PCIIOCCFGRD(t,r) _IOR(0,(r),t)
#define PCIIOCCFGWR(t,r) _IOW(0,(r),t)
/* Some common config register access commands.
* Use these as examples of how to construct
* values for other registers you want to access.
*/
/* PCIIOCGETID: arg is ptr to 32-bit int,
* returns the 32-bit ID value with VENDOR
* in the bottom 16 bits and DEVICE in the top.
*/
#define PCIIOCGETID PCIIOCCFGRD(uint32_t,PCI_CFG_VENDOR_ID)
/* PCIIOCSETCMD: arg is ptr to a 16-bit short,
* which will be written to the CMD register.
*/
#define PCIIOCSETCMD PCIIOCCFGWR(uint16_t,PCI_CFG_COMMAND)
/* PCIIOCGETREV: arg is ptr to an 8-bit char,
* which will get the 8-bit revision number.
*/
#define PCIIOCGETREV PCIIOCCFGRD(uint8_t,PCI_CFG_REV_ID)
/* PCIIOCGETHTYPE: arg is ptr to an 8-bit char,
* which will get the 8-bit header type.
*/
#define PCIIOCGETHTYPE PCIIOCCFGRD(uint8_t,PCI_CFG_HEADER_TYPE)
/* PCIIOCGETBASE(n): arg is ptr to a 32-bit int,
* which will get the value of the BASE<n> register.
*/
#define PCIIOCGETBASE(n) PCIIOCCFGRD(uint32_t,PCI_CFG_BASE_ADDR(n))
/* /hw/.../pci/[slot]/intr accepts an ioctl to
* set up user level interrupt handling as follows:
*
* "n" is a bitmap of which of the four PCI interrupt
* lines are of interest, using PCIIO_INTR_LINE_[ABCD].
*/
#define PCIIOCSETULI(n) _IOWR(1,n,struct uliargs)
#if _KERNEL
#define PCIIOCSETULI32(n) _IOWR(1,n,struct uliargs32)
#endif
/* /hw/.../pci/[slot]/dma accepts ioctls to allocate
* and free physical memory for use in user-triggered
* DMA operations.
*/
#define PCIIOCDMAALLOC _IOWR(0,1,uint64_t)
#define PCIIOCDMAFREE _IOW(0,1,uint64_t)
/* The parameter for PCIIOCDMAALLOC needs to contain
* both the size of the request and the flag values
* to be used in setting up the DMA.
*
* Any flags normally useful in pciio_dmamap
* or pciio_dmatrans function calls can6 be used here.
*/
#define PCIIOCDMAALLOC_REQUEST_PACK(flags,size) \
((((uint64_t)(flags))<<32)| \
(((uint64_t)(size))&0xFFFFFFFF))
#endif /* _ASM_SN_PCI_PCIBA_H */
Index: bridge.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci/bridge.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- bridge.h 14 Jan 2001 17:01:53 -0000 1.1.1.1
+++ bridge.h 9 Apr 2002 12:33:12 -0000 1.2
@@ -373,7 +373,7 @@
ds:2, /* Data size */
gbr:1, /* GBR enable */
vbpm:1, /* VBPM message */
- error:1, /* Error occured */
+ error:1, /* Error occurred */
barr:1, /* Barrier op */
rsvd:8;
} berr_st;
@@ -693,7 +693,7 @@
#define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
#define BRIDGE_INT_VIEW 0x000174 /* Interrupt view */
-#define BRIDGE_MULTIPLE_INT 0x00017c /* Multiple interrupt occured */
+#define BRIDGE_MULTIPLE_INT 0x00017c /* Multiple interrupt occurred */
#define BRIDGE_FORCE_ALWAYS0 0x000184 /* Force an interrupt (always)*/
#define BRIDGE_FORCE_ALWAYS_OFF 0x000008 /* Force Always offset */
Index: pci_bus_cvlink.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci/pci_bus_cvlink.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- pci_bus_cvlink.h 14 Jan 2001 17:01:53 -0000 1.1.1.1
+++ pci_bus_cvlink.h 9 Apr 2002 12:33:12 -0000 1.2
@@ -26,4 +26,23 @@
int isa64;
};
+struct sn1_dma_maps_s{
+ struct pcibr_dmamap_s dma_map;
+ dma_addr_t dma_addr;
+};
+
+struct ioports_to_tlbs_s {
+ unsigned long p:1,
+ rv_1:1,
+ ma:3,
+ a:1,
+ d:1,
+ pl:2,
+ ar:3,
+ ppn:38,
+ rv_2:2,
+ ed:1,
+ ig:11;
+};
+
#endif /* _ASM_SN_PCI_CVLINK_H */
Index: pci_defs.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci/pci_defs.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
Index: pcibr.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci/pcibr.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- pcibr.h 14 Jan 2001 17:01:56 -0000 1.1.1.1
+++ pcibr.h 9 Apr 2002 12:33:12 -0000 1.2
@@ -143,6 +143,14 @@
extern void pcibr_dmamap_done(pcibr_dmamap_t dmamap);
+/*
+ * pcibr_get_dmatrans_node() will return the compact node id to which
+ * all 32-bit Direct Mapping memory accesses will be directed.
+ * (This node id can be different for each PCI bus.)
+ */
+
+extern cnodeid_t pcibr_get_dmatrans_node(devfs_handle_t pconn_vhdl);
+
extern iopaddr_t pcibr_dmatrans_addr(devfs_handle_t dev,
device_desc_t dev_desc,
paddr_t paddr,
@@ -215,10 +223,6 @@
pciio_space_t *spacep,
iopaddr_t *addrp);
-extern int pcibr_rrb_alloc(devfs_handle_t pconn_vhdl,
- int *count_vchan0,
- int *count_vchan1);
-
extern int pcibr_wrb_flush(devfs_handle_t pconn_vhdl);
extern int pcibr_rrb_check(devfs_handle_t pconn_vhdl,
int *count_vchan0,
@@ -241,7 +245,7 @@
void pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl,
rrb_alloc_funct_f *func);
-extern void pcibr_device_unregister(devfs_handle_t);
+extern int pcibr_device_unregister(devfs_handle_t);
extern int pcibr_dma_enabled(devfs_handle_t);
/*
* Bridge-specific flags that can be set via pcibr_device_flags_set
@@ -337,7 +341,7 @@
extern void pcibr_hints_fix_rrbs(devfs_handle_t);
extern void pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t);
-extern void pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, uint64_t);
+extern void pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, ulong);
extern void pcibr_hints_handsoff(devfs_handle_t);
typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t);
@@ -353,8 +357,104 @@
#define PCIBR 'p'
#define _PCIBR(x) ((PCIBR << 8) | (x))
-#define PCIBR_SLOT_POWERUP _PCIBR(1)
-#define PCIBR_SLOT_SHUTDOWN _PCIBR(2)
-#define PCIBR_SLOT_INQUIRY _PCIBR(3)
+#define PCIBR_SLOT_STARTUP _PCIBR(1)
+#define PCIBR_SLOT_SHUTDOWN _PCIBR(2)
+#define PCIBR_SLOT_QUERY _PCIBR(3)
+
+/*
+ * Bit defintions for variable slot_status in struct
+ * pcibr_soft_slot_s. They are here so that both
+ * the pcibr driver and the pciconfig command can
+ * reference them.
+ */
+#define SLOT_STARTUP_CMPLT 0x01
+#define SLOT_STARTUP_INCMPLT 0x02
+#define SLOT_SHUTDOWN_CMPLT 0x04
+#define SLOT_SHUTDOWN_INCMPLT 0x08
+#define SLOT_POWER_UP 0x10
+#define SLOT_POWER_DOWN 0x20
+#define SLOT_IS_SYS_CRITICAL 0x40
+
+#define SLOT_STATUS_MASK (SLOT_STARTUP_CMPLT | SLOT_STARTUP_INCMPLT | \
+ SLOT_SHUTDOWN_CMPLT | SLOT_SHUTDOWN_INCMPLT)
+#define SLOT_POWER_MASK (SLOT_POWER_UP | SLOT_POWER_DOWN)
+
+/*
+ * Bit definitions for variable resp_f_staus.
+ * They are here so that both the pcibr driver
+ * and the pciconfig command can reference them.
+ */
+#define FUNC_IS_VALID 0x01
+#define FUNC_IS_SYS_CRITICAL 0x02
+
+/*
+ * Structures for requesting PCI bridge information and receiving a response
+ */
+typedef struct pcibr_slot_info_req_s *pcibr_slot_info_req_t;
+typedef struct pcibr_slot_info_resp_s *pcibr_slot_info_resp_t;
+typedef struct pcibr_slot_func_info_resp_s *pcibr_slot_func_info_resp_t;
+
+struct pcibr_slot_info_req_s {
+ int req_slot;
+ pcibr_slot_info_resp_t req_respp;
+ int req_size;
+};
+
+struct pcibr_slot_info_resp_s {
+ int resp_has_host;
+ char resp_host_slot;
+ devfs_handle_t resp_slot_conn;
+ char resp_slot_conn_name[MAXDEVNAME];
+ int resp_slot_status;
+ int resp_l1_bus_num;
+ int resp_bss_ninfo;
+ char resp_bss_devio_bssd_space[16];
+ iopaddr_t resp_bss_devio_bssd_base;
+ bridgereg_t resp_bss_device;
+ int resp_bss_pmu_uctr;
+ int resp_bss_d32_uctr;
+ int resp_bss_d64_uctr;
+ iopaddr_t resp_bss_d64_base;
+ unsigned resp_bss_d64_flags;
+ iopaddr_t resp_bss_d32_base;
+ unsigned resp_bss_d32_flags;
+ int resp_bss_ext_ates_active;
+ volatile unsigned *resp_bss_cmd_pointer;
+ unsigned resp_bss_cmd_shadow;
+ int resp_bs_rrb_valid;
+ int resp_bs_rrb_valid_v;
+ int resp_bs_rrb_res;
+ bridgereg_t resp_b_resp;
+ bridgereg_t resp_b_int_device;
+ bridgereg_t resp_b_int_enable;
+ bridgereg_t resp_b_int_host;
+
+ struct pcibr_slot_func_info_resp_s {
+ int resp_f_status;
+ char resp_f_slot_name[MAXDEVNAME];
+ char resp_f_bus;
+ char resp_f_slot;
+ char resp_f_func;
+ char resp_f_master_name[MAXDEVNAME];
+ void *resp_f_pops;
+ error_handler_f *resp_f_efunc;
+ error_handler_arg_t resp_f_einfo;
+ int resp_f_vendor;
+ int resp_f_device;
+
+ struct {
+ char resp_w_space[16];
+ iopaddr_t resp_w_base;
+ size_t resp_w_size;
+ } resp_f_window[6];
+
+ unsigned resp_f_rbase;
+ unsigned resp_f_rsize;
+ int resp_f_ibit[4];
+ int resp_f_att_det_error;
+
+ } resp_func[8];
+
+};
#endif /* _ASM_SN_PCI_PCIBR_H */
Index: pcibr_private.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci/pcibr_private.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- pcibr_private.h 14 Jan 2001 17:01:58 -0000 1.1.1.1
+++ pcibr_private.h 9 Apr 2002 12:33:12 -0000 1.2
@@ -17,6 +17,7 @@
*/
#include <asm/sn/pci/pciio_private.h>
+#include <asm/sn/ksys/l1.h>
/*
* convenience typedefs
@@ -31,6 +32,7 @@
typedef struct pcibr_hints_s *pcibr_hints_t;
typedef struct pcibr_intr_list_s *pcibr_intr_list_t;
typedef struct pcibr_intr_wrap_s *pcibr_intr_wrap_t;
+typedef struct pcibr_intr_cbuf_s *pcibr_intr_cbuf_t;
/*
* Bridge sets up PIO using this information.
@@ -50,7 +52,7 @@
xtalk_piomap_t bp_xtalk_pio; /* corresponding xtalk resource */
pcibr_piomap_t bp_next; /* Next piomap on the list */
pcibr_soft_t bp_soft; /* backpointer to bridge soft data */
- int bp_toc[1]; /* PCI timeout counter */
+ atomic_t bp_toc[1]; /* PCI timeout counter */
};
@@ -77,6 +79,18 @@
bridge_ate_t bd_ate_prime; /* value of 1st ATE written */
};
+#define IBUFSIZE 5 /* size of circular buffer (holds 4) */
+
+/*
+ * Circular buffer used for interrupt processing
+ */
+struct pcibr_intr_cbuf_s {
+ spinlock_t ib_lock; /* cbuf 'put' lock */
+ int ib_in; /* index of next free entry */
+ int ib_out; /* index of next full entry */
+ pcibr_intr_wrap_t ib_cbuf[IBUFSIZE]; /* circular buffer of wrap */
+};
+
/*
* Bridge sets up interrupts using this information.
*/
@@ -94,6 +108,7 @@
#define bi_cpu bi_pi.pi_cpu /* cpu assigned. */
unsigned bi_ibits; /* which Bridge interrupt bit(s) */
pcibr_soft_t bi_soft; /* shortcut to soft info */
+ struct pcibr_intr_cbuf_s bi_ibuf; /* circular buffer of wrap ptrs */
};
/*
@@ -121,6 +136,7 @@
/* pcibr-specific connection state */
int f_ibit[4]; /* Bridge bit for each INTx */
pcibr_piomap_t f_piomap;
+ int f_att_det_error;
};
/* =====================================================================
@@ -139,8 +155,11 @@
struct pcibr_intr_wrap_s {
pcibr_soft_t iw_soft; /* which bridge */
volatile bridgereg_t *iw_stat; /* ptr to b_int_status */
- bridgereg_t iw_intr; /* bits in b_int_status */
+ bridgereg_t iw_intr; /* bit in b_int_status */
pcibr_intr_list_t iw_list; /* ghostbusters! */
+ int iw_hdlrcnt; /* running handler count */
+ int iw_shared; /* if Bridge bit is shared */
+ int iw_connected; /* if already connected */
};
#define PCIBR_ISR_ERR_START 8
@@ -175,11 +194,14 @@
unsigned bs_dma_flags; /* revision-implied DMA flags */
+ l1sc_t *bs_l1sc; /* io brick l1 system cntr */
+ moduleid_t bs_moduleid; /* io brick moduleid */
+
/*
* Lock used primarily to get mutual exclusion while managing any
* bridge resources..
*/
- lock_t bs_lock;
+ spinlock_t bs_lock;
devfs_handle_t bs_noslot_conn; /* NO-SLOT connection point */
pcibr_info_t bs_noslot_info;
@@ -199,6 +221,9 @@
int has_host;
pciio_slot_t host_slot;
devfs_handle_t slot_conn;
+
+ int slot_status;
+
/* Potentially several connection points
* for this slot. bss_ninfo is how many,
* and bss_infos is a pointer to
@@ -265,7 +290,7 @@
/* Shadow information used for implementing
* Bridge Hardware WAR #484930
*/
- int bss_ext_ates_active;
+ atomic_t bss_ext_ates_active;
volatile unsigned *bss_cmd_pointer;
unsigned bss_cmd_shadow;
@@ -295,13 +320,10 @@
*/
xtalk_intr_t bsi_xtalk_intr;
/*
- * We do not like sharing PCI interrrupt lines
- * between devices, but the Origin 200 PCI
- * layout forces us to do so.
+ * A wrapper structure is associated with each
+ * Bridge interrupt bit.
*/
- pcibr_intr_list_t bsi_pcibr_intr_list;
- pcibr_intr_wrap_t bsi_pcibr_intr_wrap;
- int bsi_pcibr_wrap_set;
+ struct pcibr_intr_wrap_s bsi_pcibr_intr_wrap;
} bs_intr[8];
@@ -325,10 +347,10 @@
*/
struct br_errintr_info {
int bserr_toutcnt;
-#ifdef IRIX
+#ifdef LATER
toid_t bserr_toutid; /* Timeout started by errintr */
#endif
- iopaddr_t bserr_addr; /* Address where error occured */
+ iopaddr_t bserr_addr; /* Address where error occurred */
bridgereg_t bserr_intstat; /* interrupts active at error time */
} bs_errinfo;
Index: pciio.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci/pciio.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- pciio.h 14 Jan 2001 17:02:01 -0000 1.1.1.1
+++ pciio.h 9 Apr 2002 12:33:12 -0000 1.2
@@ -35,15 +35,9 @@
#define PCIIO_DEVICE_ID_NONE -1
-#ifdef colin
-typedef char pciio_bus_t; /* PCI bus number (0..255) */
-typedef char pciio_slot_t; /* PCI slot number (0..31, 255) */
-typedef char pciio_function_t; /* PCI func number (0..7, 255) */
-#else
typedef uint8_t pciio_bus_t; /* PCI bus number (0..255) */
typedef uint8_t pciio_slot_t; /* PCI slot number (0..31, 255) */
typedef uint8_t pciio_function_t; /* PCI func number (0..7, 255) */
-#endif
#define PCIIO_SLOTS ((pciio_slot_t)32)
#define PCIIO_FUNCS ((pciio_function_t)8)
@@ -446,6 +440,24 @@
pciio_space_t *spacep,
iopaddr_t *addrp);
+typedef void
+pciio_driver_reg_callback_f (devfs_handle_t conn,
+ int key1,
+ int key2,
+ int error);
+
+typedef void
+pciio_driver_unreg_callback_f (devfs_handle_t conn, /* pci connection point */
+ int key1,
+ int key2,
+ int error);
+
+typedef int
+pciio_device_unregister_f (devfs_handle_t conn);
+
+typedef int
+pciio_dma_enabled_f (devfs_handle_t conn);
+
/*
* Adapters that provide a PCI interface adhere to this software interface.
*/
@@ -491,6 +503,12 @@
/* Error handling interface */
pciio_error_devenable_f *error_devenable;
pciio_error_extract_f *error_extract;
+
+ /* Callback support */
+ pciio_driver_reg_callback_f *driver_reg_callback;
+ pciio_driver_unreg_callback_f *driver_unreg_callback;
+ pciio_device_unregister_f *device_unregister;
+ pciio_dma_enabled_f *dma_enabled;
} pciio_provider_t;
/* PCI devices use these standard PCI provider interfaces */
@@ -540,13 +558,8 @@
#define PCIIO_WIDGETDEV_SLOT_MASK 0x1f
#define PCIIO_WIDGETDEV_FUNC_MASK 0x7
-#ifdef IRIX
-#define pciio_widgetdev_create(slot,func) \
- ((slot) << PCIIO_WIDGETDEV_SLOT_SHFT + (func))
-#else
#define pciio_widgetdev_create(slot,func) \
(((slot) << PCIIO_WIDGETDEV_SLOT_SHFT) + (func))
-#endif
#define pciio_widgetdev_slot_get(wdev) \
(((wdev) >> PCIIO_WIDGETDEV_SLOT_SHFT) & PCIIO_WIDGETDEV_SLOT_MASK)
@@ -612,8 +625,14 @@
pciio_info_t pciio_info); /* details about conn point */
-extern int pciio_device_attach(devfs_handle_t pcicard); /* vertex created by pciio_device_register */
-extern int pciio_device_detach(devfs_handle_t pcicard); /* vertex created by pciio_device_register */
+extern int
+pciio_device_attach(
+ devfs_handle_t pcicard, /* vertex created by pciio_device_register */
+ int drv_flags);
+extern int
+pciio_device_detach(
+ devfs_handle_t pcicard, /* vertex created by pciio_device_register */
+ int drv_flags);
/*
* Generic PCI interface, for use with all PCI providers
@@ -632,7 +651,7 @@
extern ulong pciio_pio_mapsz_get(pciio_piomap_t pciio_piomap);
extern caddr_t pciio_pio_kvaddr_get(pciio_piomap_t pciio_piomap);
-#ifdef IRIX
+#ifdef LATER
#ifdef USE_PCI_PIO
extern uint8_t pciio_pio_read8(volatile uint8_t *addr);
extern uint16_t pciio_pio_read16(volatile uint16_t *addr);
@@ -676,7 +695,7 @@
*addr = val;
}
#endif /* USE_PCI_PIO */
-#endif
+#endif /* LATER */
/* Generic PCI dma interfaces */
extern devfs_handle_t pciio_dma_dev_get(pciio_dmamap_t pciio_dmamap);
Index: pciio_private.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci/pciio_private.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- pciio_private.h 14 Jan 2001 17:02:02 -0000 1.1.1.1
+++ pciio_private.h 9 Apr 2002 12:33:12 -0000 1.2
@@ -10,10 +10,6 @@
#ifndef _ASM_SN_PCI_PCIIO_PRIVATE_H
#define _ASM_SN_PCI_PCIIO_PRIVATE_H
-#ifdef colin
-#include <ksys/xthread.h>
-#endif
-
/*
* pciio_private.h -- private definitions for pciio
* PCI drivers should NOT include this file.
@@ -54,12 +50,12 @@
pciio_intr_line_t pi_lines; /* which interrupt line(s) */
intr_func_t pi_func; /* handler function (when connected) */
intr_arg_t pi_arg; /* handler parameter (when connected) */
-#ifdef IRIX
+#ifdef LATER
thd_int_t pi_tinfo; /* Thread info (when connected) */
#endif
cpuid_t pi_mustruncpu; /* Where we must run. */
- int pi_irq; /* IRQ assigned */
- int pi_cpu; /* cpu assigned */
+ int pi_irq; /* IRQ assigned */
+ int pi_cpu; /* cpu assigned */
};
/* PCIIO_INTR (pi_flags) flags */
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