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[LV-kern-commit] CVS: kernel-2.4/include/asm-arm/hardware amba_kmi.h,NONE,1.1 clps7111.h,NONE,1.1 ep7211.h,NONE,1.1 ep7212.h,NONE,1.1 ioc.h,1.1.1.1,1.2 iomd.h,1.1.1.1,1.2 pci_v3.h,1.1.1.1,1.2 serial_amba.h,1.1.1.1,1.2
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/hardware In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-arm/hardware Modified Files: ioc.h iomd.h pci_v3.h serial_amba.h Added Files: amba_kmi.h clps7111.h ep7211.h ep7212.h Log Message: Synch to 2.4.15 commit 1 --- NEW FILE --- /* * linux/include/asm-arm/hardware/amba_kmi.h * * Internal header file for AMBA KMI ports * * Copyright (C) 2000 Deep Blue Solutions Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * * * --------------------------------------------------------------------------- * From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical * Reference Manual - ARM DDI 0143B - see http://www.arm.com/ * --------------------------------------------------------------------------- */ #ifndef ASM_ARM_HARDWARE_AMBA_KMI_H #define ASM_ARM_HARDWARE_AMBA_KMI_H /* * KMI control register: * KMICR_TYPE 0 = PS2/AT mode, 1 = No line control bit mode * KMICR_RXINTREN 1 = enable RX interrupts * KMICR_TXINTREN 1 = enable TX interrupts * KMICR_EN 1 = enable KMI * KMICR_FD 1 = force KMI data low * KMICR_FC 1 = force KMI clock low */ #define KMICR (KMI_BASE + 0x00) #define KMICR_TYPE (1 << 5) #define KMICR_RXINTREN (1 << 4) #define KMICR_TXINTREN (1 << 3) #define KMICR_EN (1 << 2) #define KMICR_FD (1 << 1) #define KMICR_FC (1 << 0) /* * KMI status register: * KMISTAT_TXEMPTY 1 = transmitter register empty * KMISTAT_TXBUSY 1 = currently sending data * KMISTAT_RXFULL 1 = receiver register ready to be read * KMISTAT_RXBUSY 1 = currently receiving data * KMISTAT_RXPARITY parity of last databyte received * KMISTAT_IC current level of KMI clock input * KMISTAT_ID current level of KMI data input */ #define KMISTAT (KMI_BASE + 0x04) #define KMISTAT_TXEMPTY (1 << 6) #define KMISTAT_TXBUSY (1 << 5) #define KMISTAT_RXFULL (1 << 4) #define KMISTAT_RXBUSY (1 << 3) #define KMISTAT_RXPARITY (1 << 2) #define KMISTAT_IC (1 << 1) #define KMISTAT_ID (1 << 0) /* * KMI data register */ #define KMIDATA (KMI_BASE + 0x08) /* * KMI clock divisor: to generate 8MHz internal clock * div = (ref / 8MHz) - 1; 0 <= div <= 15 */ #define KMICLKDIV (KMI_BASE + 0x0c) /* * KMI interrupt register: * KMIIR_TXINTR 1 = transmit interrupt asserted * KMIIR_RXINTR 1 = receive interrupt asserted */ #define KMIIR (KMI_BASE + 0x10) #define KMIIR_TXINTR (1 << 1) #define KMIIR_RXINTR (1 << 0) /* * The size of the KMI primecell */ #define KMI_SIZE (0x100) #endif --- NEW FILE --- /* * linux/include/asm-arm/hardware/clps7111.h * * This file contains the hardware definitions of the CLPS7111 internal * registers. * * Copyright (C) 2000 Deep Blue Solutions Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_HARDWARE_CLPS7111_H #define __ASM_HARDWARE_CLPS7111_H #define CLPS7111_PHYS_BASE (0x80000000) #ifndef __ASSEMBLY__ #define clps_readb(off) __raw_readb(CLPS7111_BASE + (off)) #define clps_readl(off) __raw_readl(CLPS7111_BASE + (off)) #define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off)) #define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off)) #endif #define PADR (0x0000) #define PBDR (0x0001) #define PDDR (0x0003) #define PADDR (0x0040) #define PBDDR (0x0041) #define PDDDR (0x0043) #define PEDR (0x0080) #define PEDDR (0x00c0) #define SYSCON1 (0x0100) #define SYSFLG1 (0x0140) #define MEMCFG1 (0x0180) #define MEMCFG2 (0x01c0) #define DRFPR (0x0200) #define INTSR1 (0x0240) #define INTMR1 (0x0280) #define LCDCON (0x02c0) #define TC2D (0x0340) #define RTCDR (0x0380) #define RTCMR (0x03c0) #define PMPCON (0x0400) #define CODR (0x0440) #define UARTDR1 (0x0480) #define UBRLCR1 (0x04c0) #define SYNCIO (0x0500) #define PALLSW (0x0540) #define PALMSW (0x0580) #define STFCLR (0x05c0) #define BLEOI (0x0600) #define MCEOI (0x0640) #define TEOI (0x0680) #define TC1EOI (0x06c0) #define TC2EOI (0x0700) #define RTCEOI (0x0740) #define UMSEOI (0x0780) #define COEOI (0x07c0) #define HALT (0x0800) #define STDBY (0x0840) #define FBADDR (0x1000) #define SYSCON2 (0x1100) #define SYSFLG2 (0x1140) #define INTSR2 (0x1240) #define INTMR2 (0x1280) #define UARTDR2 (0x1480) #define UBRLCR2 (0x14c0) #define SS2DR (0x1500) #define SRXEOF (0x1600) #define SS2POP (0x16c0) #define KBDEOI (0x1700) /* common bits: SYSCON1 / SYSCON2 */ #define SYSCON_UARTEN (1 << 8) #define SYSCON1_KBDSCAN(x) ((x) & 15) #define SYSCON1_KBDSCANMASK (15) #define SYSCON1_TC1M (1 << 4) #define SYSCON1_TC1S (1 << 5) #define SYSCON1_TC2M (1 << 6) #define SYSCON1_TC2S (1 << 7) #define SYSCON1_UART1EN SYSCON_UARTEN #define SYSCON1_BZTOG (1 << 9) #define SYSCON1_BZMOD (1 << 10) #define SYSCON1_DBGEN (1 << 11) #define SYSCON1_LCDEN (1 << 12) #define SYSCON1_CDENTX (1 << 13) #define SYSCON1_CDENRX (1 << 14) #define SYSCON1_SIREN (1 << 15) #define SYSCON1_ADCKSEL(x) (((x) & 3) << 16) #define SYSCON1_ADCKSEL_MASK (3 << 16) #define SYSCON1_EXCKEN (1 << 18) #define SYSCON1_WAKEDIS (1 << 19) #define SYSCON1_IRTXM (1 << 20) /* common bits: SYSFLG1 / SYSFLG2 */ #define SYSFLG_UBUSY (1 << 11) #define SYSFLG_URXFE (1 << 22) #define SYSFLG_UTXFF (1 << 23) #define SYSFLG1_MCDR (1 << 0) #define SYSFLG1_DCDET (1 << 1) #define SYSFLG1_WUDR (1 << 2) #define SYSFLG1_WUON (1 << 3) #define SYSFLG1_CTS (1 << 8) #define SYSFLG1_DSR (1 << 9) #define SYSFLG1_DCD (1 << 10) #define SYSFLG1_UBUSY SYSFLG_UBUSY #define SYSFLG1_NBFLG (1 << 12) #define SYSFLG1_RSTFLG (1 << 13) #define SYSFLG1_PFFLG (1 << 14) #define SYSFLG1_CLDFLG (1 << 15) #define SYSFLG1_URXFE SYSFLG_URXFE #define SYSFLG1_UTXFF SYSFLG_UTXFF #define SYSFLG1_CRXFE (1 << 24) #define SYSFLG1_CTXFF (1 << 25) #define SYSFLG1_SSIBUSY (1 << 26) #define SYSFLG1_ID (1 << 29) #define SYSFLG2_SSRXOF (1 << 0) #define SYSFLG2_RESVAL (1 << 1) #define SYSFLG2_RESFRM (1 << 2) #define SYSFLG2_SS2RXFE (1 << 3) #define SYSFLG2_SS2TXFF (1 << 4) #define SYSFLG2_SS2TXUF (1 << 5) #define SYSFLG2_CKMODE (1 << 6) #define SYSFLG2_UBUSY SYSFLG_UBUSY #define SYSFLG2_URXFE SYSFLG_URXFE #define SYSFLG2_UTXFF SYSFLG_UTXFF #define LCDCON_GSEN (1 << 30) #define LCDCON_GSMD (1 << 31) #define SYSCON2_SERSEL (1 << 0) #define SYSCON2_KBD6 (1 << 1) #define SYSCON2_DRAMZ (1 << 2) #define SYSCON2_KBWEN (1 << 3) #define SYSCON2_SS2TXEN (1 << 4) #define SYSCON2_PCCARD1 (1 << 5) #define SYSCON2_PCCARD2 (1 << 6) #define SYSCON2_SS2RXEN (1 << 7) #define SYSCON2_UART2EN SYSCON_UARTEN #define SYSCON2_SS2MAEN (1 << 9) #define SYSCON2_OSTB (1 << 12) #define SYSCON2_CLKENSL (1 << 13) #define SYSCON2_BUZFREQ (1 << 14) /* common bits: UARTDR1 / UARTDR2 */ #define UARTDR_FRMERR (1 << 8) #define UARTDR_PARERR (1 << 9) #define UARTDR_OVERR (1 << 10) /* common bits: UBRLCR1 / UBRLCR2 */ #define UBRLCR_BAUD_MASK ((1 << 12) - 1) #define UBRLCR_BREAK (1 << 12) #define UBRLCR_PRTEN (1 << 13) #define UBRLCR_EVENPRT (1 << 14) #define UBRLCR_XSTOP (1 << 15) #define UBRLCR_FIFOEN (1 << 16) #define UBRLCR_WRDLEN5 (0 << 17) #define UBRLCR_WRDLEN6 (1 << 17) #define UBRLCR_WRDLEN7 (2 << 17) #define UBRLCR_WRDLEN8 (3 << 17) #define UBRLCR_WRDLEN_MASK (3 << 17) #define SYNCIO_SMCKEN (1 << 13) #define SYNCIO_TXFRMEN (1 << 14) #endif /* __ASM_HARDWARE_CLPS7111_H */ --- NEW FILE --- /* * linux/include/asm-arm/hardware/ep7211.h * * This file contains the hardware definitions of the EP7211 internal * registers. * * Copyright (C) 2001 Blue Mug, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_HARDWARE_EP7211_H #define __ASM_HARDWARE_EP7211_H #include <asm/hardware/clps7111.h> /* * define EP7211_BASE to be the base address of the region * you want to access. */ #define EP7211_PHYS_BASE (0x80000000) /* * XXX mi...@bl...: need to introduce EP7211 registers (those not * present in 7212) here. */ #endif /* __ASM_HARDWARE_EP7211_H */ --- NEW FILE --- /* * linux/include/asm-arm/hardware/ep7212.h * * This file contains the hardware definitions of the EP7212 internal * registers. * * Copyright (C) 2000 Deep Blue Solutions Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_HARDWARE_EP7212_H #define __ASM_HARDWARE_EP7212_H #include <linux/config.h> /* * define EP7212_BASE to be the base address of the region * you want to access. */ #define EP7212_PHYS_BASE (0x80000000) #ifndef __ASSEMBLY__ #define ep_readl(off) __raw_readl(EP7212_BASE + (off)) #define ep_writel(val,off) __raw_writel(val, EP7212_BASE + (off)) #endif /* * These registers are specific to the EP7212 only */ #define DAIR 0x2000 #define DAIR0 0x2040 #define DAIDR1 0x2080 #define DAIDR2 0x20c0 #define DAISR 0x2100 #define SYSCON3 0x2200 #define INTSR3 0x2240 #define INTMR3 0x2280 #define LEDFLSH 0x22c0 #if defined (CONFIG_ARCH_CDB89712) #define SDCONF 0x2300 #define SDRFPR 0x2340 #endif #define DAIR_DAIEN (1 << 16) #define DAIR_ECS (1 << 17) #define DAIR_LCTM (1 << 19) #define DAIR_LCRM (1 << 20) #define DAIR_RCTM (1 << 21) #define DAIR_RCRM (1 << 22) #define DAIR_LBM (1 << 23) #define DAIDR2_FIFOEN (1 << 15) #define DAIDR2_FIFOLEFT (0x0d << 16) #define DAIDR2_FIFORIGHT (0x11 << 16) #define DAISR_RCTS (1 << 0) #define DAISR_RCRS (1 << 1) #define DAISR_LCTS (1 << 2) #define DAISR_LCRS (1 << 3) #define DAISR_RCTU (1 << 4) #define DAISR_RCRO (1 << 5) #define DAISR_LCTU (1 << 6) #define DAISR_LCRO (1 << 7) #define DAISR_RCNF (1 << 8) #define DAISR_RCNE (1 << 9) #define DAISR_LCNF (1 << 10) #define DAISR_LCNE (1 << 11) #define DAISR_FIFO (1 << 12) #define SYSCON3_ADCCON (1 << 0) #define SYSCON3_DAISEL (1 << 3) #define SYSCON3_ADCCKNSEN (1 << 4) #define SYSCON3_FASTWAKE (1 << 8) #define SYSCON3_DAIEN (1 << 9) #if defined (CONFIG_ARCH_CDB89712) #define SDCONF_ACTIVE (1 << 10) #define SDCONF_CLKCTL (1 << 9) #define SDCONF_WIDTH_4 (0 << 7) #define SDCONF_WIDTH_8 (1 << 7) #define SDCONF_WIDTH_16 (2 << 7) #define SDCONF_WIDTH_32 (3 << 7) #define SDCONF_SIZE_16 (0 << 5) #define SDCONF_SIZE_64 (1 << 5) #define SDCONF_SIZE_128 (2 << 5) #define SDCONF_SIZE_256 (3 << 5) #define SDCONF_CASLAT_2 (2) #define SDCONF_CASLAT_3 (3) #endif #endif /* __ASM_HARDWARE_EP7212_H */ Index: ioc.h =================================================================== RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/hardware/ioc.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- ioc.h 14 Jan 2001 16:58:49 -0000 1.1.1.1 +++ ioc.h 9 Apr 2002 12:33:10 -0000 1.2 @@ -10,58 +10,63 @@ * Use these macros to read/write the IOC. All it does is perform the actual * read/write. */ - -#ifndef IOC_CONTROL +#ifndef __ASMARM_HARDWARE_IOC_H +#define __ASMARM_HARDWARE_IOC_H #ifndef __ASSEMBLY__ -#define __IOC(offset) (IOC_BASE + (offset >> 2)) -#else -#define __IOC(offset) offset + +/* + * We use __raw_base variants here so that we give the compiler the + * chance to keep IOC_BASE in a register. + */ +#define ioc_readb(off) __raw_base_readb(IOC_BASE, (off)) +#define ioc_writeb(val,off) __raw_base_writeb(val, IOC_BASE, (off)) + #endif -#define IOC_CONTROL __IOC(0x00) -#define IOC_KARTTX __IOC(0x04) -#define IOC_KARTRX __IOC(0x04) - -#define IOC_IRQSTATA __IOC(0x10) -#define IOC_IRQREQA __IOC(0x14) -#define IOC_IRQCLRA __IOC(0x14) -#define IOC_IRQMASKA __IOC(0x18) - -#define IOC_IRQSTATB __IOC(0x20) -#define IOC_IRQREQB __IOC(0x24) -#define IOC_IRQMASKB __IOC(0x28) - -#define IOC_FIQSTAT __IOC(0x30) -#define IOC_FIQREQ __IOC(0x34) -#define IOC_FIQMASK __IOC(0x38) - -#define IOC_T0CNTL __IOC(0x40) -#define IOC_T0LTCHL __IOC(0x40) -#define IOC_T0CNTH __IOC(0x44) -#define IOC_T0LTCHH __IOC(0x44) -#define IOC_T0GO __IOC(0x48) -#define IOC_T0LATCH __IOC(0x4c) - -#define IOC_T1CNTL __IOC(0x50) -#define IOC_T1LTCHL __IOC(0x50) -#define IOC_T1CNTH __IOC(0x54) -#define IOC_T1LTCHH __IOC(0x54) -#define IOC_T1GO __IOC(0x58) -#define IOC_T1LATCH __IOC(0x5c) - -#define IOC_T2CNTL __IOC(0x60) -#define IOC_T2LTCHL __IOC(0x60) -#define IOC_T2CNTH __IOC(0x64) -#define IOC_T2LTCHH __IOC(0x64) -#define IOC_T2GO __IOC(0x68) -#define IOC_T2LATCH __IOC(0x6c) - -#define IOC_T3CNTL __IOC(0x70) -#define IOC_T3LTCHL __IOC(0x70) -#define IOC_T3CNTH __IOC(0x74) -#define IOC_T3LTCHH __IOC(0x74) -#define IOC_T3GO __IOC(0x78) -#define IOC_T3LATCH __IOC(0x7c) +#define IOC_CONTROL (0x00) +#define IOC_KARTTX (0x04) +#define IOC_KARTRX (0x04) + +#define IOC_IRQSTATA (0x10) +#define IOC_IRQREQA (0x14) +#define IOC_IRQCLRA (0x14) +#define IOC_IRQMASKA (0x18) + +#define IOC_IRQSTATB (0x20) +#define IOC_IRQREQB (0x24) +#define IOC_IRQMASKB (0x28) + +#define IOC_FIQSTAT (0x30) +#define IOC_FIQREQ (0x34) +#define IOC_FIQMASK (0x38) + +#define IOC_T0CNTL (0x40) +#define IOC_T0LTCHL (0x40) +#define IOC_T0CNTH (0x44) +#define IOC_T0LTCHH (0x44) +#define IOC_T0GO (0x48) +#define IOC_T0LATCH (0x4c) + +#define IOC_T1CNTL (0x50) +#define IOC_T1LTCHL (0x50) +#define IOC_T1CNTH (0x54) +#define IOC_T1LTCHH (0x54) +#define IOC_T1GO (0x58) +#define IOC_T1LATCH (0x5c) + +#define IOC_T2CNTL (0x60) +#define IOC_T2LTCHL (0x60) +#define IOC_T2CNTH (0x64) +#define IOC_T2LTCHH (0x64) +#define IOC_T2GO (0x68) +#define IOC_T2LATCH (0x6c) + +#define IOC_T3CNTL (0x70) +#define IOC_T3LTCHL (0x70) +#define IOC_T3CNTH (0x74) +#define IOC_T3LTCHH (0x74) +#define IOC_T3GO (0x78) +#define IOC_T3LATCH (0x7c) #endif Index: iomd.h =================================================================== RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/hardware/iomd.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- iomd.h 14 Jan 2001 16:58:49 -0000 1.1.1.1 +++ iomd.h 9 Apr 2002 12:33:10 -0000 1.2 @@ -1,5 +1,5 @@ /* - * linux/include/asm-arm/iomd.h + * linux/include/asm-arm/hardware/iomd.h * * Copyright (C) 1999 Russell King * @@ -10,111 +10,121 @@ * This file contains information out the IOMD ASIC used in the * Acorn RiscPC and subsequently integrated into the CLPS7500 chips. */ +#ifndef __ASMARM_HARDWARE_IOMD_H +#define __ASMARM_HARDWARE_IOMD_H + #include <linux/config.h> #ifndef __ASSEMBLY__ -#define __IOMD(offset) (IO_IOMD_BASE + (offset >> 2)) -#else -#define __IOMD(offset) offset + +/* + * We use __raw_base variants here so that we give the compiler the + * chance to keep IOC_BASE in a register. + */ +#define iomd_readb(off) __raw_base_readb(IOMD_BASE, (off)) +#define iomd_readl(off) __raw_base_readl(IOMD_BASE, (off)) +#define iomd_writeb(val,off) __raw_base_writeb(val, IOMD_BASE, (off)) +#define iomd_writel(val,off) __raw_base_writel(val, IOMD_BASE, (off)) + #endif -#define IOMD_CONTROL __IOMD(0x000) -#define IOMD_KARTTX __IOMD(0x004) -#define IOMD_KARTRX __IOMD(0x004) -#define IOMD_KCTRL __IOMD(0x008) +#define IOMD_CONTROL (0x000) +#define IOMD_KARTTX (0x004) +#define IOMD_KARTRX (0x004) +#define IOMD_KCTRL (0x008) #ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_IOLINES __IOMD(0x00C) +#define IOMD_IOLINES (0x00C) #endif -#define IOMD_IRQSTATA __IOMD(0x010) -#define IOMD_IRQREQA __IOMD(0x014) -#define IOMD_IRQCLRA __IOMD(0x014) -#define IOMD_IRQMASKA __IOMD(0x018) +#define IOMD_IRQSTATA (0x010) +#define IOMD_IRQREQA (0x014) +#define IOMD_IRQCLRA (0x014) +#define IOMD_IRQMASKA (0x018) #ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_SUSMODE __IOMD(0x01C) +#define IOMD_SUSMODE (0x01C) #endif -#define IOMD_IRQSTATB __IOMD(0x020) -#define IOMD_IRQREQB __IOMD(0x024) -#define IOMD_IRQMASKB __IOMD(0x028) +#define IOMD_IRQSTATB (0x020) +#define IOMD_IRQREQB (0x024) +#define IOMD_IRQMASKB (0x028) -#define IOMD_FIQSTAT __IOMD(0x030) -#define IOMD_FIQREQ __IOMD(0x034) -#define IOMD_FIQMASK __IOMD(0x038) +#define IOMD_FIQSTAT (0x030) +#define IOMD_FIQREQ (0x034) +#define IOMD_FIQMASK (0x038) #ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_CLKCTL __IOMD(0x03C) +#define IOMD_CLKCTL (0x03C) #endif -#define IOMD_T0CNTL __IOMD(0x040) -#define IOMD_T0LTCHL __IOMD(0x040) -#define IOMD_T0CNTH __IOMD(0x044) -#define IOMD_T0LTCHH __IOMD(0x044) -#define IOMD_T0GO __IOMD(0x048) -#define IOMD_T0LATCH __IOMD(0x04c) +#define IOMD_T0CNTL (0x040) +#define IOMD_T0LTCHL (0x040) +#define IOMD_T0CNTH (0x044) +#define IOMD_T0LTCHH (0x044) +#define IOMD_T0GO (0x048) +#define IOMD_T0LATCH (0x04c) -#define IOMD_T1CNTL __IOMD(0x050) -#define IOMD_T1LTCHL __IOMD(0x050) -#define IOMD_T1CNTH __IOMD(0x054) -#define IOMD_T1LTCHH __IOMD(0x054) -#define IOMD_T1GO __IOMD(0x058) -#define IOMD_T1LATCH __IOMD(0x05c) +#define IOMD_T1CNTL (0x050) +#define IOMD_T1LTCHL (0x050) +#define IOMD_T1CNTH (0x054) +#define IOMD_T1LTCHH (0x054) +#define IOMD_T1GO (0x058) +#define IOMD_T1LATCH (0x05c) #ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_IRQSTATC __IOMD(0x060) -#define IOMD_IRQREQC __IOMD(0x064) -#define IOMD_IRQMASKC __IOMD(0x068) +#define IOMD_IRQSTATC (0x060) +#define IOMD_IRQREQC (0x064) +#define IOMD_IRQMASKC (0x068) -#define IOMD_VIDMUX __IOMD(0x06c) +#define IOMD_VIDMUX (0x06c) -#define IOMD_IRQSTATD __IOMD(0x070) -#define IOMD_IRQREQD __IOMD(0x074) -#define IOMD_IRQMASKD __IOMD(0x078) +#define IOMD_IRQSTATD (0x070) +#define IOMD_IRQREQD (0x074) +#define IOMD_IRQMASKD (0x078) #endif -#define IOMD_ROMCR0 __IOMD(0x080) -#define IOMD_ROMCR1 __IOMD(0x084) +#define IOMD_ROMCR0 (0x080) +#define IOMD_ROMCR1 (0x084) #ifdef CONFIG_ARCH_RPC -#define IOMD_DRAMCR __IOMD(0x088) +#define IOMD_DRAMCR (0x088) #endif -#define IOMD_REFCR __IOMD(0x08C) +#define IOMD_REFCR (0x08C) -#define IOMD_FSIZE __IOMD(0x090) -#define IOMD_ID0 __IOMD(0x094) -#define IOMD_ID1 __IOMD(0x098) -#define IOMD_VERSION __IOMD(0x09C) +#define IOMD_FSIZE (0x090) +#define IOMD_ID0 (0x094) +#define IOMD_ID1 (0x098) +#define IOMD_VERSION (0x09C) #ifdef CONFIG_ARCH_RPC -#define IOMD_MOUSEX __IOMD(0x0A0) -#define IOMD_MOUSEY __IOMD(0x0A4) +#define IOMD_MOUSEX (0x0A0) +#define IOMD_MOUSEY (0x0A4) #endif #ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_MSEDAT __IOMD(0x0A8) -#define IOMD_MSECTL __IOMD(0x0Ac) +#define IOMD_MSEDAT (0x0A8) +#define IOMD_MSECTL (0x0Ac) #endif #ifdef CONFIG_ARCH_RPC -#define IOMD_DMATCR __IOMD(0x0C0) +#define IOMD_DMATCR (0x0C0) #endif -#define IOMD_IOTCR __IOMD(0x0C4) -#define IOMD_ECTCR __IOMD(0x0C8) +#define IOMD_IOTCR (0x0C4) +#define IOMD_ECTCR (0x0C8) #ifdef CONFIG_ARCH_RPC -#define IOMD_DMAEXT __IOMD(0x0CC) +#define IOMD_DMAEXT (0x0CC) #endif #ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_ASTCR __IOMD(0x0CC) -#define IOMD_DRAMCR __IOMD(0x0D0) -#define IOMD_SELFREF __IOMD(0x0D4) -#define IOMD_ATODICR __IOMD(0x0E0) -#define IOMD_ATODSR __IOMD(0x0E4) -#define IOMD_ATODCC __IOMD(0x0E8) -#define IOMD_ATODCNT1 __IOMD(0x0EC) -#define IOMD_ATODCNT2 __IOMD(0x0F0) -#define IOMD_ATODCNT3 __IOMD(0x0F4) -#define IOMD_ATODCNT4 __IOMD(0x0F8) +#define IOMD_ASTCR (0x0CC) +#define IOMD_DRAMCR (0x0D0) +#define IOMD_SELFREF (0x0D4) +#define IOMD_ATODICR (0x0E0) +#define IOMD_ATODSR (0x0E4) +#define IOMD_ATODCC (0x0E8) +#define IOMD_ATODCNT1 (0x0EC) +#define IOMD_ATODCNT2 (0x0F0) +#define IOMD_ATODCNT3 (0x0F4) +#define IOMD_ATODCNT4 (0x0F8) #endif #ifdef CONFIG_ARCH_RPC @@ -123,63 +133,63 @@ #define DMA_EXT_IO2 4 #define DMA_EXT_IO3 8 -#define IOMD_IO0CURA __IOMD(0x100) -#define IOMD_IO0ENDA __IOMD(0x104) -#define IOMD_IO0CURB __IOMD(0x108) -#define IOMD_IO0ENDB __IOMD(0x10C) -#define IOMD_IO0CR __IOMD(0x110) -#define IOMD_IO0ST __IOMD(0x114) - -#define IOMD_IO1CURA __IOMD(0x120) -#define IOMD_IO1ENDA __IOMD(0x124) -#define IOMD_IO1CURB __IOMD(0x128) -#define IOMD_IO1ENDB __IOMD(0x12C) -#define IOMD_IO1CR __IOMD(0x130) -#define IOMD_IO1ST __IOMD(0x134) - -#define IOMD_IO2CURA __IOMD(0x140) -#define IOMD_IO2ENDA __IOMD(0x144) -#define IOMD_IO2CURB __IOMD(0x148) -#define IOMD_IO2ENDB __IOMD(0x14C) -#define IOMD_IO2CR __IOMD(0x150) -#define IOMD_IO2ST __IOMD(0x154) - -#define IOMD_IO3CURA __IOMD(0x160) -#define IOMD_IO3ENDA __IOMD(0x164) -#define IOMD_IO3CURB __IOMD(0x168) -#define IOMD_IO3ENDB __IOMD(0x16C) -#define IOMD_IO3CR __IOMD(0x170) -#define IOMD_IO3ST __IOMD(0x174) -#endif - -#define IOMD_SD0CURA __IOMD(0x180) -#define IOMD_SD0ENDA __IOMD(0x184) -#define IOMD_SD0CURB __IOMD(0x188) -#define IOMD_SD0ENDB __IOMD(0x18C) -#define IOMD_SD0CR __IOMD(0x190) -#define IOMD_SD0ST __IOMD(0x194) - -#ifdef CONFIG_ARCH_RPC -#define IOMD_SD1CURA __IOMD(0x1A0) -#define IOMD_SD1ENDA __IOMD(0x1A4) -#define IOMD_SD1CURB __IOMD(0x1A8) -#define IOMD_SD1ENDB __IOMD(0x1AC) -#define IOMD_SD1CR __IOMD(0x1B0) -#define IOMD_SD1ST __IOMD(0x1B4) -#endif - -#define IOMD_CURSCUR __IOMD(0x1C0) -#define IOMD_CURSINIT __IOMD(0x1C4) - -#define IOMD_VIDCUR __IOMD(0x1D0) -#define IOMD_VIDEND __IOMD(0x1D4) -#define IOMD_VIDSTART __IOMD(0x1D8) -#define IOMD_VIDINIT __IOMD(0x1DC) -#define IOMD_VIDCR __IOMD(0x1E0) - -#define IOMD_DMASTAT __IOMD(0x1F0) -#define IOMD_DMAREQ __IOMD(0x1F4) -#define IOMD_DMAMASK __IOMD(0x1F8) +#define IOMD_IO0CURA (0x100) +#define IOMD_IO0ENDA (0x104) +#define IOMD_IO0CURB (0x108) +#define IOMD_IO0ENDB (0x10C) +#define IOMD_IO0CR (0x110) +#define IOMD_IO0ST (0x114) + +#define IOMD_IO1CURA (0x120) +#define IOMD_IO1ENDA (0x124) +#define IOMD_IO1CURB (0x128) +#define IOMD_IO1ENDB (0x12C) +#define IOMD_IO1CR (0x130) +#define IOMD_IO1ST (0x134) + +#define IOMD_IO2CURA (0x140) +#define IOMD_IO2ENDA (0x144) +#define IOMD_IO2CURB (0x148) +#define IOMD_IO2ENDB (0x14C) +#define IOMD_IO2CR (0x150) +#define IOMD_IO2ST (0x154) + +#define IOMD_IO3CURA (0x160) +#define IOMD_IO3ENDA (0x164) +#define IOMD_IO3CURB (0x168) +#define IOMD_IO3ENDB (0x16C) +#define IOMD_IO3CR (0x170) +#define IOMD_IO3ST (0x174) +#endif + +#define IOMD_SD0CURA (0x180) +#define IOMD_SD0ENDA (0x184) +#define IOMD_SD0CURB (0x188) +#define IOMD_SD0ENDB (0x18C) +#define IOMD_SD0CR (0x190) +#define IOMD_SD0ST (0x194) + +#ifdef CONFIG_ARCH_RPC +#define IOMD_SD1CURA (0x1A0) +#define IOMD_SD1ENDA (0x1A4) +#define IOMD_SD1CURB (0x1A8) +#define IOMD_SD1ENDB (0x1AC) +#define IOMD_SD1CR (0x1B0) +#define IOMD_SD1ST (0x1B4) +#endif + +#define IOMD_CURSCUR (0x1C0) +#define IOMD_CURSINIT (0x1C4) + +#define IOMD_VIDCUR (0x1D0) +#define IOMD_VIDEND (0x1D4) +#define IOMD_VIDSTART (0x1D8) +#define IOMD_VIDINIT (0x1DC) +#define IOMD_VIDCR (0x1E0) + +#define IOMD_DMASTAT (0x1F0) +#define IOMD_DMAREQ (0x1F4) +#define IOMD_DMAMASK (0x1F8) #define DMA_END_S (1 << 31) #define DMA_END_L (1 << 30) @@ -192,39 +202,6 @@ #define DMA_ST_INT 2 #define DMA_ST_AB 1 -#ifndef IOC_CONTROL -/* - * IOC compatability - */ -#define IOC_CONTROL IOMD_CONTROL -#define IOC_IRQSTATA IOMD_IRQSTATA -#define IOC_IRQREQA IOMD_IRQREQA -#define IOC_IRQCLRA IOMD_IRQCLRA -#define IOC_IRQMASKA IOMD_IRQMASKA - -#define IOC_IRQSTATB IOMD_IRQSTATB -#define IOC_IRQREQB IOMD_IRQREQB -#define IOC_IRQMASKB IOMD_IRQMASKB - -#define IOC_FIQSTAT IOMD_FIQSTAT -#define IOC_FIQREQ IOMD_FIQREQ -#define IOC_FIQMASK IOMD_FIQMASK - -#define IOC_T0CNTL IOMD_T0CNTL -#define IOC_T0LTCHL IOMD_T0LTCHL -#define IOC_T0CNTH IOMD_T0CNTH -#define IOC_T0LTCHH IOMD_T0LTCHH -#define IOC_T0GO IOMD_T0GO -#define IOC_T0LATCH IOMD_T0LATCH - -#define IOC_T1CNTL IOMD_T1CNTL -#define IOC_T1LTCHL IOMD_T1LTCHL -#define IOC_T1CNTH IOMD_T1CNTH -#define IOC_T1LTCHH IOMD_T1LTCHH -#define IOC_T1GO IOMD_T1GO -#define IOC_T1LATCH IOMD_T1LATCH -#endif - /* * DMA (MEMC) compatability */ @@ -247,3 +224,4 @@ } while (0) #endif +#endif Index: pci_v3.h =================================================================== RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/hardware/pci_v3.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- pci_v3.h 14 Jan 2001 16:58:50 -0000 1.1.1.1 +++ pci_v3.h 9 Apr 2002 12:33:10 -0000 1.2 @@ -4,7 +4,7 @@ * Internal header file PCI V3 chip * * Copyright (C) ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd. + * Copyright (C) 2000-2001 Deep Blue Solutions Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -88,61 +88,99 @@ /* PCI COMMAND REGISTER bits */ -#define V3_COMMAND_M_FBB_EN BIT9 -#define V3_COMMAND_M_SERR_EN BIT8 -#define V3_COMMAND_M_PAR_EN BIT6 -#define V3_COMMAND_M_MASTER_EN BIT2 -#define V3_COMMAND_M_MEM_EN BIT1 -#define V3_COMMAND_M_IO_EN BIT0 +#define V3_COMMAND_M_FBB_EN (1 << 9) +#define V3_COMMAND_M_SERR_EN (1 << 8) +#define V3_COMMAND_M_PAR_EN (1 << 6) +#define V3_COMMAND_M_MASTER_EN (1 << 2) +#define V3_COMMAND_M_MEM_EN (1 << 1) +#define V3_COMMAND_M_IO_EN (1 << 0) /* SYSTEM REGISTER bits */ -#define V3_SYSTEM_M_RST_OUT BIT15 -#define V3_SYSTEM_M_LOCK BIT14 +#define V3_SYSTEM_M_RST_OUT (1 << 15) +#define V3_SYSTEM_M_LOCK (1 << 14) /* PCI_CFG bits */ -#define V3_PCI_CFG_M_RETRY_EN BIT10 -#define V3_PCI_CFG_M_AD_LOW1 BIT9 -#define V3_PCI_CFG_M_AD_LOW0 BIT8 +#define V3_PCI_CFG_M_I2O_EN (1 << 15) +#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) +#define V3_PCI_CFG_M_IO_DIS (1 << 13) +#define V3_PCI_CFG_M_EN3V (1 << 12) +#define V3_PCI_CFG_M_RETRY_EN (1 << 10) +#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) +#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) /* PCI_BASE register bits (PCI -> Local Bus) */ #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 -#define V3_PCI_BASE_M_PREFETCH BIT3 -#define V3_PCI_BASE_M_TYPE BIT2+BIT1 -#define V3_PCI_BASE_M_IO BIT0 +#define V3_PCI_BASE_M_PREFETCH (1 << 3) +#define V3_PCI_BASE_M_TYPE (3 << 1) +#define V3_PCI_BASE_M_IO (1 << 0) /* PCI MAP register bits (PCI -> Local bus) */ #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 -#define V3_PCI_MAP_M_RD_POST_INH BIT15 -#define V3_PCI_MAP_M_ROM_SIZE BIT11+BIT10 -#define V3_PCI_MAP_M_SWAP BIT9+BIT8 +#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) +#define V3_PCI_MAP_M_ROM_SIZE (3 << 10) +#define V3_PCI_MAP_M_SWAP (3 << 8) #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 -#define V3_PCI_MAP_M_REG_EN BIT1 -#define V3_PCI_MAP_M_ENABLE BIT0 +#define V3_PCI_MAP_M_REG_EN (1 << 1) +#define V3_PCI_MAP_M_ENABLE (1 << 0) -/* 9 => 512M window size +/* + * LB_BASE0,1 register bits (Local bus -> PCI) */ -#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 -/* A => 1024M window size - */ -#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 +#define V3_LB_BASE_ADR_BASE 0xfff00000 +#define V3_LB_BASE_SWAP (3 << 8) +#define V3_LB_BASE_ADR_SIZE (15 << 4) +#define V3_LB_BASE_PREFETCH (1 << 3) +#define V3_LB_BASE_ENABLE (1 << 0) + +#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) +#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) +#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) +#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) +#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) +#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) +#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) +#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) +#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) +#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) +#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) +#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) + +#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) + +/* + * LB_MAP0,1 register bits (Local bus -> PCI) + */ +#define V3_LB_MAP_MAP_ADR 0xfff0 +#define V3_LB_MAP_TYPE (7 << 1) +#define V3_LB_MAP_AD_LOW_EN (1 << 0) + +#define V3_LB_MAP_TYPE_IACK (0 << 1) +#define V3_LB_MAP_TYPE_IO (1 << 1) +#define V3_LB_MAP_TYPE_MEM (3 << 1) +#define V3_LB_MAP_TYPE_CONFIG (5 << 1) +#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) + +#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) + +/* + * LB_BASE2 register bits (Local bus -> PCI IO) + */ +#define V3_LB_BASE2_ADR_BASE 0xff00 +#define V3_LB_BASE2_SWAP (3 << 6) +#define V3_LB_BASE2_ENABLE (1 << 0) -/* LB_BASE register bits (Local bus -> PCI) - */ -#define V3_LB_BASE_M_MAP_ADR 0xFFF00000 -#define V3_LB_BASE_M_SWAP BIT9+BIT8 -#define V3_LB_BASE_M_ADR_SIZE 0x000000F0 -#define V3_LB_BASE_M_PREFETCH BIT3 -#define V3_LB_BASE_M_ENABLE BIT0 +#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) -/* LB_MAP register bits (Local bus -> PCI) +/* + * LB_MAP2 register bits (Local bus -> PCI IO) */ -#define V3_LB_MAP_M_MAP_ADR 0xFFF0 -#define V3_LB_MAP_M_TYPE 0x000E -#define V3_LB_MAP_M_AD_LOW_EN BIT0 +#define V3_LB_MAP2_MAP_ADR 0xff00 + +#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) #endif Index: serial_amba.h =================================================================== RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/hardware/serial_amba.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- serial_amba.h 14 Jan 2001 16:58:51 -0000 1.1.1.1 +++ serial_amba.h 9 Apr 2002 12:33:10 -0000 1.2 @@ -88,4 +88,7 @@ #define ARM_BAUD_2400 383 #define ARM_BAUD_1200 767 +#define AMBA_UARTRSR_ANY (AMBA_UARTRSR_OE|AMBA_UARTRSR_BE|AMBA_UARTRSR_PE|AMBA_UARTRSR_FE) +#define AMBA_UARTFR_MODEM_ANY (AMBA_UARTFR_DCD|AMBA_UARTFR_DSR|AMBA_UARTFR_CTS) + #endif |
