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[LV-kern-commit] CVS: kernel-2.4/include/asm-mips64/mips-boards atlas.h,NONE,1.1 atlasint.h,NONE,1.1 generic.h,NONE,1.1 gt64120.h,NONE,1.1 io.h,NONE,1.1 malta.h,NONE,1.1 maltaint.h,NONE,1.1 piix4.h,NONE,1.1 prom.h,NONE,1.1 saa9730_uart.h,NONE,1.1
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips64/mips-boards
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-mips64/mips-boards
Added Files:
atlas.h atlasint.h generic.h gt64120.h io.h malta.h maltaint.h
piix4.h prom.h saa9730_uart.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines of the Atlas board specific address-MAP, registers, etc.
*
*/
#ifndef _MIPS_ATLAS_H
#define _MIPS_ATLAS_H
#include <asm/addrspace.h>
/*
* Atlas RTC-device indirect register access.
*/
#define ATLAS_RTC_ADR_REG (KSEG1ADDR(0x1f000800))
#define ATLAS_RTC_DAT_REG (KSEG1ADDR(0x1f000808))
/*
* Atlas interrupt controller register base.
*/
#define ATLAS_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
/*
* Atlas UART register base.
*/
#define ATLAS_UART_REGS_BASE (0x1f000900)
#define ATLAS_BASE_BAUD ( 3686400 / 16 )
/*
* Atlas PSU standby register.
*/
#define ATLAS_PSUSTBY_REG (KSEG1ADDR(0x1f000600))
#define ATLAS_GOSTBY 0x4d
/*
* We make a universal assumption about the way the bootloader (YAMON)
* have located the Philips SAA9730 chip.
* This is not ideal, but is needed for setting up remote debugging as
* soon as possible.
*/
#define ATLAS_SAA9730_REG (KSEG1ADDR(0x08800000))
#endif /* !(_MIPS_ATLAS_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines for the Atlas interrupt controller.
*
*/
#ifndef _MIPS_ATLASINT_H
#define _MIPS_ATLASINT_H
/* Number of IRQ supported on hw interrupt 0. */
#define ATLASINT_UART 0
#define ATLASINT_END 32
/*
* Atlas registers are memory mapped on 64-bit aligned boundaries and
* only word access are allowed.
*/
struct atlas_ictrl_regs {
volatile unsigned long intraw;
long dummy1;
volatile unsigned long intseten;
long dummy2;
volatile unsigned long intrsten;
long dummy3;
volatile unsigned long intenable;
long dummy4;
volatile unsigned long intstatus;
long dummy5;
};
extern void atlasint_init(void);
#endif /* !(_MIPS_ATLASINT_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines of the MIPS boards specific address-MAP, registers, etc.
*
*/
#ifndef _MIPS_GENERIC_H
#define _MIPS_GENERIC_H
#include <asm/addrspace.h>
#include <asm/byteorder.h>
/*
* Display register base.
*/
#define ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1f000410))
#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f000418))
/*
* Yamon Prom print address.
*/
#define YAMON_PROM_PRINT_ADDR (KSEG1ADDR(0x1fc00504))
/*
* Reset register.
*/
#define SOFTRES_REG (KSEG1ADDR(0x1f000500))
#define GORESET 0x42
/*
* Galileo GT64120 system controller register base.
*/
#define MIPS_GT_BASE (KSEG1ADDR(0x1be00000))
/*
* Because of the way the internal register works on the Galileo chip,
* we need to swap the bytes when running bigendian.
*/
#define GT_WRITE(ofs, data) \
*(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data)
#define GT_READ(ofs, data) \
data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs))
#define GT_PCI_WRITE(ofs, data) \
*(volatile u32 *)(MIPS_GT_BASE+ofs) = data
#define GT_PCI_READ(ofs, data) \
data = *(volatile u32 *)(MIPS_GT_BASE+ofs)
#endif /* !(_MIPS_GENERIC_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Register definitions for Galileo 64120 system controller.
*
*/
#ifndef GT64120_H
#define GT64120_H
#define MSK(n) ((1 << (n)) - 1)
/************************************************************************
* Register offset addresses
************************************************************************/
#define GT_CPU_OFS 0x000
#define GT_CPU_OFS 0x000
#define GT_SCS10LD_OFS 0x008
#define GT_SCS10HD_OFS 0x010
#define GT_SCS32LD_OFS 0x018
#define GT_SCS32HD_OFS 0x020
#define GT_CS20LD_OFS 0x028
#define GT_CS20HD_OFS 0x030
#define GT_CS3BOOTLD_OFS 0x038
#define GT_CS3BOOTHD_OFS 0x040
#define GT_PCI0IOLD_OFS 0x048
#define GT_PCI0IOHD_OFS 0x050
#define GT_PCI0M0LD_OFS 0x058
#define GT_PCI0M0HD_OFS 0x060
#define GT_ISD_OFS 0x068
#define GT_PCI0M1LD_OFS 0x080
#define GT_PCI0M1HD_OFS 0x088
#define GT_PCI1IOLD_OFS 0x090
#define GT_PCI1IOHD_OFS 0x098
#define GT_PCI1M0LD_OFS 0x0a0
#define GT_PCI1M0HD_OFS 0x0a8
#define GT_PCI1M1LD_OFS 0x0b0
#define GT_PCI1M1HD_OFS 0x0b8
#define GT_SCS0LD_OFS 0x400
#define GT_SCS0HD_OFS 0x404
#define GT_SCS1LD_OFS 0x408
#define GT_SCS1HD_OFS 0x40c
#define GT_SCS2LD_OFS 0x410
#define GT_SCS2HD_OFS 0x414
#define GT_SCS3LD_OFS 0x418
#define GT_SCS3HD_OFS 0x41c
#define GT_CS0LD_OFS 0x420
#define GT_CS0HD_OFS 0x424
#define GT_CS1LD_OFS 0x428
#define GT_CS1HD_OFS 0x42c
#define GT_CS2LD_OFS 0x430
#define GT_CS2HD_OFS 0x434
#define GT_CS3LD_OFS 0x438
#define GT_CS3HD_OFS 0x43c
#define GT_BOOTLD_OFS 0x440
#define GT_BOOTHD_OFS 0x444
#define GT_SDRAM_B0_OFS 0x44c
#define GT_SDRAM_CFG_OFS 0x448
#define GT_SDRAM_B2_OFS 0x454
#define GT_SDRAM_OPMODE_OFS 0x474
#define GT_SDRAM_BM_OFS 0x478
#define GT_SDRAM_ADDRDECODE_OFS 0x47c
#define GT_PCI0_CMD_OFS 0xc00
#define GT_PCI0_TOR_OFS 0xc04
#define GT_PCI0_BS_SCS10_OFS 0xc08
#define GT_PCI0_BS_SCS32_OFS 0xc0c
#define GT_INTRCAUSE_OFS 0xc18
#define GT_PCI0_IACK_OFS 0xc34
#define GT_PCI0_BARE_OFS 0xc3c
#define GT_PCI0_CFGADDR_OFS 0xcf8
#define GT_PCI0_CFGDATA_OFS 0xcfc
/************************************************************************
* Register encodings
************************************************************************/
#define GT_CPU_ENDIAN_SHF 12
#define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF)
#define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK
#define GT_CPU_WR_SHF 16
#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF)
#define GT_CPU_WR_BIT GT_CPU_WR_MSK
#define GT_CPU_WR_DXDXDXDX 0
#define GT_CPU_WR_DDDD 1
#define GT_CFGADDR_CFGEN_SHF 31
#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF)
#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK
#define GT_CFGADDR_BUSNUM_SHF 16
#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF)
#define GT_CFGADDR_DEVNUM_SHF 11
#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF)
#define GT_CFGADDR_FUNCNUM_SHF 8
#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
#define GT_CFGADDR_REGNUM_SHF 2
#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF)
#define GT_SDRAM_BM_ORDER_SHF 2
#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF)
#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK
#define GT_SDRAM_BM_ORDER_SUB 1
#define GT_SDRAM_BM_ORDER_LIN 0
#define GT_SDRAM_BM_RSVD_ALL1 0xFFB
#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0
#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
#define GT_SDRAM_ADDRDECODE_ADDR_0 0
#define GT_SDRAM_ADDRDECODE_ADDR_1 1
#define GT_SDRAM_ADDRDECODE_ADDR_2 2
#define GT_SDRAM_ADDRDECODE_ADDR_3 3
#define GT_SDRAM_ADDRDECODE_ADDR_4 4
#define GT_SDRAM_ADDRDECODE_ADDR_5 5
#define GT_SDRAM_ADDRDECODE_ADDR_6 6
#define GT_SDRAM_ADDRDECODE_ADDR_7 7
#define GT_SDRAM_B0_CASLAT_SHF 0
#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF)
#define GT_SDRAM_B0_CASLAT_2 1
#define GT_SDRAM_B0_CASLAT_3 2
#define GT_SDRAM_B0_FTDIS_SHF 2
#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK
#define GT_SDRAM_B0_SRASPRCHG_SHF 3
#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK
#define GT_SDRAM_B0_SRASPRCHG_2 0
#define GT_SDRAM_B0_SRASPRCHG_3 1
#define GT_SDRAM_B0_B0COMPAB_SHF 4
#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK
#define GT_SDRAM_B0_64BITINT_SHF 5
#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK
#define GT_SDRAM_B0_64BITINT_2 0
#define GT_SDRAM_B0_64BITINT_4 1
#define GT_SDRAM_B0_BW_SHF 6
#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF)
#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK
#define GT_SDRAM_B0_BW_32 0
#define GT_SDRAM_B0_BW_64 1
#define GT_SDRAM_B0_BLODD_SHF 7
#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF)
#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK
#define GT_SDRAM_B0_PAR_SHF 8
#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF)
#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK
#define GT_SDRAM_B0_BYPASS_SHF 9
#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK
#define GT_SDRAM_B0_SRAS2SCAS_SHF 10
#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK
#define GT_SDRAM_B0_SRAS2SCAS_2 0
#define GT_SDRAM_B0_SRAS2SCAS_3 1
#define GT_SDRAM_B0_SIZE_SHF 11
#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF)
#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK
#define GT_SDRAM_B0_SIZE_16M 0
#define GT_SDRAM_B0_SIZE_64M 1
#define GT_SDRAM_B0_EXTPAR_SHF 12
#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK
#define GT_SDRAM_B0_BLEN_SHF 13
#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF)
#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK
#define GT_SDRAM_B0_BLEN_8 0
#define GT_SDRAM_B0_BLEN_4 1
#define GT_SDRAM_CFG_REFINT_SHF 0
#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14
#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK
#define GT_SDRAM_CFG_RMW_SHF 15
#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF)
#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK
#define GT_SDRAM_CFG_NONSTAGREF_SHF 16
#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK
#define GT_SDRAM_CFG_DUPCNTL_SHF 19
#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK
#define GT_SDRAM_CFG_DUPBA_SHF 20
#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK
#define GT_SDRAM_CFG_DUPEOT0_SHF 21
#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK
#define GT_SDRAM_CFG_DUPEOT1_SHF 22
#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK
#define GT_SDRAM_OPMODE_OP_SHF 0
#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
#define GT_SDRAM_OPMODE_OP_NORMAL 0
#define GT_SDRAM_OPMODE_OP_NOP 1
#define GT_SDRAM_OPMODE_OP_PRCHG 2
#define GT_SDRAM_OPMODE_OP_MODE 3
#define GT_SDRAM_OPMODE_OP_CBR 4
#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
#define GT_PCI0_BARE_SWSCS32DIS_SHF 1
#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK
#define GT_PCI0_BARE_SWSCS10DIS_SHF 2
#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK
#define GT_PCI0_BARE_INTIODIS_SHF 3
#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK
#define GT_PCI0_BARE_INTMEMDIS_SHF 4
#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK
#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5
#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK
#define GT_PCI0_BARE_CS20DIS_SHF 6
#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK
#define GT_PCI0_BARE_SCS32DIS_SHF 7
#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK
#define GT_PCI0_BARE_SCS10DIS_SHF 8
#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK
#define GT_INTRCAUSE_MASABORT0_SHF 18
#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK
#define GT_INTRCAUSE_TARABORT0_SHF 19
#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK
#define GT_PCI0_CFGADDR_REGNUM_SHF 2
#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8
#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
#define GT_PCI0_CFGADDR_DEVNUM_SHF 11
#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
#define GT_PCI0_CFGADDR_BUSNUM_SHF 16
#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31
#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK
#define GT_PCI0_CMD_MBYTESWAP_SHF 0
#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK
#define GT_PCI0_CMD_MWORDSWAP_SHF 10
#define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
#define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK
#define GT_PCI0_CMD_SBYTESWAP_SHF 16
#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK
#define GT_PCI0_CMD_SWORDSWAP_SHF 11
#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK
/************************************************************************
* Misc
************************************************************************/
#define GT_DEF_BASE 0x14000000
#define GT_DEF_PCI0_MEM0_BASE 0x12000000
#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */
#define GT_LATTIM_MIN 6 /* Minimum lat */
#endif /* #ifndef GT64120_H */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines of the MIPS boards specific IO address-MAP.
*
*/
#ifndef _ASM_MIPS_BOARDS_IO_H
#define _ASM_MIPS_BOARDS_IO_H
#include <asm/addrspace.h>
#define IO_SPACE_BASE K1BASE
#define IO_SPACE_LIMIT 0xffffffff
#endif /* _ASM_MIPS_BOARDS_IO_H */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines of the Malta board specific address-MAP, registers, etc.
*
*/
#ifndef _MIPS_MALTA_H
#define _MIPS_MALTA_H
#include <asm/addrspace.h>
#include <asm/io.h>
/*
* Malta I/O ports base address.
*/
#define MALTA_PORT_BASE (KSEG1ADDR(0x18000000))
/*
* Malta RTC-device indirect register access.
*/
#define MALTA_RTC_ADR_REG 0x70
#define MALTA_RTC_DAT_REG 0x71
/*
* Malta SMSC FDC37M817 Super I/O Controller register.
*/
#define SMSC_CONFIG_REG 0x3f0
#define SMSC_DATA_REG 0x3f1
#define SMSC_CONFIG_DEVNUM 0x7
#define SMSC_CONFIG_ACTIVATE 0x30
#define SMSC_CONFIG_ENTER 0x55
#define SMSC_CONFIG_EXIT 0xaa
#define SMSC_CONFIG_DEVNUM_FLOPPY 0
#define SMSC_CONFIG_ACTIVATE_ENABLE 1
#define SMSC_WRITE(x,a) outb(x,a)
#endif /* !(_MIPS_MALTA_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines for the Malta interrupt controller.
*
*/
#ifndef _MIPS_MALTAINT_H
#define _MIPS_MALTAINT_H
/* Number of IRQ supported on hw interrupt 0. */
#define MALTAINT_END 16
extern void maltaint_init(void);
#endif /* !(_MIPS_MALTAINT_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Register definitions for Intel PIIX4 South Bridge Device.
*
*/
#ifndef PIIX4_H
#define PIIX4_H
/************************************************************************
* IO register offsets
************************************************************************/
#define PIIX4_ICTLR1_ICW1 0x20
#define PIIX4_ICTLR1_ICW2 0x21
#define PIIX4_ICTLR1_ICW3 0x21
#define PIIX4_ICTLR1_ICW4 0x21
#define PIIX4_ICTLR2_ICW1 0xa0
#define PIIX4_ICTLR2_ICW2 0xa1
#define PIIX4_ICTLR2_ICW3 0xa1
#define PIIX4_ICTLR2_ICW4 0xa1
#define PIIX4_ICTLR1_OCW1 0x21
#define PIIX4_ICTLR1_OCW2 0x20
#define PIIX4_ICTLR1_OCW3 0x20
#define PIIX4_ICTLR1_OCW4 0x20
#define PIIX4_ICTLR2_OCW1 0xa1
#define PIIX4_ICTLR2_OCW2 0xa0
#define PIIX4_ICTLR2_OCW3 0xa0
#define PIIX4_ICTLR2_OCW4 0xa0
/************************************************************************
* Register encodings.
************************************************************************/
#define PIIX4_OCW2_NSEOI (0x1 << 5)
#define PIIX4_OCW2_SEOI (0x3 << 5)
#define PIIX4_OCW2_RNSEOI (0x5 << 5)
#define PIIX4_OCW2_RAEOIS (0x4 << 5)
#define PIIX4_OCW2_RAEOIC (0x0 << 5)
#define PIIX4_OCW2_RSEOI (0x7 << 5)
#define PIIX4_OCW2_SP (0x6 << 5)
#define PIIX4_OCW2_NOP (0x2 << 5)
#define PIIX4_OCW2_SEL (0x0 << 3)
#define PIIX4_OCW2_ILS_0 0
#define PIIX4_OCW2_ILS_1 1
#define PIIX4_OCW2_ILS_2 2
#define PIIX4_OCW2_ILS_3 3
#define PIIX4_OCW2_ILS_4 4
#define PIIX4_OCW2_ILS_5 5
#define PIIX4_OCW2_ILS_6 6
#define PIIX4_OCW2_ILS_7 7
#define PIIX4_OCW2_ILS_8 0
#define PIIX4_OCW2_ILS_9 1
#define PIIX4_OCW2_ILS_10 2
#define PIIX4_OCW2_ILS_11 3
#define PIIX4_OCW2_ILS_12 4
#define PIIX4_OCW2_ILS_13 5
#define PIIX4_OCW2_ILS_14 6
#define PIIX4_OCW2_ILS_15 7
#define PIIX4_OCW3_SEL (0x1 << 3)
#define PIIX4_OCW3_IRR 0x2
#define PIIX4_OCW3_ISR 0x3
#endif /* !(PIIX4_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* MIPS boards bootprom interface for the Linux kernel.
*
*/
#ifndef _MIPS_PROM_H
#define _MIPS_PROM_H
extern char *prom_getcmdline(void);
extern char *prom_getenv(char *name);
extern void setup_prom_printf(int tty_no);
extern void prom_printf(char *fmt, ...);
extern void prom_init_cmdline(void);
extern void prom_meminit(void);
extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
extern void prom_free_prom_memory (void);
extern void mips_display_message(const char *str);
extern void mips_display_word(unsigned int num);
extern int get_ethernet_addr(char *ethernet_addr);
/* Memory descriptor management. */
#define PROM_MAX_PMEMBLOCKS 32
struct prom_pmemblock {
unsigned int base; /* Phys addr. */
unsigned int size; /* In bytes. */
unsigned int type; /* free or prom memory */
};
#endif /* !(_MIPS_PROM_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Register definitions for the UART part of the Philips SAA9730 chip.
*
*/
#ifndef SAA9730_UART_H
#define SAA9730_UART_H
/* The SAA9730 UART register map, as seen via the PCI bus */
#define SAA9730_UART_REGS_ADDR 0x21800
struct uart_saa9730_regmap {
volatile unsigned char Thr_Rbr;
volatile unsigned char Ier;
volatile unsigned char Iir_Fcr;
volatile unsigned char Lcr;
volatile unsigned char Mcr;
volatile unsigned char Lsr;
volatile unsigned char Msr;
volatile unsigned char Scr;
volatile unsigned char BaudDivLsb;
volatile unsigned char BaudDivMsb;
volatile unsigned char Junk0;
volatile unsigned char Junk1;
volatile unsigned int Config; /* 0x2180c */
volatile unsigned int TxStart; /* 0x21810 */
volatile unsigned int TxLength; /* 0x21814 */
volatile unsigned int TxCounter; /* 0x21818 */
volatile unsigned int RxStart; /* 0x2181c */
volatile unsigned int RxLength; /* 0x21820 */
volatile unsigned int RxCounter; /* 0x21824 */
};
typedef volatile struct uart_saa9730_regmap t_uart_saa9730_regmap;
/*
* Only a subset of the UART control bits are defined here,
* enough to make the serial debug port work.
*/
#define SAA9730_LCR_DATA8 0x03
#define SAA9730_MCR_DTR 0x01
#define SAA9730_MCR_RTS 0x02
#define SAA9730_LSR_DR 0x01
#define SAA9730_LSR_THRE 0x20
#endif /* !(SAA9730_UART_H) */
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