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[LV-kern-commit] CVS: kernel-2.4/include/asm-mips/mips-boards atlas.h,NONE,1.1 atlasint.h,NONE,1.1 generic.h,NONE,1.1 malta.h,NONE,1.1 maltaint.h,NONE,1.1 piix4.h,NONE,1.1 prom.h,NONE,1.1 saa9730_uart.h,NONE,1.1
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/mips-boards
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-mips/mips-boards
Added Files:
atlas.h atlasint.h generic.h malta.h maltaint.h piix4.h prom.h
saa9730_uart.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines of the Atlas board specific address-MAP, registers, etc.
*
*/
#ifndef _MIPS_ATLAS_H
#define _MIPS_ATLAS_H
#include <asm/addrspace.h>
/*
* Atlas RTC-device indirect register access.
*/
#define ATLAS_RTC_ADR_REG (KSEG1ADDR(0x1f000800))
#define ATLAS_RTC_DAT_REG (KSEG1ADDR(0x1f000808))
/*
* Atlas interrupt controller register base.
*/
#define ATLAS_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
/*
* Atlas UART register base.
*/
#define ATLAS_UART_REGS_BASE (0x1f000900)
#define ATLAS_BASE_BAUD ( 3686400 / 16 )
/*
* Atlas PSU standby register.
*/
#define ATLAS_PSUSTBY_REG (KSEG1ADDR(0x1f000600))
#define ATLAS_GOSTBY 0x4d
/*
* We make a universal assumption about the way the bootloader (YAMON)
* have located the Philips SAA9730 chip.
* This is not ideal, but is needed for setting up remote debugging as
* soon as possible.
*/
#define ATLAS_SAA9730_REG (KSEG1ADDR(0x08800000))
#endif /* !(_MIPS_ATLAS_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines for the Atlas interrupt controller.
*
*/
#ifndef _MIPS_ATLASINT_H
#define _MIPS_ATLASINT_H
/* Number of IRQ supported on hw interrupt 0. */
#define ATLASINT_UART 0
#define ATLASINT_END 32
/*
* Atlas registers are memory mapped on 64-bit aligned boundaries and
* only word access are allowed.
*/
struct atlas_ictrl_regs {
volatile unsigned long intraw;
long dummy1;
volatile unsigned long intseten;
long dummy2;
volatile unsigned long intrsten;
long dummy3;
volatile unsigned long intenable;
long dummy4;
volatile unsigned long intstatus;
long dummy5;
};
extern void atlasint_init(void);
#endif /* !(_MIPS_ATLASINT_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines of the MIPS boards specific address-MAP, registers, etc.
*
*/
#ifndef _MIPS_GENERIC_H
#define _MIPS_GENERIC_H
#include <asm/addrspace.h>
#include <asm/byteorder.h>
/*
* Display register base.
*/
#define ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1f000410))
#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f000418))
/*
* Yamon Prom print address.
*/
#define YAMON_PROM_PRINT_ADDR (KSEG1ADDR(0x1fc00504))
/*
* Reset register.
*/
#define SOFTRES_REG (KSEG1ADDR(0x1f000500))
#define GORESET 0x42
/*
* Galileo GT64120 system controller register base.
*/
#define MIPS_GT_BASE (KSEG1ADDR(0x1be00000))
/*
* Because of the way the internal register works on the Galileo chip,
* we need to swap the bytes when running bigendian.
*/
#define GT_WRITE(ofs, data) \
*(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data)
#define GT_READ(ofs, data) \
data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs))
#define GT_PCI_WRITE(ofs, data) \
*(volatile u32 *)(MIPS_GT_BASE+ofs) = data
#define GT_PCI_READ(ofs, data) \
data = *(volatile u32 *)(MIPS_GT_BASE+ofs)
#endif /* !(_MIPS_GENERIC_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines of the Malta board specific address-MAP, registers, etc.
*
*/
#ifndef _MIPS_MALTA_H
#define _MIPS_MALTA_H
#include <asm/addrspace.h>
#include <asm/io.h>
/*
* Malta I/O ports base address.
*/
#define MALTA_PORT_BASE (KSEG1ADDR(0x18000000))
/*
* Malta RTC-device indirect register access.
*/
#define MALTA_RTC_ADR_REG 0x70
#define MALTA_RTC_DAT_REG 0x71
/*
* Malta SMSC FDC37M817 Super I/O Controller register.
*/
#define SMSC_CONFIG_REG 0x3f0
#define SMSC_DATA_REG 0x3f1
#define SMSC_CONFIG_DEVNUM 0x7
#define SMSC_CONFIG_ACTIVATE 0x30
#define SMSC_CONFIG_ENTER 0x55
#define SMSC_CONFIG_EXIT 0xaa
#define SMSC_CONFIG_DEVNUM_FLOPPY 0
#define SMSC_CONFIG_ACTIVATE_ENABLE 1
#define SMSC_WRITE(x,a) outb(x,a)
#endif /* !(_MIPS_MALTA_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines for the Malta interrupt controller.
*
*/
#ifndef _MIPS_MALTAINT_H
#define _MIPS_MALTAINT_H
/* Number of IRQ supported on hw interrupt 0. */
#define MALTAINT_END 16
extern void maltaint_init(void);
#endif /* !(_MIPS_MALTAINT_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Register definitions for Intel PIIX4 South Bridge Device.
*
*/
#ifndef PIIX4_H
#define PIIX4_H
/************************************************************************
* IO register offsets
************************************************************************/
#define PIIX4_ICTLR1_ICW1 0x20
#define PIIX4_ICTLR1_ICW2 0x21
#define PIIX4_ICTLR1_ICW3 0x21
#define PIIX4_ICTLR1_ICW4 0x21
#define PIIX4_ICTLR2_ICW1 0xa0
#define PIIX4_ICTLR2_ICW2 0xa1
#define PIIX4_ICTLR2_ICW3 0xa1
#define PIIX4_ICTLR2_ICW4 0xa1
#define PIIX4_ICTLR1_OCW1 0x21
#define PIIX4_ICTLR1_OCW2 0x20
#define PIIX4_ICTLR1_OCW3 0x20
#define PIIX4_ICTLR1_OCW4 0x20
#define PIIX4_ICTLR2_OCW1 0xa1
#define PIIX4_ICTLR2_OCW2 0xa0
#define PIIX4_ICTLR2_OCW3 0xa0
#define PIIX4_ICTLR2_OCW4 0xa0
/************************************************************************
* Register encodings.
************************************************************************/
#define PIIX4_OCW2_NSEOI (0x1 << 5)
#define PIIX4_OCW2_SEOI (0x3 << 5)
#define PIIX4_OCW2_RNSEOI (0x5 << 5)
#define PIIX4_OCW2_RAEOIS (0x4 << 5)
#define PIIX4_OCW2_RAEOIC (0x0 << 5)
#define PIIX4_OCW2_RSEOI (0x7 << 5)
#define PIIX4_OCW2_SP (0x6 << 5)
#define PIIX4_OCW2_NOP (0x2 << 5)
#define PIIX4_OCW2_SEL (0x0 << 3)
#define PIIX4_OCW2_ILS_0 0
#define PIIX4_OCW2_ILS_1 1
#define PIIX4_OCW2_ILS_2 2
#define PIIX4_OCW2_ILS_3 3
#define PIIX4_OCW2_ILS_4 4
#define PIIX4_OCW2_ILS_5 5
#define PIIX4_OCW2_ILS_6 6
#define PIIX4_OCW2_ILS_7 7
#define PIIX4_OCW2_ILS_8 0
#define PIIX4_OCW2_ILS_9 1
#define PIIX4_OCW2_ILS_10 2
#define PIIX4_OCW2_ILS_11 3
#define PIIX4_OCW2_ILS_12 4
#define PIIX4_OCW2_ILS_13 5
#define PIIX4_OCW2_ILS_14 6
#define PIIX4_OCW2_ILS_15 7
#define PIIX4_OCW3_SEL (0x1 << 3)
#define PIIX4_OCW3_IRR 0x2
#define PIIX4_OCW3_ISR 0x3
#endif /* !(PIIX4_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* MIPS boards bootprom interface for the Linux kernel.
*
*/
#ifndef _MIPS_PROM_H
#define _MIPS_PROM_H
extern char *prom_getcmdline(void);
extern char *prom_getenv(char *name);
extern void setup_prom_printf(int tty_no);
extern void prom_printf(char *fmt, ...);
extern void prom_init_cmdline(void);
extern void prom_meminit(void);
extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
extern void prom_free_prom_memory (void);
extern void mips_display_message(const char *str);
extern void mips_display_word(unsigned int num);
extern int get_ethernet_addr(char *ethernet_addr);
/* Memory descriptor management. */
#define PROM_MAX_PMEMBLOCKS 32
struct prom_pmemblock {
unsigned long base; /* Within KSEG0. */
unsigned int size; /* In bytes. */
unsigned int type; /* free or prom memory */
};
#endif /* !(_MIPS_PROM_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Register definitions for the UART part of the Philips SAA9730 chip.
*
*/
#ifndef SAA9730_UART_H
#define SAA9730_UART_H
/* The SAA9730 UART register map, as seen via the PCI bus */
#define SAA9730_UART_REGS_ADDR 0x21800
struct uart_saa9730_regmap {
volatile unsigned char Thr_Rbr;
volatile unsigned char Ier;
volatile unsigned char Iir_Fcr;
volatile unsigned char Lcr;
volatile unsigned char Mcr;
volatile unsigned char Lsr;
volatile unsigned char Msr;
volatile unsigned char Scr;
volatile unsigned char BaudDivLsb;
volatile unsigned char BaudDivMsb;
volatile unsigned char Junk0;
volatile unsigned char Junk1;
volatile unsigned int Config; /* 0x2180c */
volatile unsigned int TxStart; /* 0x21810 */
volatile unsigned int TxLength; /* 0x21814 */
volatile unsigned int TxCounter; /* 0x21818 */
volatile unsigned int RxStart; /* 0x2181c */
volatile unsigned int RxLength; /* 0x21820 */
volatile unsigned int RxCounter; /* 0x21824 */
};
typedef volatile struct uart_saa9730_regmap t_uart_saa9730_regmap;
/*
* Only a subset of the UART control bits are defined here,
* enough to make the serial debug port work.
*/
#define SAA9730_LCR_DATA8 0x03
#define SAA9730_MCR_DTR 0x01
#define SAA9730_MCR_RTS 0x02
#define SAA9730_LSR_DR 0x01
#define SAA9730_LSR_THRE 0x20
#endif /* !(SAA9730_UART_H) */
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