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[LV-kern-commit] CVS: kernel-2.4/include/asm-mips/ddb5xxx ddb5477.h,NONE,1.1 ddb5xxx.h,NONE,1.1 debug.h,NONE,1.1 pci.h,NONE,1.1
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From: Andy P. <at...@us...> - 2002-04-09 12:33:26
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Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/ddb5xxx
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-mips/ddb5xxx
Added Files:
ddb5477.h ddb5xxx.h debug.h pci.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/***********************************************************************
*
* Copyright 2001 MontaVista Software Inc.
* Author: js...@mv... or js...@ju...
*
* include/asm-mips/ddb5xxx/ddb5477.h
* DDB 5477 specific definitions and macros.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
***********************************************************************
*/
#ifndef __ASM_DDB5XXX_DDB5477_H
#define __ASM_DDB5XXX_DDB5477_H
#include <linux/config.h>
#include <asm/ddb5xxx/ddb5xxx.h>
/*
* This contains macros that are specific to DDB5477 or renamed from
* DDB5476.
*/
/*
* renamed PADRs
*/
#define DDB_LCS0 DDB_LDCS0
#define DDB_LCS1 DDB_LDCS1
#define DDB_LCS2 DDB_LDCS2
#define DDB_VRC5477 DDB_INTCS
/*
* New CPU interface registers
*/
#define DDB_INTCTRL0 0x0400 /* Interrupt Control 0 */
#define DDB_INTCTRL1 0x0404 /* Interrupt Control 1 */
#define DDB_INTCTRL2 0x0408 /* Interrupt Control 2 */
#define DDB_INTCTRL3 0x040c /* Interrupt Control 3 */
#define DDB_INT0STAT 0x0420 /* INT0 Status [R] */
#define DDB_INT1STAT 0x0428 /* INT1 Status [R] */
#define DDB_INT2STAT 0x0430 /* INT2 Status [R] */
#define DDB_INT3STAT 0x0438 /* INT3 Status [R] */
#define DDB_INT4STAT 0x0440 /* INT4 Status [R] */
#define DDB_NMISTAT 0x0450 /* NMI Status [R] */
#define DDB_INTCLR32 0x0468 /* Interrupt Clear */
#define DDB_INTPPES0 0x0470 /* PCI0 Interrupt Control */
#define DDB_INTPPES1 0x0478 /* PCI1 Interrupt Control */
#undef DDB_CPUSTAT /* duplicate in Vrc-5477 */
#define DDB_CPUSTAT 0x0480 /* CPU Status [R] */
#define DDB_BUSCTRL 0x0488 /* Internal Bus Control */
/*
* Timer registers
*/
#define DDB_REFCTRL_L DDB_T0CTRL
#define DDB_REFCTRL_H (DDB_T0CTRL+4)
#define DDB_REFCNTR DDB_T0CNTR
#define DDB_SPT0CTRL_L DDB_T1CTRL
#define DDB_SPT0CTRL_H (DDB_T1CTRL+4)
#define DDB_SPT1CTRL_L DDB_T2CTRL
#define DDB_SPT1CTRL_H (DDB_T2CTRL+4)
#define DDB_SPT1CNTR DDB_T1CTRL
#define DDB_WDTCTRL_L DDB_T3CTRL
#define DDB_WDTCTRL_H (DDB_T3CTRL+4)
#define DDB_WDTCNTR DDB_T3CNTR
/*
* DMA registers are moved. We don't care about it for now. TODO.
*/
/*
* BARs for ext PCI (PCI0)
*/
#undef DDB_BARC
#undef DDB_BARB
#define DDB_BARC0 0x0210 /* PCI0 Control */
#define DDB_BARM010 0x0218 /* PCI0 SDRAM bank01 */
#define DDB_BARM230 0x0220 /* PCI0 SDRAM bank23 */
#define DDB_BAR00 0x0240 /* PCI0 LDCS0 */
#define DDB_BAR10 0x0248 /* PCI0 LDCS1 */
#define DDB_BAR20 0x0250 /* PCI0 LDCS2 */
#define DDB_BAR30 0x0258 /* PCI0 LDCS3 */
#define DDB_BAR40 0x0260 /* PCI0 LDCS4 */
#define DDB_BAR50 0x0268 /* PCI0 LDCS5 */
#define DDB_BARB0 0x0280 /* PCI0 BOOT */
#define DDB_BARP00 0x0290 /* PCI0 for IOPCI Window0 */
#define DDB_BARP10 0x0298 /* PCI0 for IOPCI Window1 */
/*
* BARs for IOPIC (PCI1)
*/
#define DDB_BARC1 0x0610 /* PCI1 Control */
#define DDB_BARM011 0x0618 /* PCI1 SDRAM bank01 */
#define DDB_BARM231 0x0620 /* PCI1 SDRAM bank23 */
#define DDB_BAR01 0x0640 /* PCI1 LDCS0 */
#define DDB_BAR11 0x0648 /* PCI1 LDCS1 */
#define DDB_BAR21 0x0650 /* PCI1 LDCS2 */
#define DDB_BAR31 0x0658 /* PCI1 LDCS3 */
#define DDB_BAR41 0x0660 /* PCI1 LDCS4 */
#define DDB_BAR51 0x0668 /* PCI1 LDCS5 */
#define DDB_BARB1 0x0680 /* PCI1 BOOT */
#define DDB_BARP01 0x0690 /* PCI1 for ext PCI Window0 */
#define DDB_BARP11 0x0698 /* PCI1 for ext PCI Window1 */
/*
* Other registers for ext PCI (PCI0)
*/
#define DDB_PCIINIT00 0x02f0 /* PCI0 Initiator 0 */
#define DDB_PCIINIT10 0x02f8 /* PCI0 Initiator 1 */
#define DDB_PCISWP0 0x02b0 /* PCI0 Swap */
#define DDB_PCIERR0 0x02b8 /* PCI0 Error */
#define DDB_PCICTL0_L 0x02e0 /* PCI0 Control-L */
#define DDB_PCICTL0_H 0x02e4 /* PCI0 Control-H */
#define DDB_PCIARB0_L 0x02e8 /* PCI0 Arbitration-L */
#define DDB_PCIARB0_H 0x02ec /* PCI0 Arbitration-H */
/*
* Other registers for IOPCI (PCI1)
*/
#define DDB_IOPCIW0 0x00d0 /* PCI Address Window 0 [R/W] */
#define DDB_IOPCIW1 0x00d8 /* PCI Address Window 1 [R/W] */
#define DDB_PCIINIT01 0x06f0 /* PCI1 Initiator 0 */
#define DDB_PCIINIT11 0x06f8 /* PCI1 Initiator 1 */
#define DDB_PCISWP1 0x06b0 /* PCI1 Swap */
#define DDB_PCIERR1 0x06b8 /* PCI1 Error */
#define DDB_PCICTL1_L 0x06e0 /* PCI1 Control-L */
#define DDB_PCICTL1_H 0x06e4 /* PCI1 Control-H */
#define DDB_PCIARB1_L 0x06e8 /* PCI1 Arbitration-L */
#define DDB_PCIARB1_H 0x06ec /* PCI1 Arbitration-H */
/*
* Local Bus
*/
#define DDB_LCST0 0x0110 /* LB Chip Select Timing 0 */
#define DDB_LCST1 0x0118 /* LB Chip Select Timing 1 */
#undef DDB_LCST2
#define DDB_LCST2 0x0120 /* LB Chip Select Timing 2 */
#undef DDB_LCST3
#undef DDB_LCST4
#undef DDB_LCST5
#undef DDB_LCST6
#undef DDB_LCST7
#undef DDB_LCST8
#define DDB_ERRADR 0x0150 /* Error Address Register */
#define DDB_ERRCS 0x0160
#define DDB_BTM 0x0170 /* Boot Time Mode value */
/*
* MISC registers
*/
#define DDB_GIUFUNSEL 0x4040 /* select dual-func pins */
#define DDB_PIBMISC 0x0750 /* USB buffer enable / power saving */
/*
* Memory map (physical address)
*
* Note most of the following address must be properly aligned by the
* corresponding size. For example, if PCI_IO_SIZE is 16MB, then
* PCI_IO_BASE must be aligned along 16MB boundary.
*/
#define DDB_SDRAM_BASE 0x00000000
#define DDB_SDRAM_SIZE 0x08000000 /* 128MB, for sure? */
#define DDB_PCI0_MEM_BASE 0x08000000
#define DDB_PCI0_MEM_SIZE 0x08000000 /* 128 MB */
#define DDB_PCI1_MEM_BASE 0x10000000
#define DDB_PCI1_MEM_SIZE 0x08000000 /* 128 MB */
#define DDB_PCI0_CONFIG_BASE 0x18000000
#define DDB_PCI0_CONFIG_SIZE 0x01000000 /* 16 MB */
#define DDB_PCI1_CONFIG_BASE 0x19000000
#define DDB_PCI1_CONFIG_SIZE 0x01000000 /* 16 MB */
#define DDB_PCI_IO_BASE 0x1a000000 /* we concatenate two IOs */
#define DDB_PCI0_IO_BASE 0x1a000000
#define DDB_PCI0_IO_SIZE 0x01000000 /* 16 MB */
#define DDB_PCI1_IO_BASE 0x1b000000
#define DDB_PCI1_IO_SIZE 0x01000000 /* 16 MB */
#define DDB_LCS0_BASE 0x1c000000 /* flash memory */
#define DDB_LCS0_SIZE 0x01000000 /* 16 MB */
#define DDB_LCS1_BASE 0x1d000000 /* misc */
#define DDB_LCS1_SIZE 0x01000000 /* 16 MB */
#define DDB_LCS2_BASE 0x1e000000 /* Mezzanine */
#define DDB_LCS2_SIZE 0x01000000 /* 16 MB */
#define DDB_VRC5477_BASE 0x1fa00000 /* VRC5477 control regs */
#define DDB_VRC5477_SIZE 0x00200000 /* 2MB */
#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
#define DDB_LED DDB_LCS1_BASE + 0x10000
/*
* DDB5477 specific functions
*/
extern void ddb5477_irq_setup(void);
/* route irq to cpu int pin */
extern void ll_vrc5477_irq_route(int vrc5477_irq, int ip);
/* low-level routine for enabling vrc5477 irq, bypassing high-level */
extern void ll_vrc5477_irq_enable(int vrc5477_irq);
extern void ll_vrc5477_irq_disable(int vrc5477_irq);
/*
* debug routines
*/
#if defined(CONFIG_LL_DEBUG)
extern void vrc5477_show_pdar_regs(void);
extern void vrc5477_show_pci_regs(void);
extern void vrc5477_show_bar_regs(void);
extern void vrc5477_show_int_regs(void);
extern void vrc5477_show_all_regs(void);
#endif
#endif /* __ASM_DDB5XXX_DDB5477_H */
--- NEW FILE ---
/***********************************************************************
*
* Copyright 2001 MontaVista Software Inc.
* Author: js...@mv... or js...@ju...
*
* Copyright (C) 2000 Geert Uytterhoeven <ge...@so...>
* Sony Software Development Center Europe (SDCE), Brussels
*
* include/asm-mips/ddb5xxx/ddb5xxx.h
* Common header for all NEC DDB 5xxx boards, including 5074, 5476, 5477.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
***********************************************************************
*/
#ifndef __ASM_DDB5XXX_DDB5XXX_H
#define __ASM_DDB5XXX_DDB5XXX_H
#include <linux/config.h>
#include <linux/types.h>
#include <asm/ddb5xxx/debug.h>
/*
* This file is based on the following documentation:
*
* NEC Vrc 5074 System Controller Data Sheet, June 1998
*
* [jsun] It is modified so that this file only contains the macros
* that are true for all DDB 5xxx boards. The modification is based on
*
* uPD31577(VRC5477) VR5432-SDRAM/PCI Bridge (Luke)
* Preliminary Specification Decoment, Rev 1.1, 27 Dec, 2000
*
*/
#define DDB_BASE 0xbfa00000
#define DDB_SIZE 0x00200000 /* 2 MB */
/*
* Physical Device Address Registers (PDARs)
*/
#define DDB_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */
#define DDB_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */
#define DDB_LDCS0 0x0010 /* Device Chip-Select 0 [R/W] */
#define DDB_LDCS1 0x0018 /* Device Chip-Select 1 [R/W] */
#define DDB_LDCS2 0x0020 /* Device Chip-Select 2 [R/W] */
#define DDB_LDCS3 0x0028 /* Device Chip-Select 3 [R/W] */
#define DDB_LDCS4 0x0030 /* Device Chip-Select 4 [R/W] */
#define DDB_LDCS5 0x0038 /* Device Chip-Select 5 [R/W] */
#define DDB_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */
#define DDB_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */
#define DDB_INTCS 0x0070 /* Controller Internal Registers and Devices */
/* [R/W] */
#define DDB_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */
/* Vrc5477 has two more, IOPCIW0, IOPCIW1 */
/*
* CPU Interface Registers
*/
#define DDB_CPUSTAT 0x0080 /* CPU Status [R/W] */
#define DDB_INTCTRL 0x0088 /* Interrupt Control [R/W] */
#define DDB_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */
#define DDB_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */
/* Enable [R/W] */
#define DDB_INTCLR 0x00A0 /* Interrupt Clear [R/W] */
#define DDB_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */
/*
* Memory-Interface Registers
*/
#define DDB_MEMCTRL 0x00C0 /* Memory Control */
#define DDB_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */
#define DDB_CHKERR 0x00D0 /* Memory Check Error Status [R] */
/*
* PCI-Bus Registers
*/
#define DDB_PCICTRL 0x00E0 /* PCI Control [R/W] */
#define DDB_PCIARB 0x00E8 /* PCI Arbiter [R/W] */
#define DDB_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */
#define DDB_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */
#define DDB_PCIERR 0x00B8 /* PCI Error [R/W] */
/*
* Local-Bus Registers
*/
#define DDB_LCNFG 0x0100 /* Local Bus Configuration [R/W] */
#define DDB_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */
#define DDB_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */
#define DDB_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */
#define DDB_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */
#define DDB_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */
#define DDB_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */
#define DDB_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */
#define DDB_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */
/* Enables [R/W] */
#define DDB_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */
#define DDB_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */
/*
* DMA Registers
*/
#define DDB_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */
#define DDB_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */
#define DDB_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */
#define DDB_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */
#define DDB_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */
#define DDB_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */
/*
* Timer Registers
*/
#define DDB_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */
#define DDB_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */
#define DDB_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */
#define DDB_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */
#define DDB_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */
#define DDB_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */
#define DDB_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */
#define DDB_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */
/*
* PCI Configuration Space Registers
*/
#define DDB_PCI_BASE 0x0200
#define DDB_VID 0x0200 /* PCI Vendor ID [R] */
#define DDB_DID 0x0202 /* PCI Device ID [R] */
#define DDB_PCICMD 0x0204 /* PCI Command [R/W] */
#define DDB_PCISTS 0x0206 /* PCI Status [R/W] */
#define DDB_REVID 0x0208 /* PCI Revision ID [R] */
#define DDB_CLASS 0x0209 /* PCI Class Code [R] */
#define DDB_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */
#define DDB_MLTIM 0x020D /* PCI Latency Timer [R/W] */
#define DDB_HTYPE 0x020E /* PCI Header Type [R] */
#define DDB_BIST 0x020F /* BIST [R] (unimplemented) */
#define DDB_BARC 0x0210 /* PCI Base Address Register Control [R/W] */
#define DDB_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */
#define DDB_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */
#define DDB_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */
/* (unimplemented) */
#define DDB_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */
#define DDB_SSID 0x022E /* PCI Sub-System ID [R/W] */
#define DDB_ROM 0x0230 /* Expansion ROM Base Address [R] */
/* (unimplemented) */
#define DDB_INTLIN 0x023C /* PCI Interrupt Line [R/W] */
#define DDB_INTPIN 0x023D /* PCI Interrupt Pin [R] */
#define DDB_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */
#define DDB_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */
#define DDB_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */
#define DDB_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */
#define DDB_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */
#define DDB_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */
#define DDB_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */
#define DDB_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */
#define DDB_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */
#define DDB_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */
/*
* Nile 4 Register Access
*/
static inline void ddb_sync(void)
{
volatile u32 *p = (volatile u32 *)0xbfc00000;
(void)(*p);
}
static inline void ddb_out32(u32 offset, u32 val)
{
*(volatile u32 *)(DDB_BASE+offset) = val;
ddb_sync();
}
static inline u32 ddb_in32(u32 offset)
{
u32 val = *(volatile u32 *)(DDB_BASE+offset);
ddb_sync();
return val;
}
static inline void ddb_out16(u32 offset, u16 val)
{
*(volatile u16 *)(DDB_BASE+offset) = val;
ddb_sync();
}
static inline u16 ddb_in16(u32 offset)
{
u16 val = *(volatile u16 *)(DDB_BASE+offset);
ddb_sync();
return val;
}
static inline void ddb_out8(u32 offset, u8 val)
{
*(volatile u8 *)(DDB_BASE+offset) = val;
ddb_sync();
}
static inline u8 ddb_in8(u32 offset)
{
u8 val = *(volatile u8 *)(DDB_BASE+offset);
ddb_sync();
return val;
}
/*
* Physical Device Address Registers
*/
extern u32
ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible);
extern void
ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
int on_memory_bus, int pci_visible);
/*
* PCI Master Registers
*/
#define DDB_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */
#define DDB_PCICMD_IO 1 /* PCI I/O Space */
#define DDB_PCICMD_MEM 3 /* PCI Memory Space */
#define DDB_PCICMD_CFG 5 /* PCI Configuration Space */
/*
* additional options for pci init reg (no shifting needed)
*/
#define DDB_PCI_CFGTYPE1 0x200 /* for pci init0/1 regs */
#define DDB_PCI_ACCESS_32 0x10 /* for pci init0/1 regs */
extern void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options);
/*
* we need to reset pci bus when we start up and shutdown
*/
extern void ddb_pci_reset_bus(void);
/*
* include the board dependent part
*/
#if defined(CONFIG_DDB5074)
#include <asm/ddb5xxx/ddb5074.h>
#elif defined(CONFIG_DDB5476)
#include <asm/ddb5xxx/ddb5476.h>
#elif defined(CONFIG_DDB5477)
#include <asm/ddb5xxx/ddb5477.h>
#else
#error "Unknown DDB board!"
#endif
#endif /* __ASM_DDB5XXX_DDB5XXX_H */
--- NEW FILE ---
/***********************************************************************
*
* Copyright 2001 MontaVista Software Inc.
* Author: js...@mv... or js...@ju...
*
* include/asm-mips/ddb5xxx/debug.h
* Some debug macros used by ddb code.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
***********************************************************************
*/
#ifndef __ASM_DDB5XXX_DEBUG_H
#define __ASM_DDB5XXX_DEBUG_H
#include <linux/config.h>
/*
* macro for catching spurious errors. Eable to LL_DEBUG in kernel hacking
* config menu.
*/
#ifdef CONFIG_LL_DEBUG
#include <linux/kernel.h>
#define MIPS_ASSERT(x) if (!(x)) { panic("MIPS_ASSERT failed at %s:%d\n", __FILE__, __LINE__); }
#define MIPS_VERIFY(x, y) MIPS_ASSERT(x y)
#define MIPS_DEBUG(x) do { x; } while (0)
#else
#define MIPS_ASSERT(x)
#define MIPS_VERIFY(x, y) x
#define MIPS_DEBUG(x)
#endif
#endif /* __ASM_DDB5XXX_DEBUG_H */
--- NEW FILE ---
#ifndef __ASM_DDB5XXXX_PCI_H
#define __ASM_DDB5XXXX_PCI_H
/*
* This file essentially defines the interface between board
* specific PCI code and MIPS common PCI code. Should potentially put
* into include/asm/pci.h file.
*/
#include <linux/ioport.h>
#include <linux/pci.h>
/*
* Each pci channel is a top-level PCI bus seem by CPU. A machine with
* multiple PCI channels may have multiple PCI host controllers or a
* single controller supporting multiple channels.
*/
struct pci_channel {
struct pci_ops *pci_ops;
struct resource *io_resource;
struct resource *mem_resource;
};
/*
* each board defines an array of pci_channels, that ends with all NULL entry
*/
extern struct pci_channel mips_pci_channels[];
/*
* board supplied pci irq fixup routine
*/
extern void pcibios_fixup_irqs(void);
#endif /* __ASM_DDB5XXXX_PCI_H */
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