[LV-kern-commit] CVS: kernel-2.4/include/asm-mips/pmc ev64120.h,NONE,1.1 ev64120int.h,NONE,1.1

[Andy P. <at...@us...>]

Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/pmc
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-mips/pmc

Added Files:
	ev64120.h ev64120int.h 
Log Message:
Synch to 2.4.15 commit 1


--- NEW FILE ---
/*
 * This is a direct copy of the ev96100.h file, with a global search and
 * replace.  The numbers are the same.
 *
 * The reason I'm duplicating this is so that the 64120/96100
 * defines won't be confusing in the source code.
 */
#ifndef _ASM_PMC_CP7000_H
#define _ASM_PMC_CP7000_H

#include <asm/addrspace.h>

/*
 *   GT64120 config space base address
 */
#define GT64120_BASE    (KSEG1ADDR(0x14000000))
#define MIPS_GT_BASE    GT64120_BASE
 
/*
 *   PCI Bus allocation
 */
#define GT_PCI_MEM_BASE    0x12000000
#define GT_PCI_MEM_SIZE    0x02000000
#define GT_PCI_IO_BASE     0x10000000
#define GT_PCI_IO_SIZE     0x02000000
#define GT_ISA_IO_BASE     PCI_IO_BASE          

/*
 *   Duart I/O ports.
 */
#define EV64120_COM1_BASE_ADDR  (0x1d000000 + 0x20) 
#define EV64120_COM2_BASE_ADDR  (0x1d000000 + 0x00)


/*
 *   EV64120 interrupt controller register base.
 */
#define EV64120_ICTRL_REGS_BASE   (KSEG1ADDR(0x1f000000))

/*
 *   EV64120 UART register base.
 */
#define EV64120_UART0_REGS_BASE    (KSEG1ADDR(EV64120_COM1_BASE_ADDR))
#define EV64120_UART1_REGS_BASE    (KSEG1ADDR(EV64120_COM2_BASE_ADDR))
#define EV64120_BASE_BAUD ( 3686400 / 16 )


/*
 * Because of an error/peculiarity in the Galileo chip, we need to swap the 
 * bytes when running bigendian.
 */

#define GT_WRITE(ofs, data)  \
	*(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data)
#define GT_READ(ofs, data)   \
	*data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs))
    

#endif /* _ASM_PMC_CP7000_H */

--- NEW FILE ---
#ifndef _ASM_PMC_CP7000INT_H
#define _ASM_PMC_CP7000INT_H

#define INT_CAUSE_MAIN 0
#define INT_CAUSE_HIGH 1

#define MAX_CAUSE_REGS 4
#define MAX_CAUSE_REG_WIDTH 32

void hook_irq_handler (int int_cause , int bit_num , void *isr_ptr);
int disable_galileo_irq (int int_cause , int bit_num);
int enable_galileo_irq (int int_cause , int bit_num);

extern struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];

/*
 * PCI interrupts will come in on either the INTA or INTD interrups lines,
 * which are mapped to the #2 and #5 interrupt pins of the MIPS.  On our
 * boards, they all either come in on IntD or they all come in on IntA, they
 * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
 * "requested" interrupt numbers and go through the list whenever we get an
 * IntA/D.
 *
 * All PCI interrupts have numbers >= 20 by arbitrary convention.  Any
 * interrupt < 8 is an interrupt that is maskable on MIPS.
 */

#define TIMER	4
#define INTA	2
#define INTD	5

#endif /* _ASM_PMC_CP7000INT_H */