From: Kenn H. <ke...@us...> - 2001-03-04 23:51:54
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Update of /cvsroot/linux-vax/kernel-2.4/include/asm-vax In directory usw-pr-cvs1:/tmp/cvs-serv16016 Modified Files: ka43.h Log Message: Pull in more definitions from NetBSD Index: ka43.h =================================================================== RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-vax/ka43.h,v retrieving revision 1.1 retrieving revision 1.2 diff -u -r1.1 -r1.2 --- ka43.h 2001/01/17 16:18:52 1.1 +++ ka43.h 2001/03/04 23:53:25 1.2 @@ -1,3 +1,72 @@ +/* + * $Id$ + * + * Definitions for KA43 CPU (VAXstation 3100m76). + * + * Taken from NetBSD + * + */ + +#ifndef __VAX_KA43_H +#define __VAX_KA43_H + +/* Fixed addresses in CPU's physical memory map */ + +#define KA43_CH2_BASE 0x10000000 /* 2nd level cache data area */ +#define KA43_CH2_END 0x1FFFFFFF +#define KA43_CH2_SIZE 0x10000000 + +#define KA43_CPU_BASE 0x20080000 /* so called "CPU registers" */ +#define KA43_CPU_END 0x200800FF +#define KA43_CPU_SIZE 0x100 + +#define KA43_NWA_BASE 0x20090000 /* Network Address ROM */ +#define KA43_NWA_END 0x2009007F +#define KA43_NWA_SIZE 0x80 + +#define KA43_SER_BASE 0x200A0000 /* Serial line controller */ +#define KA43_SER_END 0x200A000F +#define KA43_SER_SIZE 0x10 + +#define KA43_WAT_BASE 0x200B0000 /* TOY clock and NV-RAM */ +#define KA43_WAT_END 0x200B00FF +#define KA43_WAT_SIZE 0x100 + +#define KA43_SC1_BASE 0x200C0080 /* 1st SCSI Controller Chip */ +#define KA43_SC1_END 0x200C009F +#define KA43_SC1_SIZE 0x20 + +#define KA43_SC2_BASE 0x200C0180 /* 2nd SCSI Controller Chip */ +#define KA43_SC2_END 0x200C019F +#define KA43_SC2_SIZE 0x20 + +#define KA43_SCS_BASE 0x200C0000 /* area occupied by SCSI 1+2 */ +#define KA43_SCS_END 0x200C01FF +#define KA43_SCS_SIZE 0x200 + +#define KA43_LAN_BASE 0x200E0000 /* LANCE chip registers */ +#define KA43_LAN_END 0x200E0007 +#define KA43_LAN_SIZE 0x08 + +#define KA43_CUR_BASE 0x200F0000 /* Monochrome video cursor chip */ +#define KA43_CUR_END 0x200F003C +#define KA43_CUR_SIZE 0x40 + +#define KA43_DMA_BASE 0x202D0000 /* 128KB Data Buffer */ +#define KA43_DMA_END 0x202EFFFF +#define KA43_DMA_SIZE 0x20000 + +#define KA43_CT2_BASE 0x21000000 /* 2nd level cache tag area */ +#define KA43_CT2_END 0x2101FFFF +#define KA43_CT2_SIZE 0x20000 +#define KA43_CH2_CREG 0x21100000 /* 2nd level cache control register */ + +#define KA43_VME_BASE 0x30000000 +#define KA43_VME_END 0x3003FFFF +#define KA43_VME_SIZE 0x40000 + +#define KA43_DIAGMEM 0x28000000 + /* Cache defines Primary Cachce */ #define KA43_PCS_ENABLE 0x00000002 /* Enable primary cache */ #define KA43_PCS_FLUSH 0x00000004 /* Flush cache */ @@ -19,16 +88,34 @@ #define KA43_SESR_WSB 0x00010000 #define KA43_SESR_CIEA 0x7FFC0000 -#define KA43_CH2_BASE 0x10000000 /* 2nd level cache data area */ -#define KA43_CH2_END 0x1FFFFFFF -#define KA43_CH2_SIZE 0x10000000 -#define KA43_CT2_BASE 0x21000000 /* 2nd level cache tag area */ -#define KA43_CT2_END 0x2101FFFF -#define KA43_CT2_SIZE 0x20000 -#define KA43_CH2_CREG 0x21100000 /* 2nd level cache control register */ - #define PR_PCTAG 124 #define PR_PCIDX 125 #define PC_PCERR 126 #define PR_PCSTS 127 + +/* Bits in ka43_cpu_regs.parctl */ +#define KA43_PCTL_DPEN 0x00000001 /* DMA parity enable (bit 0) */ +#define KA43_PCTL_CPEN 0x00000002 /* CPU Parity enable (bit 1) */ +#define KA43_PCTL_DMA 0x01000000 /* LANCE DMA control (bit 24) */ + +#ifndef __ASSEMBLY__ + +struct ka43_cpu_regs { + unsigned long hltcod; /* Halt Code Register */ + unsigned long pad2; + unsigned long pad3; + unsigned char intreg[4]; /* Four 1-byte registers */ + unsigned short diagdsp; /* Diagnostic display register */ + unsigned short pad4; + unsigned long parctl; /* Parity Control Register */ + unsigned short pad5; + unsigned short pad6; + unsigned short pad7; + unsigned short diagtme; /* Diagnostic time register */ +}; + +#endif /* __ASSEMBLY */ + +#endif /* __VAX_KA43_H */ + |