[LV-kern-commit] CVS: kernel-2.4/arch/vax/kernel cpu_ka43.c,1.4,1.5

[Kenn H. <ke...@us...>]

Update of /cvsroot/linux-vax/kernel-2.4/arch/vax/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv15326

Modified Files:
	cpu_ka43.c 
Log Message:
Unmap cache-relation I/O mappings after cache has been initialized.  We
don't need them any more...

Clear CPEN (CPU parity enable).  Not sure about this, but VMS seems to
do it, and NetBSD does it when netbooting.


Index: cpu_ka43.c
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/arch/vax/kernel/cpu_ka43.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -r1.4 -r1.5
--- cpu_ka43.c	2001/02/22 22:36:42	1.4
+++ cpu_ka43.c	2001/03/04 23:50:30	1.5
@@ -25,19 +25,16 @@
 
 void ka43_pre_vm_init(void);
 void ka43_post_vm_init(void);
-void ka43_cache_disable(void);
-void ka43_cache_clear(void);
-void ka43_cache_enable(void);
+void ka43_cache_disable(volatile unsigned int *creg_addr);
+void ka43_cache_clear(volatile unsigned int *ctag_addr);
+void ka43_cache_enable(volatile unsigned int *creg_addr);
 
 void ka43_init_devices(void);
 
 const char *ka43_cpu_type_str(void);
 
-/* These are initialized at compile time with the physical addresses
-   of the KA43's CPU-specific data structures.  Once VM is turned on,
-   we'll map in these physical ranges, and update these pointers. */
-static volatile unsigned int *ka43_creg = (void*)KA43_CH2_CREG;
-static volatile unsigned int *ka43_ctag = (void*)KA43_CT2_BASE;
+/* Internal CPU register space */
+static volatile struct ka43_cpu_regs *cpu_regs;
 
 struct ka43_machine_vector {
 	struct vax_mv mv;
@@ -78,34 +75,46 @@
 
 void ka43_post_vm_init(void)
 {
+   volatile unsigned int *ctag_addr;
+   volatile unsigned int *creg_addr;
+
    init_dz11_console(0x200A0000, 3);
 
    dz_serial_console_init(0, 0);
 
-   ka43_creg = ioremap(KA43_CH2_CREG, 1);
-   ka43_ctag = ioremap(KA43_CT2_BASE, KA43_CT2_SIZE);
+   cpu_regs = ioremap(KA43_CPU_BASE, KA43_CPU_SIZE);
+   creg_addr = ioremap(KA43_CH2_CREG, 1);
+   ctag_addr = ioremap(KA43_CT2_BASE, KA43_CT2_SIZE);
+
+   /* Disable parity on DMA and CPU memory accesses.  Don't know what the
+      story is with this, but VMS seems do this too...  */
+   cpu_regs->parctl = 0;
 
   /*
    * Resetting the cache involves disabling it, then clear it and enable again.
    */
-   ka43_cache_disable();
-   ka43_cache_clear();
-   ka43_cache_enable();
-
+   ka43_cache_disable(creg_addr);
+   ka43_cache_clear(ctag_addr);
+   ka43_cache_enable(creg_addr);
+
+   /* Don't need these mappings any more */
+   iounmap((void *)ctag_addr);
+   iounmap((void *)creg_addr);
 }
 
-void ka43_cache_disable(void)
+void ka43_cache_disable(volatile unsigned int *creg_addr)
 {
    __mtpr(KA43_PCS_REFRESH, PR_PCSTS);       /* disable primary cache */
    __mtpr(__mfpr(PR_PCSTS), PR_PCSTS);       /* clear error flags */
 
    /* disable secondary cache */
-   *ka43_creg = *ka43_creg & ~KA43_SESR_CENB;
+   *creg_addr = *creg_addr & ~KA43_SESR_CENB;
+
    /* clear error flags */
-   *ka43_creg = KA43_SESR_SERR | KA43_SESR_LERR | KA43_SESR_CERR;
+   *creg_addr = KA43_SESR_SERR | KA43_SESR_LERR | KA43_SESR_CERR;
 }
 
-void ka43_cache_clear(void)
+void ka43_cache_clear(volatile unsigned int *ctag_addr)
 {
    int i;
   
@@ -117,13 +126,13 @@
 
    __mtpr(KA43_PCS_FLUSH | KA43_PCS_REFRESH, PR_PCSTS);
    
-   for (i = 0; i < KA43_CT2_SIZE; i+= 4)
+   for (i = 0; i < KA43_CT2_SIZE / sizeof(*ctag_addr); i++)
    {
-      ka43_ctag[i/4] = 0xff;
+      ctag_addr[i] = 0xff;
    }
 }
 
-void ka43_cache_enable(void)
+void ka43_cache_enable(volatile unsigned int *creg_addr)
 {
    volatile char *membase = (void*)0x80000000;     /* physical 0x00 */
    int i,val;
@@ -133,7 +142,7 @@
    __mtpr(KA43_PCS_ENABLE | KA43_PCS_REFRESH, PR_PCSTS); /* enable */
 
    /* enable secondary cache */
-   *ka43_creg = KA43_SESR_CENB;
+   *creg_addr = KA43_SESR_CENB;
    for (i=0; i<128*1024; i++) {
       val += membase[i]; 
    }