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From: James S. <jsi...@us...> - 2002-05-30 20:42:44
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Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv29100/arch/mips64/kernel
Modified Files:
entry.S irq.c linux32.c pci-dma.c proc.c r4k_switch.S setup.c
signal.c signal32.c smp.c syscall.c unaligned.c
Log Message:
Updated Mips 64 to OSS tree.
Index: entry.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/entry.S,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- entry.S 18 Dec 2001 00:25:47 -0000 1.5
+++ entry.S 30 May 2002 20:42:10 -0000 1.6
@@ -9,8 +9,6 @@
* Copyright (C) 1999, 2000 Silicon Graphics
* Copyright (C) 2001 MIPS Technologies, Inc.
*/
-#include <linux/config.h>
-
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
@@ -37,7 +35,7 @@
EXPORT(ret_from_irq)
EXPORT(ret_from_exception)
- lw t0, PT_STATUS(sp) # returning to kernel mode?
+ ld t0, PT_STATUS(sp) # returning to kernel mode?
andi t0, t0, KU_USER
bnez t0, ret_from_sys_call
j restore_all
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/irq.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- irq.c 28 Jan 2002 20:31:57 -0000 1.4
+++ irq.c 30 May 2002 20:42:10 -0000 1.5
@@ -76,13 +76,13 @@
int get_irq_list(char *buf)
{
+ int i, j;
struct irqaction * action;
char *p = buf;
- int i;
p += sprintf(p, " ");
- for (i=0; i < 1 /*smp_num_cpus*/; i++)
- p += sprintf(p, "CPU%d ", i);
+ for (j=0; j<smp_num_cpus; j++)
+ p += sprintf(p, "CPU%d ",j);
*p++ = '\n';
for (i = 0 ; i < NR_IRQS ; i++) {
@@ -90,7 +90,13 @@
if (!action)
continue;
p += sprintf(p, "%3d: ",i);
+#ifndef CONFIG_SMP
p += sprintf(p, "%10u ", kstat_irqs(i));
+#else
+ for (j = 0; j < smp_num_cpus; j++)
+ p += sprintf(p, "%10u ",
+ kstat.irqs[cpu_logical_map(j)][i]);
+#endif
p += sprintf(p, " %14s", irq_desc[i].handler->typename);
p += sprintf(p, " %s", action->name);
@@ -98,7 +104,8 @@
p += sprintf(p, ", %s", action->name);
*p++ = '\n';
}
- p += sprintf(p, "ERR: %10lu\n", irq_err_count);
+ p += sprintf(p, "\n");
+ p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
return p - buf;
}
Index: linux32.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/linux32.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- linux32.c 28 May 2002 20:25:36 -0000 1.6
+++ linux32.c 30 May 2002 20:42:10 -0000 1.7
@@ -1607,7 +1607,9 @@
if (!p)
return -ENOMEM;
err = get_user (p->mtype, &up->mtype);
- err |= __copy_from_user (p->mtext, &up->mtext, second);
+ if (err)
+ goto out;
+ err = __copy_from_user (p->mtext, &up->mtext, second);
if (err)
goto out;
old_fs = get_fs ();
Index: pci-dma.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/pci-dma.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- pci-dma.c 28 Jan 2002 20:34:23 -0000 1.1
+++ pci-dma.c 30 May 2002 20:42:10 -0000 1.2
@@ -7,6 +7,7 @@
* Copyright (C) 2000 Ralf Baechle <ra...@gn...>
* swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
*/
+#include <linux/config.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/string.h>
Index: proc.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/proc.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- proc.c 21 Apr 2002 20:01:14 -0000 1.11
+++ proc.c 30 May 2002 20:42:10 -0000 1.12
@@ -59,13 +59,15 @@
[CPU_TX3912] "TX3912",
[CPU_TX3922] "TX3922",
[CPU_TX3927] "TX3927",
- [CPU_AU1000] "Au1000",
+ [CPU_AU1000] "Au1000",
+ [CPU_AU1500] "Au1500",
[CPU_4KEC] "MIPS 4KEc",
[CPU_4KSC] "MIPS 4KSc",
[CPU_VR41XX] "NEC Vr41xx",
[CPU_R5500] "R5500",
[CPU_TX49XX] "TX49xx",
- [CPU_TX39XX] "TX39xx"
+ [CPU_TX39XX] "TX39xx",
+ [CPU_20KC] "MIPS 20Kc"
};
@@ -100,6 +102,7 @@
seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
seq_printf(m, "microsecond timers\t: %s\n",
(mips_cpu.options & MIPS_CPU_COUNTER) ? "yes" : "no");
+ seq_printf(m, "tlb_entries\t\t: %d\n", mips_cpu.tlbsize);
seq_printf(m, "extra interrupt vector\t: %s\n",
(mips_cpu.options & MIPS_CPU_DIVEC) ? "yes" : "no");
seq_printf(m, "hardware watchpoint\t: %s\n",
Index: r4k_switch.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/r4k_switch.S,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- r4k_switch.S 28 May 2002 20:25:36 -0000 1.3
+++ r4k_switch.S 30 May 2002 20:42:10 -0000 1.4
@@ -8,7 +8,6 @@
* Copyright (C) 1994, 1995, 1996, by Andreas Busse
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
-#include <linux/config.h>
#include <asm/asm.h>
#include <asm/cachectl.h>
#include <asm/current.h>
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/setup.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- setup.c 19 Feb 2002 17:50:59 -0000 1.11
+++ setup.c 30 May 2002 20:42:10 -0000 1.12
@@ -140,6 +140,11 @@
case CPU_NEVADA:
case CPU_RM7000:
case CPU_TX49XX:
+ case CPU_4KC:
+ case CPU_4KEC:
+ case CPU_4KSC:
+ case CPU_5KC:
+/* case CPU_20KC:*/
cpu_wait = r4k_wait;
printk(" available.\n");
break;
@@ -189,9 +194,26 @@
static inline void cpu_probe(void)
{
#ifdef CONFIG_CPU_MIPS32
+ unsigned long config0 = read_32bit_cp0_register(CP0_CONFIG);
unsigned long config1;
-#endif
+ if (config0 & (1 << 31)) {
+ /* MIPS32 compliant CPU. Read Config 1 register. */
+ mips_cpu.isa_level = MIPS_CPU_ISA_M32;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
+ MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC;
+ config1 = read_mips32_cp0_config1();
+ if (config1 & (1 << 3))
+ mips_cpu.options |= MIPS_CPU_WATCH;
+ if (config1 & (1 << 2))
+ mips_cpu.options |= MIPS_CPU_MIPS16;
+ if (config1 & (1 << 1))
+ mips_cpu.options |= MIPS_CPU_EJTAG;
+ if (config1 & 1)
+ mips_cpu.options |= MIPS_CPU_FPU;
+ mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
+ }
+#endif
mips_cpu.processor_id = read_32bit_cp0_register(CP0_PRID);
switch (mips_cpu.processor_id & 0xff0000) {
case PRID_COMP_LEGACY:
@@ -381,48 +403,20 @@
switch (mips_cpu.processor_id & 0xff00) {
case PRID_IMP_4KC:
mips_cpu.cputype = CPU_4KC;
- goto cpu_4kc;
+ break;
case PRID_IMP_4KEC:
mips_cpu.cputype = CPU_4KEC;
- goto cpu_4kc;
+ break;
case PRID_IMP_4KSC:
mips_cpu.cputype = CPU_4KSC;
-cpu_4kc:
- /*
- * Why do we set all these options by default, THEN
- * query them??
- */
- mips_cpu.isa_level = MIPS_CPU_ISA_M32;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_4KTLB | MIPS_CPU_COUNTER |
- MIPS_CPU_DIVEC | MIPS_CPU_WATCH |
- MIPS_CPU_MCHECK;
- config1 = read_mips32_cp0_config1();
- if (config1 & (1 << 3))
- mips_cpu.options |= MIPS_CPU_WATCH;
- if (config1 & (1 << 2))
- mips_cpu.options |= MIPS_CPU_MIPS16;
- if (config1 & 1)
- mips_cpu.options |= MIPS_CPU_FPU;
- mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
break;
case PRID_IMP_5KC:
mips_cpu.cputype = CPU_5KC;
mips_cpu.isa_level = MIPS_CPU_ISA_M64;
- /* See comment above about querying options */
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_4KTLB | MIPS_CPU_COUNTER |
- MIPS_CPU_DIVEC | MIPS_CPU_WATCH |
- MIPS_CPU_MCHECK;
- config1 = read_mips32_cp0_config1();
- if (config1 & (1 << 3))
- mips_cpu.options |= MIPS_CPU_WATCH;
- if (config1 & (1 << 2))
- mips_cpu.options |= MIPS_CPU_MIPS16;
- if (config1 & 1)
- mips_cpu.options |= MIPS_CPU_FPU;
- mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
break;
+ case PRID_IMP_20KC:
+ mips_cpu.cputype = CPU_20KC;
+ mips_cpu.isa_level = MIPS_CPU_ISA_M64;
default:
mips_cpu.cputype = CPU_UNKNOWN;
break;
@@ -432,19 +426,10 @@
switch (mips_cpu.processor_id & 0xff00) {
case PRID_IMP_AU1_REV1:
case PRID_IMP_AU1_REV2:
- mips_cpu.cputype = CPU_AU1000;
- mips_cpu.isa_level = MIPS_CPU_ISA_M32;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_4KTLB | MIPS_CPU_COUNTER |
- MIPS_CPU_DIVEC | MIPS_CPU_WATCH;
- config1 = read_mips32_cp0_config1();
- if (config1 & (1 << 3))
- mips_cpu.options |= MIPS_CPU_WATCH;
- if (config1 & (1 << 2))
- mips_cpu.options |= MIPS_CPU_MIPS16;
- if (config1 & 1)
- mips_cpu.options |= MIPS_CPU_FPU;
- mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
+ if (mips_cpu.processor_id & 0xff000000)
+ mips_cpu.cputype = CPU_AU1500;
+ else
+ mips_cpu.cputype = CPU_AU1000;
break;
default:
mips_cpu.cputype = CPU_UNKNOWN;
Index: signal.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/signal.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- signal.c 20 Nov 2001 17:34:02 -0000 1.3
+++ signal.c 30 May 2002 20:42:10 -0000 1.4
@@ -456,8 +456,9 @@
regs->cp0_epc = regs->regs[25] = (unsigned long) ka->sa.sa_handler;
#if DEBUG_SIG
- printk("SIG deliver (%s:%d): sp=0x%p pc=0x%p ra=0x%p\n", current->comm,
- current->pid, frame, regs->cp0_epc, frame->sf_code);
+ printk("SIG deliver (%s:%d): sp=0x%p pc=0x%lx ra=0x%p\n",
+ current->comm, current->pid,
+ frame, regs->cp0_epc, frame->sf_code);
#endif
return;
@@ -532,8 +533,9 @@
regs->cp0_epc = regs->regs[25] = (unsigned long) ka->sa.sa_handler;
#if DEBUG_SIG
- printk("SIG deliver (%s:%d): sp=0x%p pc=0x%p ra=0x%p\n", current->comm,
- current->pid, frame, regs->cp0_epc, frame->rs_code);
+ printk("SIG deliver (%s:%d): sp=0x%p pc=0x%lx ra=0x%p\n",
+ current->comm, current->pid,
+ frame, regs->cp0_epc, frame->rs_code);
#endif
return;
Index: signal32.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/signal32.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- signal32.c 20 Nov 2001 17:34:02 -0000 1.3
+++ signal32.c 30 May 2002 20:42:10 -0000 1.4
@@ -537,8 +537,9 @@
regs->cp0_epc = regs->regs[25] = (unsigned long) ka->sa.sa_handler;
#if DEBUG_SIG
- printk("SIG deliver (%s:%d): sp=0x%p pc=0x%p ra=0x%p\n", current->comm,
- current->pid, frame, regs->cp0_epc, frame->sf_code);
+ printk("SIG deliver (%s:%d): sp=0x%p pc=0x%lx ra=0x%p\n",
+ current->comm, current->pid,
+ frame, regs->cp0_epc, frame->sf_code);
#endif
return;
@@ -613,8 +614,9 @@
regs->cp0_epc = regs->regs[25] = (unsigned long) ka->sa.sa_handler;
#if DEBUG_SIG
- printk("SIG deliver (%s:%d): sp=0x%p pc=0x%p ra=0x%p\n", current->comm,
- current->pid, frame, regs->cp0_epc, frame->rs_code);
+ printk("SIG deliver (%s:%d): sp=0x%p pc=0x%lx ra=0x%p\n",
+ current->comm, current->pid,
+ frame, regs->cp0_epc, frame->rs_code);
#endif
return;
Index: smp.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/smp.c,v
retrieving revision 1.16
retrieving revision 1.17
diff -u -d -r1.16 -r1.17
--- smp.c 21 Apr 2002 20:01:14 -0000 1.16
+++ smp.c 30 May 2002 20:42:10 -0000 1.17
@@ -7,6 +7,7 @@
* Copyright (C) 2000, 2001 Ralf Baechle
* Copyright (C) 2000, 2001 Silicon Graphics, Inc.
*/
+#include <linux/config.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
@@ -78,6 +79,7 @@
printk("Slave cpu booted successfully\n");
CPUMASK_SETB(cpu_online_map, cpu);
atomic_inc(&cpus_booted);
+ while (!atomic_read(&smp_commenced));
cpu_idle();
}
#endif /* CONFIG_SGI_IP27 */
Index: syscall.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/syscall.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- syscall.c 26 Feb 2002 17:35:25 -0000 1.3
+++ syscall.c 30 May 2002 20:42:10 -0000 1.4
@@ -50,6 +50,59 @@
return res;
}
+#define COLOUR_ALIGN(addr,pgoff) \
+ ((((addr)+SHMLBA-1)&~(SHMLBA-1)) + \
+ (((pgoff)<<PAGE_SHIFT) & (SHMLBA-1)))
+
+unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
+ unsigned long len, unsigned long pgoff, unsigned long flags)
+{
+ struct vm_area_struct * vmm;
+ int do_color_align;
+
+ if (flags & MAP_FIXED) {
+ /*
+ * We do not accept a shared mapping if it would violate
+ * cache aliasing constraints.
+ */
+ if ((flags & MAP_SHARED) && (addr & (SHMLBA - 1)))
+ return -EINVAL;
+ return addr;
+ }
+
+ if (len > TASK_SIZE)
+ return -ENOMEM;
+ do_color_align = 0;
+ if (filp || (flags & MAP_SHARED))
+ do_color_align = 1;
+ if (addr) {
+ if (do_color_align)
+ addr = COLOUR_ALIGN(addr, pgoff);
+ else
+ addr = PAGE_ALIGN(addr);
+ vmm = find_vma(current->mm, addr);
+ if (TASK_SIZE - len >= addr &&
+ (!vmm || addr + len <= vmm->vm_start))
+ return addr;
+ }
+ addr = TASK_UNMAPPED_BASE;
+ if (do_color_align)
+ addr = COLOUR_ALIGN(addr, pgoff);
+ else
+ addr = PAGE_ALIGN(addr);
+
+ for (vmm = find_vma(current->mm, addr); ; vmm = vmm->vm_next) {
+ /* At this point: (!vmm || addr < vmm->vm_end). */
+ if (TASK_SIZE - len < addr)
+ return -ENOMEM;
+ if (!vmm || addr + len <= vmm->vm_start)
+ return addr;
+ addr = vmm->vm_end;
+ if (do_color_align)
+ addr = COLOUR_ALIGN(addr, pgoff);
+ }
+}
+
asmlinkage unsigned long
sys_mmap(unsigned long addr, size_t len, unsigned long prot,
unsigned long flags, unsigned long fd, off_t offset)
Index: unaligned.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/unaligned.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- unaligned.c 24 Apr 2002 17:34:12 -0000 1.6
+++ unaligned.c 30 May 2002 20:42:11 -0000 1.7
@@ -5,7 +5,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 1996, 1998, 1999 by Ralf Baechle
+ * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*
* This file contains exception handler for address error exception with the
@@ -351,7 +351,7 @@
fault:
/* Did we have an exception handler installed? */
- fixup = search_exception_table(regs->cp0_epc);
+ fixup = search_exception_table(exception_epc(regs));
if (fixup) {
long new_epc;
new_epc = fixup_exception(dpf_reg, fixup, regs->cp0_epc);
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