[Linux-mips-commits]CVS: linux/include/asm-mips mipsregs.h,1.20,1.21 cpu.h,1.26,1.27

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv29039/include/asm-mips

Modified Files:
	mipsregs.h cpu.h 
Log Message:
Build fixes.



Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/mipsregs.h,v
retrieving revision 1.20
retrieving revision 1.21
diff -u -d -r1.20 -r1.21
--- mipsregs.h	9 May 2002 17:22:36 -0000	1.20
+++ mipsregs.h	29 May 2002 18:19:58 -0000	1.21
@@ -52,12 +52,15 @@
 #define CP0_XCONTEXT $20
 #define CP0_FRAMEMASK $21
 #define CP0_DIAGNOSTIC $22
+#define CP0_DEBUG $23
+#define CP0_DEPC $24
 #define CP0_PERFORMANCE $25
 #define CP0_ECC $26
 #define CP0_CACHEERR $27
 #define CP0_TAGLO $28
 #define CP0_TAGHI $29
 #define CP0_ERROREPC $30
+#define CP0_DESAVE $31
 
 #ifdef CONFIG_CPU_LX45XXX
 #define CP0_CCTL $20		/* Lexra Cache Control Register */

Index: cpu.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/cpu.h,v
retrieving revision 1.26
retrieving revision 1.27
diff -u -d -r1.26 -r1.27
--- cpu.h	16 May 2002 18:40:07 -0000	1.26
+++ cpu.h	29 May 2002 18:19:58 -0000	1.27
@@ -56,13 +56,12 @@
 #define PRID_IMP_R4640		0x2200
 #define PRID_IMP_R4650		0x2200		/* Same as R4640 */
 #define PRID_IMP_R5000		0x2300
-#define PRID_IMP_TX49		0x2d00
-#define PRID_IMP_R5900		0x2e00
-#define PRID_IMP_TX49		0x2d00
 #define PRID_IMP_SONIC		0x2400
 #define PRID_IMP_MAGIC		0x2500
 #define PRID_IMP_RM7000		0x2700
 #define PRID_IMP_NEVADA		0x2800		/* RM5260 ??? */
+#define PRID_IMP_TX49		0x2d00
+#define PRID_IMP_R5900		0x2e00
 #define PRID_IMP_R5432		0x5400
 #define PRID_IMP_R5500		0x5500
 #define PRID_IMP_4KC		0x8000
@@ -106,6 +105,7 @@
 #define PRID_REV_TX3922 	0x0030
 #define PRID_REV_TX3927 	0x0040
 #define PRID_REV_TX3927B 	0x0041
+#define PRID_REV_TX4927		0x0022
 
 /*
  * FPU implementation/revision register (CP1 control register 0).
@@ -180,6 +180,6 @@
 #define MIPS_CPU_CACHE_CDEX	0x00000800 /* Create_Dirty_Exclusive CACHE op */
 #define MIPS_CPU_MCHECK		0x00001000 /* Machine check exception */
 #define MIPS_CPU_EJTAG		0x00002000 /* EJTAG exception */
-#define MIPS_CPU_FPUEX		0x00004000 /* FPU exception */
+#define MIPS_CPU_NOFPUEX	0x00004000 /* no FPU exception */
 
 #endif /* _ASM_CPU_H */