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[Linux-mips-commits]CVS: linux/arch/mips/kernel setup.c,1.62,1.63
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From: Paul M. <le...@us...> - 2002-05-28 20:57:31
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Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv3127/arch/mips/kernel
Modified Files:
setup.c
Log Message:
Further OSS syncing..
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.62
retrieving revision 1.63
diff -u -d -r1.62 -r1.63
--- setup.c 16 May 2002 18:40:06 -0000 1.62
+++ setup.c 28 May 2002 20:57:27 -0000 1.63
@@ -149,9 +149,12 @@
case CPU_NEVADA:
case CPU_RM7000:
case CPU_TX49XX:
-#ifdef CONFIG_MIPS_RC32355
case CPU_RC32300:
-#endif
+ case CPU_4KC:
+ case CPU_4KEC:
+ case CPU_4KSC:
+ case CPU_5KC:
+/* case CPU_20KC:*/
cpu_wait = r4k_wait;
printk(" available.\n");
break;
@@ -241,9 +244,26 @@
static inline void cpu_probe(void)
{
#ifdef CONFIG_CPU_MIPS32
+ unsigned long config0 = read_32bit_cp0_register(CP0_CONFIG);
unsigned long config1;
-#endif
+ if (config0 & (1 << 31)) {
+ /* MIPS32 compliant CPU. Read Config 1 register. */
+ mips_cpu.isa_level = MIPS_CPU_ISA_M32;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
+ MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC;
+ config1 = read_mips32_cp0_config1();
+ if (config1 & (1 << 3))
+ mips_cpu.options |= MIPS_CPU_WATCH;
+ if (config1 & (1 << 2))
+ mips_cpu.options |= MIPS_CPU_MIPS16;
+ if (config1 & (1 << 1))
+ mips_cpu.options |= MIPS_CPU_EJTAG;
+ if (config1 & 1)
+ mips_cpu.options |= MIPS_CPU_FPU;
+ mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
+ }
+#endif
mips_cpu.processor_id = read_32bit_cp0_register(CP0_PRID);
switch (mips_cpu.processor_id & 0xff0000) {
case PRID_COMP_LEGACY:
@@ -251,7 +271,7 @@
case PRID_IMP_R2000:
mips_cpu.cputype = CPU_R2000;
mips_cpu.isa_level = MIPS_CPU_ISA_I;
- mips_cpu.options = MIPS_CPU_TLB;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
if (cpu_has_fpu())
mips_cpu.options |= MIPS_CPU_FPU;
mips_cpu.tlbsize = 64;
@@ -265,7 +285,7 @@
else
mips_cpu.cputype = CPU_R3000;
mips_cpu.isa_level = MIPS_CPU_ISA_I;
- mips_cpu.options = MIPS_CPU_TLB;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
if (cpu_has_fpu())
mips_cpu.options |= MIPS_CPU_FPU;
mips_cpu.tlbsize = 64;
@@ -327,7 +347,7 @@
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
MIPS_CPU_32FPR | MIPS_CPU_WATCH |
- MIPS_CPU_VCE | MIPS_CPU_FPUEX;
+ MIPS_CPU_VCE;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_VR41XX:
@@ -344,14 +364,13 @@
mips_cpu.cputype = CPU_R4300;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR;
mips_cpu.tlbsize = 32;
break;
case PRID_IMP_R4600:
mips_cpu.cputype = CPU_R4600;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
mips_cpu.tlbsize = 48;
break;
#if 0
@@ -364,8 +383,7 @@
*/
mips_cpu.cputype = CPU_R4650;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
mips_cpu.tlbsize = 48;
break;
#endif
@@ -399,14 +417,14 @@
mips_cpu.cputype = CPU_R4700;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_TX49:
mips_cpu.cputype = CPU_TX49XX;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR;
mips_cpu.tlbsize = 48;
mips_cpu.icache.ways = 4;
mips_cpu.dcache.ways = 4;
@@ -415,31 +433,28 @@
mips_cpu.cputype = CPU_R5000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_R5432:
mips_cpu.cputype = CPU_R5432;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_WATCH |
- MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR | MIPS_CPU_WATCH;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_R5500:
mips_cpu.cputype = CPU_R5500;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_WATCH |
- MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR | MIPS_CPU_WATCH;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_NEVADA:
mips_cpu.cputype = CPU_NEVADA;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_DIVEC |
- MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR | MIPS_CPU_DIVEC;
mips_cpu.tlbsize = 48;
mips_cpu.icache.ways = 2;
mips_cpu.dcache.ways = 2;
@@ -448,33 +463,28 @@
mips_cpu.cputype = CPU_R5900;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU |
- MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
- MIPS_CPU_FPUEX;
+ MIPS_CPU_COUNTER | MIPS_CPU_DIVEC;
mips_cpu.tlbsize = 48;
mips_cpu.icache.ways = 2;
mips_cpu.dcache.ways = 2;
break;
-
-
case PRID_IMP_R6000:
mips_cpu.cputype = CPU_R6000;
mips_cpu.isa_level = MIPS_CPU_ISA_II;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU;
mips_cpu.tlbsize = 32;
break;
case PRID_IMP_R6000A:
mips_cpu.cputype = CPU_R6000A;
mips_cpu.isa_level = MIPS_CPU_ISA_II;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU;
mips_cpu.tlbsize = 32;
break;
case PRID_IMP_RM7000:
mips_cpu.cputype = CPU_RM7000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR;
/*
* Undocumented RM7000: Bit 29 in the info register of
* the RM7000 v2.0 indicates if the TLB has 48 or 64
@@ -489,8 +499,7 @@
mips_cpu.cputype = CPU_R8000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_FPU | MIPS_CPU_32FPR |
- MIPS_CPU_FPUEX;
+ MIPS_CPU_FPU | MIPS_CPU_32FPR;
mips_cpu.tlbsize = 384; /* has wierd TLB: 3-way x 128 */
break;
case PRID_IMP_R10000:
@@ -498,8 +507,7 @@
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
MIPS_CPU_FPU | MIPS_CPU_32FPR |
- MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
- MIPS_CPU_FPUEX;
+ MIPS_CPU_COUNTER | MIPS_CPU_WATCH;
mips_cpu.tlbsize = 64;
break;
case PRID_IMP_RC32334:
@@ -523,49 +531,20 @@
switch (mips_cpu.processor_id & 0xff00) {
case PRID_IMP_4KC:
mips_cpu.cputype = CPU_4KC;
- goto cpu_4kc;
+ break;
case PRID_IMP_4KEC:
mips_cpu.cputype = CPU_4KEC;
- goto cpu_4kc;
+ break;
case PRID_IMP_4KSC:
mips_cpu.cputype = CPU_4KSC;
-cpu_4kc:
- /*
- * Why do we set all these options by default, THEN
- * query them??
- */
- mips_cpu.isa_level = MIPS_CPU_ISA_M32;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_4KTLB | MIPS_CPU_COUNTER |
- MIPS_CPU_DIVEC | MIPS_CPU_WATCH |
- MIPS_CPU_MCHECK;
- config1 = read_mips32_cp0_config1();
- if (config1 & (1 << 3))
- mips_cpu.options |= MIPS_CPU_WATCH;
- if (config1 & (1 << 2))
- mips_cpu.options |= MIPS_CPU_MIPS16;
- if (config1 & 1)
- mips_cpu.options |= MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
- mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
break;
case PRID_IMP_5KC:
mips_cpu.cputype = CPU_5KC;
mips_cpu.isa_level = MIPS_CPU_ISA_M64;
- /* See comment above about querying options */
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_4KTLB | MIPS_CPU_COUNTER |
- MIPS_CPU_DIVEC | MIPS_CPU_WATCH |
- MIPS_CPU_MCHECK;
- config1 = read_mips32_cp0_config1();
- if (config1 & (1 << 3))
- mips_cpu.options |= MIPS_CPU_WATCH;
- if (config1 & (1 << 2))
- mips_cpu.options |= MIPS_CPU_MIPS16;
- if (config1 & 1)
- mips_cpu.options |= MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
- mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
+ break;
+ case PRID_IMP_20KC:
+ mips_cpu.cputype = CPU_20KC;
+ mips_cpu.isa_level = MIPS_CPU_ISA_M64;
break;
default:
mips_cpu.cputype = CPU_UNKNOWN;
@@ -591,18 +570,6 @@
break;
}
mips_cpu.isa_level = MIPS_CPU_ISA_M32;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_4KTLB | MIPS_CPU_COUNTER |
- MIPS_CPU_DIVEC | MIPS_CPU_WATCH;
- config1 = read_mips32_cp0_config1();
- if (config1 & (1 << 3))
- mips_cpu.options |= MIPS_CPU_WATCH;
- if (config1 & (1 << 2))
- mips_cpu.options |= MIPS_CPU_MIPS16;
- if (config1 & 1)
- mips_cpu.options |= MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
- mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
break;
default:
mips_cpu.cputype = CPU_UNKNOWN;
@@ -620,8 +587,7 @@
MIPS_CPU_MCHECK;
#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
/* FPU in pass1 is known to have issues. */
- mips_cpu.options |= MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
+ mips_cpu.options |= MIPS_CPU_FPU;
#endif
break;
default:
@@ -680,11 +646,9 @@
*/
loadmmu();
- /* Disable coprocessors and set FPU for 16 FPRs */
- s = read_32bit_cp0_register(CP0_STATUS);
- s &= ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_FR);
- s |= ST0_CU0;
- write_32bit_cp0_register(CP0_STATUS, s);
+ /* Disable coprocessors and set FPU for 16/32 FPR register model */
+ clear_cp0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_FR);
+ set_cp0_status(ST0_CU0);
start_kernel();
}
@@ -712,7 +676,8 @@
for (i = 0; i < boot_mem_map.nr_map; i++) {
printk(" memory: %08Lx @ %08Lx ",
(u64) boot_mem_map.map[i].size,
- (u64) boot_mem_map.map[i].addr);
+ (u64) boot_mem_map.map[i].addr);
+
switch (boot_mem_map.map[i].type) {
case BOOT_MEM_RAM:
printk("(usable)\n");
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