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[Linux-mips-commits]CVS: linux/arch/mips/au1000/pb1000 pci_fixup.c,1.4,1.5 pci_ops.c,1.2,1.3 setup.c,1.19,1.20
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From: Pete P. <pp...@us...> - 2002-05-01 18:08:21
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Update of /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000
In directory usw-pr-cvs1:/tmp/cvs-serv32242/arch/mips/au1000/pb1000
Modified Files:
pci_fixup.c pci_ops.c setup.c
Log Message:
Replaced readl/writel type of macros with au_readl/au_writel since
we need to enable software byte swapping in BE mode, but register
accesses should not be swapped. The Pb1x00 boards are now mostly BE
safe, but some external peripherals (external to the SOC) are not yet
usable in BE mode. USB has not been tested in BE mode either.
Index: pci_fixup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000/pci_fixup.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- pci_fixup.c 25 Sep 2001 03:36:35 -0000 1.4
+++ pci_fixup.c 1 May 2002 18:00:29 -0000 1.5
@@ -54,13 +54,13 @@
{
unsigned long pci_mem_start = (unsigned long) PCI_MEM_START;
- writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
- writel(0, SDRAM_MBAR); // set mbar to 0
- writel(0x2, SDRAM_CMD); // enable memory accesses
+ au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
+ au_writel(0, SDRAM_MBAR); // set mbar to 0
+ au_writel(0x2, SDRAM_CMD); // enable memory accesses
au_sync_delay(1);
// set extend byte to mbar of ext slot
- writel(((pci_mem_start >> 24) & 0xff) |
+ au_writel(((pci_mem_start >> 24) & 0xff) |
(1 << 8 | 1 << 9 | 1 << 10 | 1 << 27), PCI_BRIDGE_CONFIG);
DBG("Set bridge config to %x\n", readl(PCI_BRIDGE_CONFIG));
}
Index: pci_ops.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000/pci_ops.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- pci_ops.c 25 Sep 2001 03:36:35 -0000 1.2
+++ pci_ops.c 1 May 2002 18:00:29 -0000 1.3
@@ -92,9 +92,9 @@
config = PCI_CONFIG_BASE | (where & ~0x3);
if (access_type == PCI_ACCESS_WRITE) {
- outl(*data, config);
+ au_writel(*data, config);
} else {
- *data = inl(config);
+ *data = au_readl(config);
}
au_sync_udelay(1);
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000/setup.c,v
retrieving revision 1.19
retrieving revision 1.20
diff -u -d -r1.19 -r1.20
--- setup.c 17 Apr 2002 23:56:39 -0000 1.19
+++ setup.c 1 May 2002 18:00:29 -0000 1.20
@@ -121,8 +121,8 @@
#endif
// set AUX clock to 12MHz * 8 = 96 MHz
- writel(8, SYS_AUXPLL);
- writel(0, SYS_PINSTATERD);
+ au_writel(8, SYS_AUXPLL);
+ au_writel(0, SYS_PINSTATERD);
udelay(100);
#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
@@ -138,19 +138,19 @@
#endif
/* zero and disable FREQ2 */
- sys_freqctrl = readl(SYS_FREQCTRL0);
+ sys_freqctrl = au_readl(SYS_FREQCTRL0);
sys_freqctrl &= ~0xFFF00000;
- writel(sys_freqctrl, SYS_FREQCTRL0);
+ au_writel(sys_freqctrl, SYS_FREQCTRL0);
/* zero and disable USBH/USBD clocks */
- sys_clksrc = readl(SYS_CLKSRC);
+ sys_clksrc = au_readl(SYS_CLKSRC);
sys_clksrc &= ~0x00007FE0;
- writel(sys_clksrc, SYS_CLKSRC);
+ au_writel(sys_clksrc, SYS_CLKSRC);
- sys_freqctrl = readl(SYS_FREQCTRL0);
+ sys_freqctrl = au_readl(SYS_FREQCTRL0);
sys_freqctrl &= ~0xFFF00000;
- sys_clksrc = readl(SYS_CLKSRC);
+ sys_clksrc = au_readl(SYS_CLKSRC);
sys_clksrc &= ~0x00007FE0;
switch (prid & 0x000000FF)
@@ -159,17 +159,17 @@
case 0x01: /* HA */
case 0x02: /* HB */
/* CPU core freq to 48MHz to slow it way down... */
- writel(4, SYS_CPUPLL);
+ au_writel(4, SYS_CPUPLL);
/*
* Setup 48MHz FREQ2 from CPUPLL for USB Host
*/
/* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
- writel(sys_freqctrl, SYS_FREQCTRL0);
+ au_writel(sys_freqctrl, SYS_FREQCTRL0);
/* CPU core freq to 384MHz */
- writel(0x20, SYS_CPUPLL);
+ au_writel(0x20, SYS_CPUPLL);
printk("Au1000: 48MHz OHCI workaround enabled\n");
break;
@@ -177,7 +177,7 @@
default: /* HC and newer */
// FREQ2 = aux/2 = 48 MHz
sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
- writel(sys_freqctrl, SYS_FREQCTRL0);
+ au_writel(sys_freqctrl, SYS_FREQCTRL0);
break;
}
@@ -190,64 +190,64 @@
#ifdef CONFIG_AU1000_USB_DEVICE
sys_clksrc |= ((4<<7) | (0<<6) | (0<<5));
#endif
- writel(sys_clksrc, SYS_CLKSRC);
+ au_writel(sys_clksrc, SYS_CLKSRC);
#ifdef CONFIG_USB_OHCI
// enable host controller and wait for reset done
- writel(0x08, USB_HOST_CONFIG);
+ au_writel(0x08, USB_HOST_CONFIG);
udelay(1000);
- writel(0x0E, USB_HOST_CONFIG);
+ au_writel(0x0E, USB_HOST_CONFIG);
udelay(1000);
- readl(USB_HOST_CONFIG); // throw away first read
- while (!(readl(USB_HOST_CONFIG) & 0x10))
- readl(USB_HOST_CONFIG);
+ au_readl(USB_HOST_CONFIG); // throw away first read
+ while (!(au_readl(USB_HOST_CONFIG) & 0x10))
+ au_readl(USB_HOST_CONFIG);
#endif
// configure pins GPIO[14:9] as GPIO
- pin_func = readl(SYS_PINFUNC) & (u32)(~0x8080);
+ pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
#ifndef CONFIG_AU1000_USB_DEVICE
// 2nd USB port is USB host
pin_func |= 0x8000;
#endif
- writel(pin_func, SYS_PINFUNC);
- writel(0x2800, SYS_TRIOUTCLR);
- writel(0x0030, SYS_OUTPUTCLR);
+ au_writel(pin_func, SYS_PINFUNC);
+ au_writel(0x2800, SYS_TRIOUTCLR);
+ au_writel(0x0030, SYS_OUTPUTCLR);
#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
// make gpio 15 an input (for interrupt line)
- pin_func = readl(SYS_PINFUNC) & (u32)(~0x100);
+ pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x100);
// we don't need I2S, so make it available for GPIO[31:29]
pin_func |= (1<<5);
- writel(pin_func, SYS_PINFUNC);
+ au_writel(pin_func, SYS_PINFUNC);
- writel(0x8000, SYS_TRIOUTCLR);
+ au_writel(0x8000, SYS_TRIOUTCLR);
#ifdef CONFIG_FB
conswitchp = &dummy_con;
#endif
- static_cfg0 = readl(MEM_STCFG0) & (u32)(~0xc00);
- writel(static_cfg0, MEM_STCFG0);
+ static_cfg0 = au_readl(MEM_STCFG0) & (u32)(~0xc00);
+ au_writel(static_cfg0, MEM_STCFG0);
// configure RCE2* for LCD
- writel(0x00000004, MEM_STCFG2);
+ au_writel(0x00000004, MEM_STCFG2);
// MEM_STTIME2
- writel(0x09000000, MEM_STTIME2);
+ au_writel(0x09000000, MEM_STTIME2);
// Set 32-bit base address decoding for RCE2*
- writel(0x10003ff0, MEM_STADDR2);
+ au_writel(0x10003ff0, MEM_STADDR2);
// PCI CPLD setup
// expand CE0 to cover PCI
- writel(0x11803e40, MEM_STADDR1);
+ au_writel(0x11803e40, MEM_STADDR1);
// burst visibility on
- writel(readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
+ au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
- writel(0x83, MEM_STCFG1); // ewait enabled, flash timing
- writel(0x33030a10, MEM_STTIME1); // slower timing for FPGA
+ au_writel(0x83, MEM_STCFG1); // ewait enabled, flash timing
+ au_writel(0x33030a10, MEM_STTIME1); // slower timing for FPGA
#ifdef CONFIG_FB_E1356
if ((argptr = strstr(argptr, "video=")) == NULL) {
@@ -258,21 +258,22 @@
#ifdef CONFIG_PCI
- writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
- writel(0, SDRAM_MBAR); // set mbar to 0
- writel(0x2, SDRAM_CMD); // enable memory accesses
+ au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
+ au_writel(0, SDRAM_MBAR); // set mbar to 0
+ au_writel(0x2, SDRAM_CMD); // enable memory accesses
au_sync_delay(1);
#endif
#ifndef CONFIG_SERIAL_NONSTANDARD
/* don't touch the default serial console */
- writel(0, UART0_ADDR + UART_CLK);
+ au_writel(0, UART0_ADDR + UART_CLK);
#endif
- writel(0, UART1_ADDR + UART_CLK);
- writel(0, UART2_ADDR + UART_CLK);
- writel(0, UART3_ADDR + UART_CLK);
+ au_writel(0, UART1_ADDR + UART_CLK);
+ au_writel(0, UART2_ADDR + UART_CLK);
+ au_writel(0, UART3_ADDR + UART_CLK);
#ifdef CONFIG_BLK_DEV_IDE
+ if (0)
{
argptr = prom_getcmdline();
strcat(argptr, " ide0=noprobe");
@@ -282,15 +283,15 @@
// setup irda clocks
// aux clock, divide by 2, clock from 2/4 divider
- writel(readl(SYS_CLKSRC) | 0x7, SYS_CLKSRC);
- pin_func = readl(SYS_PINFUNC) & (u32)(~(1<<2)); // clear IRTXD
- writel(pin_func, SYS_PINFUNC);
+ au_writel(au_readl(SYS_CLKSRC) | 0x7, SYS_CLKSRC);
+ pin_func = au_readl(SYS_PINFUNC) & (u32)(~(1<<2)); // clear IRTXD
+ au_writel(pin_func, SYS_PINFUNC);
- while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
- writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
+ au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
au_sync();
- while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
- writel(0, SYS_TOYTRIM);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
+ au_writel(0, SYS_TOYTRIM);
/* Enable Au1000 BCLK switching - note: sed1356 must not use
* its BCLK (Au1000 LCLK) for any timings */
@@ -301,7 +302,7 @@
case 0x02: /* HB */
break;
default: /* HC and newer */
- writel(0x00000060, 0xb190003c);
+ au_writel(0x00000060, 0xb190003c);
break;
}
}
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