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[Linux-mips-commits]CVS: linux/arch/mips/au1000/common clocks.c,1.4,1.5 dbg_io.c,1.5,1.6 dma.c,1.8,1.9 irq.c,1.17,1.18 power.c,1.7,1.8 reset.c,1.5,1.6 rtc.c,1.2,1.3 serial.c,1.8,1.9 time.c,1.11,1.12 usbdev.c,1.9,1.10
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/common
In directory usw-pr-cvs1:/tmp/cvs-serv32242/arch/mips/au1000/common
Modified Files:
clocks.c dbg_io.c dma.c irq.c power.c reset.c rtc.c serial.c
time.c usbdev.c
Log Message:
Replaced readl/writel type of macros with au_readl/au_writel since
we need to enable software byte swapping in BE mode, but register
accesses should not be swapped. The Pb1x00 boards are now mostly BE
safe, but some external peripherals (external to the SOC) are not yet
usable in BE mode. USB has not been tested in BE mode either.
Index: clocks.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/clocks.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- clocks.c 23 Mar 2002 02:13:01 -0000 1.4
+++ clocks.c 1 May 2002 18:00:28 -0000 1.5
@@ -75,9 +75,9 @@
unsigned int static_cfg0;
unsigned int sys_busclk =
(get_au1000_speed()/1000) /
- ((int)(readl(SYS_POWERCTRL)&0x03) + 2);
+ ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2);
- static_cfg0 = readl(MEM_STCFG0);
+ static_cfg0 = au_readl(MEM_STCFG0);
if (static_cfg0 & (1<<11))
lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */
Index: dbg_io.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/dbg_io.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- dbg_io.c 15 Feb 2002 19:47:24 -0000 1.5
+++ dbg_io.c 1 May 2002 18:00:28 -0000 1.6
@@ -53,8 +53,8 @@
#define UART_MOD_CNTRL 0x100 /* Module Control */
/* memory-mapped read/write of the port */
-#define UART16550_READ(y) (readl(DEBUG_BASE + y) & 0xff)
-#define UART16550_WRITE(y,z) (writel(z&0xff, DEBUG_BASE + y))
+#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff)
+#define UART16550_WRITE(y,z) (au_writel(z&0xff, DEBUG_BASE + y))
extern unsigned long get_au1000_uart_baud_base(void);
extern unsigned long cal_r4koff(void);
Index: dma.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/dma.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- dma.c 25 Mar 2002 22:58:15 -0000 1.8
+++ dma.c 1 May 2002 18:00:29 -0000 1.9
@@ -133,17 +133,17 @@
printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);
printk(KERN_INFO " mode = 0x%08x\n",
- readl(chan->io + DMA_MODE_SET));
+ au_readl(chan->io + DMA_MODE_SET));
printk(KERN_INFO " addr = 0x%08x\n",
- readl(chan->io + DMA_PERIPHERAL_ADDR));
+ au_readl(chan->io + DMA_PERIPHERAL_ADDR));
printk(KERN_INFO " start0 = 0x%08x\n",
- readl(chan->io + DMA_BUFFER0_START));
+ au_readl(chan->io + DMA_BUFFER0_START));
printk(KERN_INFO " start1 = 0x%08x\n",
- readl(chan->io + DMA_BUFFER1_START));
+ au_readl(chan->io + DMA_BUFFER1_START));
printk(KERN_INFO " count0 = 0x%08x\n",
- readl(chan->io + DMA_BUFFER0_COUNT));
+ au_readl(chan->io + DMA_BUFFER0_COUNT));
printk(KERN_INFO " count1 = 0x%08x\n",
- readl(chan->io + DMA_BUFFER1_COUNT));
+ au_readl(chan->io + DMA_BUFFER1_COUNT));
}
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/irq.c,v
retrieving revision 1.17
retrieving revision 1.18
diff -u -d -r1.17 -r1.18
--- irq.c 2 Apr 2002 22:59:39 -0000 1.17
+++ irq.c 1 May 2002 18:00:29 -0000 1.18
@@ -105,86 +105,86 @@
if (irq_nr > AU1000_LAST_INTC0_INT) {
switch (type) {
case INTC_INT_RISE_EDGE: /* 0:0:1 */
- writel(1<<(irq_nr-32), IC1_CFG2CLR);
- writel(1<<(irq_nr-32), IC1_CFG1CLR);
- writel(1<<(irq_nr-32), IC1_CFG0SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG0SET);
break;
case INTC_INT_FALL_EDGE: /* 0:1:0 */
- writel(1<<(irq_nr-32), IC1_CFG2CLR);
- writel(1<<(irq_nr-32), IC1_CFG1SET);
- writel(1<<(irq_nr-32), IC1_CFG0CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG1SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
break;
case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
- writel(1<<(irq_nr-32), IC1_CFG2SET);
- writel(1<<(irq_nr-32), IC1_CFG1CLR);
- writel(1<<(irq_nr-32), IC1_CFG0SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG2SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG0SET);
break;
case INTC_INT_LOW_LEVEL: /* 1:1:0 */
- writel(1<<(irq_nr-32), IC1_CFG2SET);
- writel(1<<(irq_nr-32), IC1_CFG1SET);
- writel(1<<(irq_nr-32), IC1_CFG0CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG2SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG1SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
break;
case INTC_INT_DISABLED: /* 0:0:0 */
- writel(1<<(irq_nr-32), IC1_CFG0CLR);
- writel(1<<(irq_nr-32), IC1_CFG1CLR);
- writel(1<<(irq_nr-32), IC1_CFG2CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
break;
default: /* disable the interrupt */
printk("unexpected int type %d (irq %d)\n", type, irq_nr);
- writel(1<<(irq_nr-32), IC1_CFG0CLR);
- writel(1<<(irq_nr-32), IC1_CFG1CLR);
- writel(1<<(irq_nr-32), IC1_CFG2CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
return;
}
if (int_req) /* assign to interrupt request 1 */
- writel(1<<(irq_nr-32), IC1_ASSIGNCLR);
+ au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR);
else /* assign to interrupt request 0 */
- writel(1<<(irq_nr-32), IC1_ASSIGNSET);
- writel(1<<(irq_nr-32), IC1_SRCSET);
- writel(1<<(irq_nr-32), IC1_MASKCLR);
- writel(1<<(irq_nr-32), IC1_WAKECLR);
+ au_writel(1<<(irq_nr-32), IC1_ASSIGNSET);
+ au_writel(1<<(irq_nr-32), IC1_SRCSET);
+ au_writel(1<<(irq_nr-32), IC1_MASKCLR);
+ au_writel(1<<(irq_nr-32), IC1_WAKECLR);
}
else {
switch (type) {
case INTC_INT_RISE_EDGE: /* 0:0:1 */
- writel(1<<irq_nr, IC0_CFG2CLR);
- writel(1<<irq_nr, IC0_CFG1CLR);
- writel(1<<irq_nr, IC0_CFG0SET);
+ au_writel(1<<irq_nr, IC0_CFG2CLR);
+ au_writel(1<<irq_nr, IC0_CFG1CLR);
+ au_writel(1<<irq_nr, IC0_CFG0SET);
break;
case INTC_INT_FALL_EDGE: /* 0:1:0 */
- writel(1<<irq_nr, IC0_CFG2CLR);
- writel(1<<irq_nr, IC0_CFG1SET);
- writel(1<<irq_nr, IC0_CFG0CLR);
+ au_writel(1<<irq_nr, IC0_CFG2CLR);
+ au_writel(1<<irq_nr, IC0_CFG1SET);
+ au_writel(1<<irq_nr, IC0_CFG0CLR);
break;
case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
- writel(1<<irq_nr, IC0_CFG2SET);
- writel(1<<irq_nr, IC0_CFG1CLR);
- writel(1<<irq_nr, IC0_CFG0SET);
+ au_writel(1<<irq_nr, IC0_CFG2SET);
+ au_writel(1<<irq_nr, IC0_CFG1CLR);
+ au_writel(1<<irq_nr, IC0_CFG0SET);
break;
case INTC_INT_LOW_LEVEL: /* 1:1:0 */
- writel(1<<irq_nr, IC0_CFG2SET);
- writel(1<<irq_nr, IC0_CFG1SET);
- writel(1<<irq_nr, IC0_CFG0CLR);
+ au_writel(1<<irq_nr, IC0_CFG2SET);
+ au_writel(1<<irq_nr, IC0_CFG1SET);
+ au_writel(1<<irq_nr, IC0_CFG0CLR);
break;
case INTC_INT_DISABLED: /* 0:0:0 */
- writel(1<<irq_nr, IC0_CFG0CLR);
- writel(1<<irq_nr, IC0_CFG1CLR);
- writel(1<<irq_nr, IC0_CFG2CLR);
+ au_writel(1<<irq_nr, IC0_CFG0CLR);
+ au_writel(1<<irq_nr, IC0_CFG1CLR);
+ au_writel(1<<irq_nr, IC0_CFG2CLR);
break;
default: /* disable the interrupt */
printk("unexpected int type %d (irq %d)\n", type, irq_nr);
- writel(1<<irq_nr, IC0_CFG0CLR);
- writel(1<<irq_nr, IC0_CFG1CLR);
- writel(1<<irq_nr, IC0_CFG2CLR);
+ au_writel(1<<irq_nr, IC0_CFG0CLR);
+ au_writel(1<<irq_nr, IC0_CFG1CLR);
+ au_writel(1<<irq_nr, IC0_CFG2CLR);
return;
}
if (int_req) /* assign to interrupt request 1 */
- writel(1<<irq_nr, IC0_ASSIGNCLR);
+ au_writel(1<<irq_nr, IC0_ASSIGNCLR);
else /* assign to interrupt request 0 */
- writel(1<<irq_nr, IC0_ASSIGNSET);
- writel(1<<irq_nr, IC0_SRCSET);
- writel(1<<irq_nr, IC0_MASKCLR);
- writel(1<<irq_nr, IC0_WAKECLR);
+ au_writel(1<<irq_nr, IC0_ASSIGNSET);
+ au_writel(1<<irq_nr, IC0_SRCSET);
+ au_writel(1<<irq_nr, IC0_MASKCLR);
+ au_writel(1<<irq_nr, IC0_WAKECLR);
}
au_sync();
}
@@ -207,12 +207,12 @@
inline void local_enable_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- writel(1<<(irq_nr-32), IC1_MASKSET);
- writel(1<<(irq_nr-32), IC1_WAKESET);
+ au_writel(1<<(irq_nr-32), IC1_MASKSET);
+ au_writel(1<<(irq_nr-32), IC1_WAKESET);
}
else {
- writel(1<<irq_nr, IC0_MASKSET);
- writel(1<<irq_nr, IC0_WAKESET);
+ au_writel(1<<irq_nr, IC0_MASKSET);
+ au_writel(1<<irq_nr, IC0_WAKESET);
}
au_sync();
}
@@ -221,12 +221,12 @@
inline void local_disable_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- writel(1<<(irq_nr-32), IC1_MASKCLR);
- writel(1<<(irq_nr-32), IC1_WAKECLR);
+ au_writel(1<<(irq_nr-32), IC1_MASKCLR);
+ au_writel(1<<(irq_nr-32), IC1_WAKECLR);
}
else {
- writel(1<<irq_nr, IC0_MASKCLR);
- writel(1<<irq_nr, IC0_WAKECLR);
+ au_writel(1<<irq_nr, IC0_MASKCLR);
+ au_writel(1<<irq_nr, IC0_WAKECLR);
}
au_sync();
}
@@ -235,12 +235,12 @@
static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- writel(1<<(irq_nr-32), IC1_RISINGCLR);
- writel(1<<(irq_nr-32), IC1_MASKCLR);
+ au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
+ au_writel(1<<(irq_nr-32), IC1_MASKCLR);
}
else {
- writel(1<<irq_nr, IC0_RISINGCLR);
- writel(1<<irq_nr, IC0_MASKCLR);
+ au_writel(1<<irq_nr, IC0_RISINGCLR);
+ au_writel(1<<irq_nr, IC0_MASKCLR);
}
au_sync();
}
@@ -249,12 +249,12 @@
static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- writel(1<<(irq_nr-32), IC1_FALLINGCLR);
- writel(1<<(irq_nr-32), IC1_MASKCLR);
+ au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
+ au_writel(1<<(irq_nr-32), IC1_MASKCLR);
}
else {
- writel(1<<irq_nr, IC0_FALLINGCLR);
- writel(1<<irq_nr, IC0_MASKCLR);
+ au_writel(1<<irq_nr, IC0_FALLINGCLR);
+ au_writel(1<<irq_nr, IC0_MASKCLR);
}
au_sync();
}
@@ -267,7 +267,7 @@
au_sync();
#if defined(CONFIG_MIPS_PB1000)
if (irq_nr == AU1000_GPIO_15) {
- writew(0x8000, PB1000_MDR); /* ack int */
+ au_writel(0x8000, PB1000_MDR); /* ack int */
au_sync();
}
#endif
@@ -286,7 +286,7 @@
}
#if defined(CONFIG_MIPS_PB1000)
if (irq_nr == AU1000_GPIO_15) {
- writew(0x4000, PB1000_MDR); /* enable int */
+ au_writel(0x4000, PB1000_MDR); /* enable int */
au_sync();
}
#endif
@@ -299,13 +299,13 @@
save_and_cli(flags);
if (controller) {
- mask = readl(IC1_MASKSET);
+ mask = au_readl(IC1_MASKSET);
for (i=32; i<64; i++) {
local_disable_irq(i);
}
}
else {
- mask = readl(IC0_MASKSET);
+ mask = au_readl(IC0_MASKSET);
for (i=0; i<32; i++) {
local_disable_irq(i);
}
@@ -329,9 +329,9 @@
}
}
if (controller)
- new_mask = readl(IC1_MASKSET);
+ new_mask = au_readl(IC1_MASKSET);
else
- new_mask = readl(IC0_MASKSET);
+ new_mask = au_readl(IC0_MASKSET);
restore_flags(flags);
}
@@ -511,7 +511,7 @@
int irq = 0, i;
static unsigned long intc0_req0 = 0;
- intc0_req0 |= readl(IC0_REQ0INT);
+ intc0_req0 |= au_readl(IC0_REQ0INT);
if (!intc0_req0) return;
@@ -531,7 +531,7 @@
int irq = 0, i;
static unsigned long intc0_req1 = 0;
- intc0_req1 = readl(IC0_REQ1INT);
+ intc0_req1 = au_readl(IC0_REQ1INT);
if (!intc0_req1) return;
@@ -567,20 +567,20 @@
volatile unsigned short levels, mdr;
unsigned char ide_status;
- intc1_req0 |= readl(IC1_REQ0INT);
+ intc1_req0 |= au_readl(IC1_REQ0INT);
if (!intc1_req0) return;
-#ifdef CONFIG_MIPS_PB1000
- writew(1, CPLD_AUX0); /* debug led 0 */
+#if defined(CONFIG_MIPS_PB1000) && defined(DEBUG_IRQ)
+ au_writel(1, CPLD_AUX0); /* debug led 0 */
#endif
for (i=0; i<32; i++) {
if ((intc1_req0 & (1<<i))) {
intc1_req0 &= ~(1<<i);
-#ifdef CONFIG_MIPS_PB1000
- writew(2, CPLD_AUX0); /* turn on debug led 1 */
+#if defined(CONFIG_MIPS_PB1000) && defined(DEBUG_IRQ)
+ au_writel(2, CPLD_AUX0); /* turn on debug led 1 */
do_IRQ(irq+32, regs);
- writew(0, CPLD_AUX0); /* turn off debug led 1 */
+ au_writel(0, CPLD_AUX0); /* turn off debug led 1 */
#else
do_IRQ(irq+32, regs);
#endif
@@ -588,8 +588,8 @@
}
irq++;
}
-#ifdef CONFIG_MIPS_PB1000
- writew(0, CPLD_AUX0);
+#if defined(CONFIG_MIPS_PB1000) && defined(DEBUG_IRQ)
+ au_writel(0, CPLD_AUX0);
#endif
}
@@ -599,7 +599,7 @@
int irq = 0, i;
static unsigned long intc1_req1 = 0;
- intc1_req1 |= readl(IC1_REQ1INT);
+ intc1_req1 |= au_readl(IC1_REQ1INT);
if (!intc1_req1) return;
Index: power.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/power.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- power.c 23 Apr 2002 16:43:47 -0000 1.7
+++ power.c 1 May 2002 18:00:29 -0000 1.8
@@ -81,16 +81,16 @@
flush_cache_all();
/* pin 6 is gpio */
- writel(readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
+ au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
/* gpio 6 can cause a wake up event */
- wakeup = readl(SYS_WAKEMSK);
+ wakeup = au_readl(SYS_WAKEMSK);
wakeup &= ~(1 << 8); /* turn off match20 wakeup */
wakeup |= 1 << 6; /* turn on gpio 6 wakeup */
- writel(wakeup, SYS_WAKEMSK);
+ au_writel(wakeup, SYS_WAKEMSK);
- writel(1, SYS_WAKESRC); /* clear cause */
- writel(1, SYS_SLPPWR); /* prepare to sleep */
+ au_writel(1, SYS_WAKESRC); /* clear cause */
+ au_writel(1, SYS_SLPPWR); /* prepare to sleep */
__asm__("la $4, 1f\n\t"
"lui $5, 0xb190\n\t"
@@ -194,22 +194,22 @@
set_au1000_speed(new_cpu_freq);
set_au1000_uart_baud_base(new_baud_base);
- old_refresh = readl(MEM_SDREFCFG) & 0x1ffffff;
+ old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff;
new_refresh =
((old_refresh * new_cpu_freq) /
- old_cpu_freq) | (readl(MEM_SDREFCFG) & ~0x1ffffff);
+ old_cpu_freq) | (au_readl(MEM_SDREFCFG) & ~0x1ffffff);
- writel(pll, SYS_CPUPLL);
+ au_writel(pll, SYS_CPUPLL);
au_sync_delay(1);
- writel(new_refresh, MEM_SDREFCFG);
+ au_writel(new_refresh, MEM_SDREFCFG);
au_sync_delay(1);
for (i = 0; i < 4; i++) {
- if (readl
+ if (au_readl
(UART_BASE + UART_MOD_CNTRL +
i * 0x00100000) == 3) {
old_clk =
- readl(UART_BASE + UART_CLK +
+ au_readl(UART_BASE + UART_CLK +
i * 0x00100000);
// baud_rate = baud_base/clk
baud_rate = old_baud_base / old_clk;
@@ -231,7 +231,7 @@
(baud_rate = 9600);
// new_clk = new_baud_base/baud_rate
new_clk = new_baud_base / baud_rate;
- writel(new_clk,
+ au_writel(new_clk,
UART_BASE + UART_CLK +
i * 0x00100000);
au_sync_delay(10);
Index: reset.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/reset.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- reset.c 2 Apr 2002 22:59:39 -0000 1.5
+++ reset.c 1 May 2002 18:00:29 -0000 1.6
@@ -35,6 +35,7 @@
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/system.h>
+#include <asm/au1000.h>
extern int au_sleep(void);
@@ -47,59 +48,59 @@
switch (prid & 0xFF000000)
{
case 0x00000000: /* Au1000 */
- writel(0x02, 0xb0000010); /* ac97_enable */
- writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
+ au_writel(0x02, 0xb0000010); /* ac97_enable */
+ au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
asm("sync");
- writel(0x00, 0xb017fffc); /* usbh_enable */
- writel(0x00, 0xb0200058); /* usbd_enable */
- writel(0x00, 0xb0300040); /* ir_enable */
- writel(0x00, 0xb0520000); /* macen0 */
- writel(0x00, 0xb0520004); /* macen1 */
- writel(0x00, 0xb1000008); /* i2s_enable */
- writel(0x00, 0xb1100100); /* uart0_enable */
- writel(0x00, 0xb1200100); /* uart1_enable */
- writel(0x00, 0xb1300100); /* uart2_enable */
- writel(0x00, 0xb1400100); /* uart3_enable */
- writel(0x02, 0xb1600100); /* ssi0_enable */
- writel(0x02, 0xb1680100); /* ssi1_enable */
- writel(0x00, 0xb1900020); /* sys_freqctrl0 */
- writel(0x00, 0xb1900024); /* sys_freqctrl1 */
- writel(0x00, 0xb1900028); /* sys_clksrc */
- writel(0x00, 0xb1900100); /* sys_pininputen */
+ au_writel(0x00, 0xb017fffc); /* usbh_enable */
+ au_writel(0x00, 0xb0200058); /* usbd_enable */
+ au_writel(0x00, 0xb0300040); /* ir_enable */
+ au_writel(0x00, 0xb0520000); /* macen0 */
+ au_writel(0x00, 0xb0520004); /* macen1 */
+ au_writel(0x00, 0xb1000008); /* i2s_enable */
+ au_writel(0x00, 0xb1100100); /* uart0_enable */
+ au_writel(0x00, 0xb1200100); /* uart1_enable */
+ au_writel(0x00, 0xb1300100); /* uart2_enable */
+ au_writel(0x00, 0xb1400100); /* uart3_enable */
+ au_writel(0x02, 0xb1600100); /* ssi0_enable */
+ au_writel(0x02, 0xb1680100); /* ssi1_enable */
+ au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
+ au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
+ au_writel(0x00, 0xb1900028); /* sys_clksrc */
+ au_writel(0x00, 0xb1900100); /* sys_pininputen */
break;
case 0x01000000: /* Au1500 */
- writel(0x02, 0xb0000010); /* ac97_enable */
- writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
+ au_writel(0x02, 0xb0000010); /* ac97_enable */
+ au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
asm("sync");
- writel(0x00, 0xb017fffc); /* usbh_enable */
- writel(0x00, 0xb0200058); /* usbd_enable */
- writel(0x00, 0xb1520000); /* macen0 */
- writel(0x00, 0xb1520004); /* macen1 */
- writel(0x00, 0xb1100100); /* uart0_enable */
- writel(0x00, 0xb1400100); /* uart3_enable */
- writel(0x00, 0xb1900020); /* sys_freqctrl0 */
- writel(0x00, 0xb1900024); /* sys_freqctrl1 */
- writel(0x00, 0xb1900028); /* sys_clksrc */
- writel(0x00, 0xb1900100); /* sys_pininputen */
+ au_writel(0x00, 0xb017fffc); /* usbh_enable */
+ au_writel(0x00, 0xb0200058); /* usbd_enable */
+ au_writel(0x00, 0xb1520000); /* macen0 */
+ au_writel(0x00, 0xb1520004); /* macen1 */
+ au_writel(0x00, 0xb1100100); /* uart0_enable */
+ au_writel(0x00, 0xb1400100); /* uart3_enable */
+ au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
+ au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
+ au_writel(0x00, 0xb1900028); /* sys_clksrc */
+ au_writel(0x00, 0xb1900100); /* sys_pininputen */
break;
case 0x02000000: /* Au1100 */
- writel(0x02, 0xb0000010); /* ac97_enable */
- writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
+ au_writel(0x02, 0xb0000010); /* ac97_enable */
+ au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
asm("sync");
- writel(0x00, 0xb017fffc); /* usbh_enable */
- writel(0x00, 0xb0200058); /* usbd_enable */
- writel(0x00, 0xb0300040); /* ir_enable */
- writel(0x00, 0xb0520000); /* macen0 */
- writel(0x00, 0xb1000008); /* i2s_enable */
- writel(0x00, 0xb1100100); /* uart0_enable */
- writel(0x00, 0xb1200100); /* uart1_enable */
- writel(0x00, 0xb1400100); /* uart3_enable */
- writel(0x02, 0xb1600100); /* ssi0_enable */
- writel(0x02, 0xb1680100); /* ssi1_enable */
- writel(0x00, 0xb1900020); /* sys_freqctrl0 */
- writel(0x00, 0xb1900024); /* sys_freqctrl1 */
- writel(0x00, 0xb1900028); /* sys_clksrc */
- writel(0x00, 0xb1900100); /* sys_pininputen */
+ au_writel(0x00, 0xb017fffc); /* usbh_enable */
+ au_writel(0x00, 0xb0200058); /* usbd_enable */
+ au_writel(0x00, 0xb0300040); /* ir_enable */
+ au_writel(0x00, 0xb0520000); /* macen0 */
+ au_writel(0x00, 0xb1000008); /* i2s_enable */
+ au_writel(0x00, 0xb1100100); /* uart0_enable */
+ au_writel(0x00, 0xb1200100); /* uart1_enable */
+ au_writel(0x00, 0xb1400100); /* uart3_enable */
+ au_writel(0x02, 0xb1600100); /* ssi0_enable */
+ au_writel(0x02, 0xb1680100); /* ssi1_enable */
+ au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
+ au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
+ au_writel(0x00, 0xb1900028); /* sys_clksrc */
+ au_writel(0x00, 0xb1900100); /* sys_pininputen */
break;
default:
Index: rtc.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/rtc.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- rtc.c 30 Apr 2002 23:08:58 -0000 1.2
+++ rtc.c 1 May 2002 18:00:29 -0000 1.3
@@ -9,19 +9,20 @@
*/
#include <linux/mc146818rtc.h>
#include <asm/io.h>
+#include <asm/au1000.h>
#define PB1500_RTC_ADDR 0xAC000000
unsigned char std_rtc_read_data(unsigned long offset)
{
offset <<= 2;
- return (u8)(readl(offset + PB1500_RTC_ADDR) & 0xff);
+ return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff);
}
static void std_rtc_write_data(unsigned char data, unsigned long offset)
{
offset <<= 2;
- writel(data, offset + PB1500_RTC_ADDR);
+ au_writel(data, offset + PB1500_RTC_ADDR);
}
static int std_rtc_bcd_mode(void)
Index: serial.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/serial.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- serial.c 23 Mar 2002 02:13:01 -0000 1.8
+++ serial.c 1 May 2002 18:00:29 -0000 1.9
@@ -241,12 +241,12 @@
static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
{
- return (readl(info->port+offset) & 0xffff);
+ return (au_readl(info->port+offset) & 0xffff);
}
static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
{
- writel(value & 0xffff, info->port+offset);
+ au_writel(value & 0xffff, info->port+offset);
}
@@ -750,8 +750,8 @@
info->xmit.buf = (unsigned char *) page;
- if (readl(UART_MOD_CNTRL + state->port) != 0x3) {
- writel(3, UART_MOD_CNTRL + state->port);
+ if (au_readl(UART_MOD_CNTRL + state->port) != 0x3) {
+ au_writel(3, UART_MOD_CNTRL + state->port);
au_sync_delay(10);
}
#ifdef SERIAL_DEBUG_OPEN
@@ -988,7 +988,7 @@
info->flags &= ~ASYNC_INITIALIZED;
#ifndef CONFIG_REMOTE_DEBUG
- writel(0, UART_MOD_CNTRL + state->port);
+ au_writel(0, UART_MOD_CNTRL + state->port);
au_sync_delay(10);
#endif
restore_flags(flags);
@@ -2515,8 +2515,8 @@
if (!CONFIGURED_SERIAL_PORT(state))
return;
- if (readl(UART_MOD_CNTRL + state->port) != 0x3) {
- writel(3, UART_MOD_CNTRL + state->port);
+ if (au_readl(UART_MOD_CNTRL + state->port) != 0x3) {
+ au_writel(3, UART_MOD_CNTRL + state->port);
au_sync_delay(10);
}
@@ -2550,7 +2550,7 @@
serial_outp(info, UART_IER, 0);
#ifndef CONFIG_REMOTE_DEBUG
- writel(0, UART_MOD_CNTRL + state->port);
+ au_writel(0, UART_MOD_CNTRL + state->port);
au_sync_delay(10);
#endif
restore_flags(flags);
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/time.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- time.c 23 Mar 2002 02:13:01 -0000 1.11
+++ time.c 1 May 2002 18:00:29 -0000 1.12
@@ -123,13 +123,13 @@
static int jiffie_drift = 0;
kstat.irqs[0][irq]++;
- if (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
+ if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
/* should never happen! */
printk(KERN_WARNING "counter 0 w status eror\n");
return;
}
- pc0 = readl(SYS_TOYREAD);
+ pc0 = au_readl(SYS_TOYREAD);
if (pc0 < last_match20) {
/* counter overflowed */
time_elapsed = (0xffffffff - last_match20) + pc0;
@@ -146,7 +146,7 @@
}
last_pc0 = pc0;
- writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
+ au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
au_sync();
/* our counter ticks at 10.009765625 ms/tick, we we're running
@@ -176,27 +176,27 @@
save_and_cli(flags);
- counter = readl(SYS_COUNTER_CNTRL);
- writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
+ counter = au_readl(SYS_COUNTER_CNTRL);
+ au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
- while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
- writel(trim_divide-1, SYS_RTCTRIM); /* RTC now ticks at 32.768/16 kHz */
- while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
+ au_writel(trim_divide-1, SYS_RTCTRIM); /* RTC now ticks at 32.768/16 kHz */
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
- while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
- writel (0, SYS_TOYWRITE);
- while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
+ au_writel (0, SYS_TOYWRITE);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
- start = readl(SYS_RTCREAD);
+ start = au_readl(SYS_RTCREAD);
start += 2;
/* wait for the beginning of a new tick */
- while (readl(SYS_RTCREAD) < start);
+ while (au_readl(SYS_RTCREAD) < start);
/* Start r4k counter. */
write_32bit_cp0_register(CP0_COUNT, 0);
end = start + (32768 / trim_divide)/2; /* wait 0.5 seconds */
- while (end > readl(SYS_RTCREAD));
+ while (end > au_readl(SYS_RTCREAD));
count = read_32bit_cp0_register(CP0_COUNT);
cpu_speed = count * 2;
@@ -241,20 +241,20 @@
* counter 0 interrupt as a special irq and it doesn't show
* up under /proc/interrupts.
*/
- while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
- writel(0, SYS_TOYWRITE);
- while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
+ au_writel(0, SYS_TOYWRITE);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
- writel(readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
- writel(~0, SYS_WAKESRC);
+ au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
+ au_writel(~0, SYS_WAKESRC);
au_sync();
- while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
/* setup match20 to interrupt once every 10ms */
- last_pc0 = last_match20 = readl(SYS_TOYREAD);
- writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
+ last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
+ au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
au_sync();
- while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
startup_match20_interrupt();
#endif
@@ -282,7 +282,7 @@
unsigned long pc0;
unsigned long offset;
- pc0 = readl(SYS_TOYREAD);
+ pc0 = au_readl(SYS_TOYREAD);
if (pc0 < last_pc0) {
offset = 0xffffffff - last_pc0 + pc0;
printk("offset over: %x\n", (unsigned)offset);
Index: usbdev.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/usbdev.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- usbdev.c 23 Mar 2002 02:13:01 -0000 1.9
+++ usbdev.c 1 May 2002 18:00:29 -0000 1.10
@@ -591,7 +591,7 @@
spin_lock_irqsave(&ep->lock, flags);
- cs = readl(ep->reg->ctrl_stat) | USBDEV_CS_STALL;
+ cs = au_readl(ep->reg->ctrl_stat) | USBDEV_CS_STALL;
outl_sync(cs, ep->reg->ctrl_stat);
spin_unlock_irqrestore(&ep->lock, flags);
@@ -607,7 +607,7 @@
spin_lock_irqsave(&ep->lock, flags);
- cs = readl(ep->reg->ctrl_stat) & ~USBDEV_CS_STALL;
+ cs = au_readl(ep->reg->ctrl_stat) & ~USBDEV_CS_STALL;
outl_sync(cs, ep->reg->ctrl_stat);
spin_unlock_irqrestore(&ep->lock, flags);
@@ -635,8 +635,8 @@
spin_lock_irqsave(&ep->lock, flags);
bufptr = pkt->bufptr;
- while (readl(ep->reg->read_fifo_status) & USBDEV_FSTAT_FCNT_MASK) {
- *bufptr++ = readl(ep->reg->read_fifo) & 0xff;
+ while (au_readl(ep->reg->read_fifo_status) & USBDEV_FSTAT_FCNT_MASK) {
+ *bufptr++ = au_readl(ep->reg->read_fifo) & 0xff;
read_count++;
pkt->size++;
}
@@ -661,7 +661,7 @@
spin_lock_irqsave(&ep->lock, flags);
bufptr = pkt->bufptr;
- while ((readl(ep->reg->write_fifo_status) & USBDEV_FSTAT_FCNT_MASK) <
+ while ((au_readl(ep->reg->write_fifo_status) & USBDEV_FSTAT_FCNT_MASK) <
EP_FIFO_DEPTH) {
if (bufptr < pkt->buf + pkt->size) {
outl_sync(*bufptr++, ep->reg->write_fifo);
@@ -698,7 +698,7 @@
* working right, but flush it anyway just in case.
*/
flush_write_fifo(ep);
- cs = readl(ep->reg->ctrl_stat) & USBDEV_CS_STALL;
+ cs = au_readl(ep->reg->ctrl_stat) & USBDEV_CS_STALL;
cs |= (pkt->size << USBDEV_CS_TSIZE_BIT);
outl_sync(cs, ep->reg->ctrl_stat);
#ifdef USBDEV_PIO
@@ -731,7 +731,7 @@
dbg(__FUNCTION__ ": pkt=%p, ab=%d",
ep->inlist.head, get_dma_active_buffer(ep->indma));
- outl_sync(readl(ep->reg->ctrl_stat) & USBDEV_CS_STALL,
+ outl_sync(au_readl(ep->reg->ctrl_stat) & USBDEV_CS_STALL,
ep->reg->ctrl_stat);
//disable_dma(ep->indma);
free_packet(ep, &ep->inlist);
@@ -1084,7 +1084,7 @@
pkt_t *pkt = 0;
u32 cs;
- cs = readl(ep->reg->ctrl_stat);
+ cs = au_readl(ep->reg->ctrl_stat);
switch (fifo_num) {
case 0:
@@ -1151,7 +1151,7 @@
int i;
u32 status;
- status = readl(USB_DEV_INT_STATUS);
+ status = au_readl(USB_DEV_INT_STATUS);
outl_sync(status, USB_DEV_INT_STATUS); // ack'em
#ifdef USBDEV_PIO
@@ -1181,7 +1181,7 @@
u32 cs0, buff_done;
spin_lock(&ep->lock);
- cs0 = readl(ep->reg->ctrl_stat);
+ cs0 = au_readl(ep->reg->ctrl_stat);
// first check packet transmit done
if ((buff_done = get_dma_buffer_done(ep->indma)) != 0) {
|
