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[Linux-mips-commits]CVS: linux/arch/mips/au1000/pb1500 pci_ops.c,1.3,1.4 setup.c,1.7,1.8
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From: Pete P. <pp...@us...> - 2002-05-01 18:08:12
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Update of /cvsroot/linux-mips/linux/arch/mips/au1000/pb1500
In directory usw-pr-cvs1:/tmp/cvs-serv32242/arch/mips/au1000/pb1500
Modified Files:
pci_ops.c setup.c
Log Message:
Replaced readl/writel type of macros with au_readl/au_writel since
we need to enable software byte swapping in BE mode, but register
accesses should not be swapped. The Pb1x00 boards are now mostly BE
safe, but some external peripherals (external to the SOC) are not yet
usable in BE mode. USB has not been tested in BE mode either.
Index: pci_ops.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1500/pci_ops.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- pci_ops.c 23 Mar 2002 02:13:01 -0000 1.3
+++ pci_ops.c 1 May 2002 18:00:30 -0000 1.4
@@ -107,9 +107,9 @@
return -1;
}
- writel(((0x2000 << 16) | (readl(Au1500_PCI_STATCMD) & 0xffff)),
+ au_writel(((0x2000 << 16) | (au_readl(Au1500_PCI_STATCMD) & 0xffff)),
Au1500_PCI_STATCMD);
- //writel(readl(Au1500_PCI_CFG) & ~PCI_ERROR, Au1500_PCI_CFG);
+ //au_writel(au_readl(Au1500_PCI_CFG) & ~PCI_ERROR, Au1500_PCI_CFG);
au_sync_udelay(1);
/* setup the lower 31 bits of the 36 bit address */
@@ -127,9 +127,9 @@
#endif
if (access_type == PCI_ACCESS_WRITE) {
- writel(*data, config);
+ au_writel(*data, config);
} else {
- *data = readl(config);
+ *data = au_readl(config);
}
au_sync_udelay(2);
@@ -137,7 +137,7 @@
access_type, bus, device, where, *data, config);
/* check master abort */
- status = readl(Au1500_PCI_STATCMD);
+ status = au_readl(Au1500_PCI_STATCMD);
if (status & (1<<29)) {
*data = 0xffffffff;
return -1;
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1500/setup.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- setup.c 30 Apr 2002 23:08:19 -0000 1.7
+++ setup.c 1 May 2002 18:00:30 -0000 1.8
@@ -131,8 +131,8 @@
#endif
// set AUX clock to 12MHz * 8 = 96 MHz
- writel(8, SYS_AUXPLL);
- writel(0, SYS_PINSTATERD);
+ au_writel(8, SYS_AUXPLL);
+ au_writel(0, SYS_PINSTATERD);
udelay(100);
#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
@@ -148,24 +148,24 @@
#endif
/* zero and disable FREQ2 */
- sys_freqctrl = readl(SYS_FREQCTRL0);
+ sys_freqctrl = au_readl(SYS_FREQCTRL0);
sys_freqctrl &= ~0xFFF00000;
- writel(sys_freqctrl, SYS_FREQCTRL0);
+ au_writel(sys_freqctrl, SYS_FREQCTRL0);
/* zero and disable USBH/USBD clocks */
- sys_clksrc = readl(SYS_CLKSRC);
+ sys_clksrc = au_readl(SYS_CLKSRC);
sys_clksrc &= ~0x00007FE0;
- writel(sys_clksrc, SYS_CLKSRC);
+ au_writel(sys_clksrc, SYS_CLKSRC);
- sys_freqctrl = readl(SYS_FREQCTRL0);
+ sys_freqctrl = au_readl(SYS_FREQCTRL0);
sys_freqctrl &= ~0xFFF00000;
- sys_clksrc = readl(SYS_CLKSRC);
+ sys_clksrc = au_readl(SYS_CLKSRC);
sys_clksrc &= ~0x00007FE0;
// FREQ2 = aux/2 = 48 MHz
sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
- writel(sys_freqctrl, SYS_FREQCTRL0);
+ au_writel(sys_freqctrl, SYS_FREQCTRL0);
/*
* Route 48MHz FREQ2 into USB Host and/or Device
@@ -176,28 +176,28 @@
#ifdef CONFIG_AU1000_USB_DEVICE
sys_clksrc |= ((4<<7) | (0<<6) | (0<<5));
#endif
- writel(sys_clksrc, SYS_CLKSRC);
+ au_writel(sys_clksrc, SYS_CLKSRC);
- pin_func = readl(SYS_PINFUNC) & (u32)(~0x8000);
+ pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8000);
#ifndef CONFIG_AU1000_USB_DEVICE
// 2nd USB port is USB host
pin_func |= 0x8000;
#endif
- writel(pin_func, SYS_PINFUNC);
+ au_writel(pin_func, SYS_PINFUNC);
#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
#ifdef CONFIG_USB_OHCI
// enable host controller and wait for reset done
- writel(0x08, USB_HOST_CONFIG);
+ au_writel(0x08, USB_HOST_CONFIG);
udelay(1000);
- writel(0x0c, USB_HOST_CONFIG);
+ au_writel(0x0c, USB_HOST_CONFIG);
udelay(1000);
- readl(USB_HOST_CONFIG);
- while (!(readl(USB_HOST_CONFIG) & 0x10))
+ au_readl(USB_HOST_CONFIG);
+ while (!(au_readl(USB_HOST_CONFIG) & 0x10))
;
- readl(USB_HOST_CONFIG);
+ au_readl(USB_HOST_CONFIG);
#endif
#ifdef CONFIG_FB
@@ -218,9 +218,9 @@
#ifndef CONFIG_SERIAL_NONSTANDARD
/* don't touch the default serial console */
- writel(0, UART0_ADDR + UART_CLK);
+ au_writel(0, UART0_ADDR + UART_CLK);
#endif
- writel(0, UART3_ADDR + UART_CLK);
+ au_writel(0, UART3_ADDR + UART_CLK);
#ifdef CONFIG_BLK_DEV_IDE
ide_ops = &std_ide_ops;
@@ -228,40 +228,40 @@
#ifdef CONFIG_PCI
// Setup PCI bus controller
- writel(0, Au1500_PCI_CMEM);
- writel(0x00003fff, Au1500_CFG_BASE);
+ au_writel(0, Au1500_PCI_CMEM);
+ au_writel(0x00003fff, Au1500_CFG_BASE);
#if defined(__MIPSEB__)
- writel(0xf | (2<<6) | (1<<4), Au1500_PCI_CFG);
+ au_writel(0xf | (2<<6) | (1<<4), Au1500_PCI_CFG);
#else
- writel(0xf, Au1500_PCI_CFG);
+ au_writel(0xf, Au1500_PCI_CFG);
#endif
- writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
- writel(0, Au1500_PCI_MWBASE_REV_CCL);
- writel(0x02a00356, Au1500_PCI_STATCMD);
- writel(0x00003c04, Au1500_PCI_HDRTYPE);
- writel(0x00000008, Au1500_PCI_MBAR);
+ au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
+ au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
+ au_writel(0x02a00356, Au1500_PCI_STATCMD);
+ au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
+ au_writel(0x00000008, Au1500_PCI_MBAR);
au_sync();
#endif
- while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
- writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
+ au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
au_sync();
- while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
- writel(0, SYS_TOYTRIM);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
+ au_writel(0, SYS_TOYTRIM);
/* Enable BCLK switching */
- writel(0x00000060, 0xb190003c);
+ au_writel(0x00000060, 0xb190003c);
#ifdef CONFIG_RTC
rtc_ops = &pb1500_rtc_ops;
// Enable the RTC if not already enabled
- if (!(readl(0xac000028) & 0x20)) {
+ if (!(au_readl(0xac000028) & 0x20)) {
printk("enabling clock ...\n");
- writel((readl(0xac000028) | 0x20), 0xac000028);
+ au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
}
// Put the clock in BCD mode
if (readl(0xac00002C) & 0x4) { /* reg B */
- writel((readl(0xac00002c) & ~0x4), 0xac00002c);
+ au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
au_sync();
}
#endif
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