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[Linux-mips-commits]CVS: linux/include/asm-mips/rc32300 79eb355.h,NONE,1.1 ds1501rtc.h,NONE,1.1 rc32355.h,NONE,1.1 rc32355_dma.h,NONE,1.1 rc32355_eth.h,NONE,1.1 79s334.h,1.2,1.3 rc32300.h,1.3,1.4 rc32334.h,1.1,1.2
Update of /cvsroot/linux-mips/linux/include/asm-mips/rc32300
In directory usw-pr-cvs1:/tmp/cvs-serv16874/include/asm-mips/rc32300
Modified Files:
79s334.h rc32300.h rc32334.h
Added Files:
79eb355.h ds1501rtc.h rc32355.h rc32355_dma.h rc32355_eth.h
Log Message:
Initial IDT 79EB355 support.
--- NEW FILE: 79eb355.h ---
/*
*
* BRIEF MODULE DESCRIPTION
* Definitions for IDT 79EB355 evaluation board.
*
* Copyright 2002 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* st...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _79EB355_H_
#define _79EB355_H_
#define IDT_BUS_FREQ 75 // MHz
#define IDT_CLOCK_MULT 2
/* Memory map of 79EB355 board */
/* DRAM */
#define RAM_BASE 0x00000000
#define RAM_SIZE (32*1024*1024)
/* SRAM (device 1) */
#define SRAM_BASE 0x02000000
#define SRAM_SIZE 0x00100000
/* FLASH (device 2) */
#define FLASH_BASE 0x0C000000
#define FLASH_SIZE 0x00C00000
/* ATM PHY (device 4) */
#define ATM_PHY_BASE 0x14000000
/* TDM switch (device 3) */
#define TDM_BASE 0x1A000000
/* LCD panel (device 3) */
#define LCD_BASE 0x1A002000
/* RTC (DS1511W) (device 3) */
#define RTC_BASE 0x1A004000
/* NVRAM (256 bytes internal to the DS1511 RTC) */
#define NVRAM_ADDR RTC_BASE + 0x10
#define NVRAM_DATA RTC_BASE + 0x13
#define NVRAM_ENVSIZE_OFF 4
#define NVRAM_ENVSTART_OFF 32
#include <asm/rc32300/rc32355.h>
#include <asm/rc32300/ds1501rtc.h>
#endif /* _79EB355_H_ */
--- NEW FILE: ds1501rtc.h ---
/*
*
* BRIEF MODULE DESCRIPTION
* Definitions for Dallas DS1501 RTC present on IDT 79EB355 board.
*
* Copyright 2002 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* st...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _DS1501RTC_H_
#define _DS1501RTC_H_
/* Image of DS1501 registers */
typedef struct {
u8 secs;
u8 mins;
u8 hours;
u8 weekday;
u8 date;
u8 month;
u8 year;
u8 century;
u8 alarm_secs;
u8 alarm_mins;
u8 alarm_hours;
u8 alarm_day_date;
u8 watchdog_a;
u8 watchdog_secs;
u8 control_a;
u8 control_b;
u8 nvram_addr;
u8 dummy[2];
u8 nvram_data;
} ds1501_regs_t;
#define rtc ((ds1501_regs_t*)KSEG1ADDR(RTC_BASE))
/*
* Control register bit definitions
*/
#define TDC_ENA_BUFF 0x80
#define TDC_DIS_BUFF 0x7f
#define TDS_STOP 0x80
#endif /* _DS1501RTC_H */
--- NEW FILE: rc32355.h ---
/*
*
* BRIEF MODULE DESCRIPTION
* Definitions for IDT RC32355 CPU.
*
* Copyright 2002 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* st...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _RC32355_H_
#define _RC32355_H_
#include <linux/delay.h>
#include <asm/io.h>
/* Base address of internal registers */
#define RC32355_REG_BASE 0x18000000
/* System ID Registers */
#define CPU_SYSID (RC32355_REG_BASE + 0x00018)
#define CPU_BTADDR (RC32355_REG_BASE + 0x0001c)
#define CPU_REV (RC32355_REG_BASE + 0x0002c)
/* Reset Controller */
#define RESET_CNTL (RC32355_REG_BASE + 0x08000)
/* Device Controller */
#define DEV0_BASE (RC32355_REG_BASE + 0x10000)
#define DEV0_MASK (RC32355_REG_BASE + 0x10004)
#define DEV0_CNTL (RC32355_REG_BASE + 0x10008)
#define DEV0_TIMING (RC32355_REG_BASE + 0x1000c)
#define DEV_REG_OFFSET 0x10
/* SDRAM Controller */
#define SDRAM0_BASE (RC32355_REG_BASE + 0x18000)
#define SDRAM0_MASK (RC32355_REG_BASE + 0x18004)
#define SDRAM1_BASE (RC32355_REG_BASE + 0x18008)
#define SDRAM1_MASK (RC32355_REG_BASE + 0x1800c)
#define SDRAM_CNTL (RC32355_REG_BASE + 0x18010)
/* Bus Arbiter */
#define BUS_ARB_CNTL0 (RC32355_REG_BASE + 0x20000)
#define BUS_ARB_CNTL1 (RC32355_REG_BASE + 0x20004)
/* Counters/Timers */
#define TIMER0_COUNT (RC32355_REG_BASE + 0x28000)
#define TIMER0_COMPARE (RC32355_REG_BASE + 0x28004)
#define TIMER0_CNTL (RC32355_REG_BASE + 0x28008)
#define TIMER_REG_OFFSET 0x0C
/* System Integrity */
/* Interrupt Controller */
#define IC_GROUP0_PEND (RC32355_REG_BASE + 0x30000)
#define IC_GROUP0_MASK (RC32355_REG_BASE + 0x30004)
#define IC_GROUP_OFFSET 0x08
#define NUM_INTR_GROUPS 5
/*
* The IRQ mapping is as follows:
*
* IRQ Mapped To
* --- -------------------
* 0 SW0 (IP0) SW0 intr
* 1 SW1 (IP1) SW1 intr
* - Int0 (IP2) mapped to GROUP0_IRQ_BASE
* - Int1 (IP3) mapped to GROUP1_IRQ_BASE
* - Int2 (IP4) mapped to GROUP2_IRQ_BASE
* - Int3 (IP5) mapped to GROUP3_IRQ_BASE
* - Int4 (IP6) mapped to GROUP4_IRQ_BASE
* 7 Int5 (IP7) CP0 Timer
*
* IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
* internally on the RC32355 is routed to the Expansion
* Interrupt Controller.
*/
#define MIPS_CPU_TIMER_IRQ 7
#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 6) // DMA
#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 16) // ATM
#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 10) // TDM, Eth, USB, UARTs, I2C
#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 24) // GPIO
#define RC32355_NR_IRQS (GROUP4_IRQ_BASE + 32)
/* DMA - see rc32355_dma.h for full list of registers */
#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
#define DMA_CHAN_OFFSET 0x14
/* GPIO Controller */
/* TDM Bus */
/* 16550 UARTs */
#ifdef __MIPSEB__
#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
#else
#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
#endif
#define RC32300_BASE_BAUD (IDT_BUS_FREQ * 1000 * 1000 / 16)
#define RC32300_UART0_IRQ GROUP3_IRQ_BASE + 14
#define RC32300_UART1_IRQ GROUP3_IRQ_BASE + 17
/* ATM */
/* Ethernet - see rc32355_eth.h for full list of registers */
#define RC32355_ETH_BASE (RC32355_REG_BASE + 0x60000)
#endif /* _RC32355_H_ */
--- NEW FILE: rc32355_dma.h ---
/*
*
* BRIEF MODULE DESCRIPTION
* DMA controller defines on IDT RC32355 (Banyan)
*
* Copyright 2002 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* st...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef BANYAN_DMA_H
#define BANYAN_DMA_H
/*
* An image of one RC32355 dma channel registers
*/
typedef struct {
u32 dmac;
u32 dmas;
u32 dmasm;
u32 dmadptr;
u32 dmandptr;
} rc32355_dma_ch_t;
/*
* An image of all RC32355 dma channel registers
*/
typedef struct {
rc32355_dma_ch_t ch[16];
} rc32355_dma_regs_t;
#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
/* DMAC register layout */
#define DMAC_RUN 0x1 /* Halts processing when cleared */
#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
#define DMAC_MODE_MASK 0xC /* DMA operating mode */
#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
/* DMAS and DMASM register layout */
#define DMAS_F 0x01 /* Finished */
#define DMAS_D 0x02 /* Done */
#define DMAS_C 0x04 /* Chain */
#define DMAS_E 0x08 /* Error */
#define DMAS_H 0x10 /* Halt */
/* Polling count for DMAS_H bit in DMAS register after halting DMA */
#define DMA_HALT_TIMEOUT 500
static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
{
int timeout=1;
if (readl(&ch->dmac) & DMAC_RUN) {
writel(0, &ch->dmac);
for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
if (readl(&ch->dmas) & DMAS_H) {
writel(0, &ch->dmas);
break;
}
}
}
return timeout ? 0 : 1;
}
static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
{
writel(0, &ch->dmandptr);
writel(dma_addr, &ch->dmadptr);
}
static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
{
writel(dma_addr, &ch->dmandptr);
}
/* The following can be used to describe DMA channels 0 to 15, and the */
/* sub device's needed to select them in the DMADESC_DS_MASK field */
#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
#define DMA_DEV_ATMVCC(entry) 0
#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
#define DMA_DEV_ETHERIN 0 /* Ethernet input */
#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
#define DMA_DEV_TDMIN 0 /* TDM Bus input */
#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
#define DMA_CHAN_USBIN 13 /* USB input */
#define DMA_DEV_USBIN 0 /* USB input */
#define DMA_CHAN_USBOUT 14 /* USB output */
#define DMA_DEV_USBOUT 0 /* USB output */
#define DMA_CHAN_EXTERN 15 /* External DMA */
#define DMA_DEV_EXTERN 0 /* External DMA */
/*
* An RC32355 dma descriptor in system memory
*/
typedef struct {
u32 cmdstat; /* control and status */
u32 curr_addr; /* current address of data */
u32 devcs; /* peripheral-specific control and status */
u32 link; /* link to next descriptor */
} rc32355_dma_desc_t;
/* Values for the descriptor cmdstat word */
#define DMADESC_F 0x80000000u /* Finished bit */
#define DMADESC_D 0x40000000u /* Done bit */
#define DMADESC_T 0x20000000u /* Terminated bit */
#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
#define DMADESC_COD 0x04000000u /* Chain On Done */
#define DMADESC_COF 0x02000000u /* Chain On Finished */
#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
#define DMADESC_DS_SHIFT 20 /* Device Select shift */
#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
#define DMA_DEVCMD(devcmd) \
(((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
#define DMA_DS(ds) \
(((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
#define DMA_COUNT(count) \
((count) & DMADESC_COUNT_MASK)
#endif /* BANYAN_DMA_H */
--- NEW FILE: rc32355_eth.h ---
/*
*
* BRIEF MODULE DESCRIPTION
* Ethernet registers on IDT RC32355 (Banyan)
*
* Copyright 2002 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* st...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef BANYAN_ETHER_H
#define BANYAN_ETHER_H
#include <asm/rc32300/rc32355_dma.h>
/*
* A partial image of the RC32355 ethernet registers
*/
typedef struct {
u32 ethintfc;
u32 ethfifott;
u32 etharc;
u32 ethhash0;
u32 ethhash1;
u32 ethfifost;
u32 ethfifos;
u32 ethodeops;
u32 ethis;
u32 ethos;
u32 ethmcp;
u32 _u1;
u32 ethid;
u32 _u2;
u32 _u3;
u32 _u4;
u32 ethod;
u32 _u5;
u32 _u6;
u32 _u7;
u32 ethodeop;
u32 _u8[43];
u32 ethsal0;
u32 ethsah0;
u32 ethsal1;
u32 ethsah1;
u32 ethsal2;
u32 ethsah2;
u32 ethsal3;
u32 ethsah3;
u32 ethrbc;
u32 ethrpc;
u32 ethrupc;
u32 ethrfc;
u32 ethtbc;
u32 ethgpf;
u32 _u9[50];
u32 ethmac1;
u32 ethmac2;
u32 ethipgt;
u32 ethipgr;
u32 ethclrt;
u32 ethmaxf;
u32 _u10;
u32 ethmtest;
u32 miimcfg;
u32 miimcmd;
u32 miimaddr;
u32 miimwtd;
u32 miimrdd;
u32 miimind;
u32 _u11;
u32 _u12;
u32 ethcfsa0;
u32 ethcfsa1;
u32 ethcfsa2;
} rc32355_eth_regs_t;
#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
/* for n in { 0, 1, 2, 3 } */
#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
/* for n in { 0, 1, 2 } */
#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
/*
* Register Interpretations follow
*/
/******************************************************************************
* ETHINTFC register
*****************************************************************************/
#define ETHERINTFC_EN (1<<0)
#define ETHERINTFC_ITS (1<<1)
#define ETHERINTFC_RES (1<<2)
#define ETHERINTFC_RIP (1<<2)
#define ETHERINTFC_JAM (1<<3)
/******************************************************************************
* ETHFIFOTT register
*****************************************************************************/
#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
/******************************************************************************
* ETHARC register
*****************************************************************************/
#define ETHERARC_PRO (1<<0)
#define ETHERARC_AM (1<<1)
#define ETHERARC_AFM (1<<2)
#define ETHERARC_AB (1<<3)
/******************************************************************************
* ETHHASH registers
*****************************************************************************/
#define ETHERHASH0(v) (((v)&0xffff)<<0)
#define ETHERHASH1(v) (((v)&0xffff)<<0)
/******************************************************************************
* ETHSA registers
*****************************************************************************/
#define ETHERSAL0(v) (((v)&0xffff)<<0)
#define ETHERSAL1(v) (((v)&0xffff)<<0)
#define ETHERSAL2(v) (((v)&0xffff)<<0)
#define ETHERSAL3(v) (((v)&0xffff)<<0)
#define ETHERSAH0(v) (((v)&0xff)<<0)
#define ETHERSAH1(v) (((v)&0xff)<<0)
#define ETHERSAH2(v) (((v)&0xff)<<0)
#define ETHERSAH3(v) (((v)&0xff)<<0)
/******************************************************************************
* ETHFIFOST register
*****************************************************************************/
#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
/******************************************************************************
* ETHFIFOS register
*****************************************************************************/
#define ETHERFIFOS_IR (1<<0)
#define ETHERFIFOS_OR (1<<1)
#define ETHERFIFOS_OVR (1<<2)
#define ETHERFIFOS_UND (1<<3)
/******************************************************************************
* DATA registers
*****************************************************************************/
#define ETHERID(v) (((v)&0xffff)<<0)
#define ETHEROD(v) (((v)&0xffff)<<0)
/******************************************************************************
* ETHODEOPS register
*****************************************************************************/
#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
/******************************************************************************
* ETHODEOP register
*****************************************************************************/
#define ETHERODEOP(v) (((v)&0xffff)<<0)
/******************************************************************************
* ETHIS register
*****************************************************************************/
#define ETHERIS_EOP (1<<0)
#define ETHERIS_ROK (1<<2)
#define ETHERIS_FM (1<<3)
#define ETHERIS_MP (1<<4)
#define ETHERIS_BP (1<<5)
#define ETHERIS_VLT (1<<6)
#define ETHERIS_CF (1<<7)
#define ETHERIS_OVR (1<<8)
#define ETHERIS_CRC (1<<9)
#define ETHERIS_CV (1<<10)
#define ETHERIS_DB (1<<11)
#define ETHERIS_LE (1<<12)
#define ETHERIS_LOR (1<<13)
#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
/******************************************************************************
* ETHOS register
*****************************************************************************/
#define ETHEROS_T (1<<0)
#define ETHEROS_TOK (1<<6)
#define ETHEROS_MP (1<<7)
#define ETHEROS_BP (1<<8)
#define ETHEROS_UND (1<<9)
#define ETHEROS_OF (1<<10)
#define ETHEROS_ED (1<<11)
#define ETHEROS_EC (1<<12)
#define ETHEROS_LC (1<<13)
#define ETHEROS_TD (1<<14)
#define ETHEROS_CRC (1<<15)
#define ETHEROS_LE (1<<16)
#define ETHEROS_CC(v) (((v)&0xf)<<17)
#define ETHEROS_PFD (1<<21)
/******************************************************************************
* Statistics registers
*****************************************************************************/
#define ETHERRBC(v) (((v)&0xffff)<<0)
#define ETHERRPC(v) (((v)&0xffff)<<0)
#define ETHERRUPC(v) (((v)&0xffff)<<0)
#define ETHERRFC(v) (((v)&0xffff)<<0)
#define ETHERTBC(v) (((v)&0xffff)<<0)
/******************************************************************************
* ETHGPF register
*****************************************************************************/
#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
/******************************************************************************
* MAC registers
*****************************************************************************/
//ETHMAC1
#define ETHERMAC1_RE (1<<0)
#define ETHERMAC1_PAF (1<<1)
#define ETHERMAC1_RFC (1<<2)
#define ETHERMAC1_TFC (1<<3)
#define ETHERMAC1_LB (1<<4)
#define ETHERMAC1_MR (1<<15)
//ETHMAC2
#define ETHERMAC2_FD (1<<0)
#define ETHERMAC2_FLC (1<<1)
#define ETHERMAC2_HFE (1<<2)
#define ETHERMAC2_DC (1<<3)
#define ETHERMAC2_CEN (1<<4)
#define ETHERMAC2_PE (1<<5)
#define ETHERMAC2_VPE (1<<6)
#define ETHERMAC2_APE (1<<7)
#define ETHERMAC2_PPE (1<<8)
#define ETHERMAC2_LPE (1<<9)
#define ETHERMAC2_NB (1<<12)
#define ETHERMAC2_BP (1<<13)
#define ETHERMAC2_ED (1<<14)
//ETHIPGT
#define ETHERIPGT(v) (((v)&0x3f)<<0)
//ETHIPGR
#define ETHERIPGR_IPGR1(v) (((v)&0x3f)<<0)
#define ETHERIPGR_IPGR2(v) (((v)&0x3f)<<8)
//ETHCLRT
#define ETHERCLRT_MAXRET(v) (((v)&0x3f)<<0)
#define ETHERCLRT_COLWIN(v) (((v)&0x3f)<<8)
//ETHMAXF
#define ETHERMAXF(v) (((v)&0x3f)<<0)
//ETHMTEST
#define ETHERMTEST_TB (1<<2)
//ETHMCP
#define ETHERMCP_DIV(v) (((v)&0xff)<<0)
//MIIMCFG
#define ETHERMIIMCFG_CS(v) (((v)&0x3)<<2)
#define ETHERMIIMCFG_R (1<<15)
//MIIMCMD
#define ETHERMIIMCMD_RD (1<<0)
#define ETHERMIIMCMD_SCN (1<<1)
//MIIMADDR
#define ETHERMIIMADDR_REGADDR(v) (((v)&0x1f)<<0)
#define ETHERMIIMADDR_PHYADDR(v) (((v)&0x1f)<<8)
//MIIMWTD
#define ETHERMIIMWTD(v) (((v)&0xff)<<0)
//MIIMRDD
#define ETHERMIIMRDD(v) (((v)&0xff)<<0)
//MIIMIND
#define ETHERMIIMIND_BSY (1<<0)
#define ETHERMIIMIND_SCN (1<<1)
#define ETHERMIIMIND_NV (1<<2)
//DMA DEVCS IN
#define ETHERDMA_IN_LENGTH(v) (((v)&0xffff)<<16)
#define ETHERDMA_IN_CES (1<<14)
#define ETHERDMA_IN_LOR (1<<13)
#define ETHERDMA_IN_LE (1<<12)
#define ETHERDMA_IN_DB (1<<11)
#define ETHERDMA_IN_CV (1<<10)
#define ETHERDMA_IN_CRC (1<<9)
#define ETHERDMA_IN_OVR (1<<8)
#define ETHERDMA_IN_CF (1<<7)
#define ETHERDMA_IN_VLT (1<<6)
#define ETHERDMA_IN_BP (1<<5)
#define ETHERDMA_IN_MP (1<<4)
#define ETHERDMA_IN_FM (1<<3)
#define ETHERDMA_IN_ROK (1<<2)
#define ETHERDMA_IN_LD (1<<1)
#define ETHERDMA_IN_FD (1<<0)
//DMA DEVCS OUT
#define ETHERDMA_OUT_CC(v) (((v)&0xf)<<17)
#define ETHERDMA_OUT_CNT 0x001e0000
#define ETHERDMA_OUT_SHFT 17
#define ETHERDMA_OUT_LE (1<<16)
#define ETHERDMA_OUT_CRC (1<<15)
#define ETHERDMA_OUT_TD (1<<14)
#define ETHERDMA_OUT_LC (1<<13)
#define ETHERDMA_OUT_EC (1<<12)
#define ETHERDMA_OUT_ED (1<<11)
#define ETHERDMA_OUT_OF (1<<10)
#define ETHERDMA_OUT_UND (1<<9)
#define ETHERDMA_OUT_BP (1<<8)
#define ETHERDMA_OUT_MP (1<<7)
#define ETHERDMA_OUT_TOK (1<<6)
#define ETHERDMA_OUT_HEN (1<<5)
#define ETHERDMA_OUT_CEN (1<<4)
#define ETHERDMA_OUT_PEN (1<<3)
#define ETHERDMA_OUT_OEN (1<<2)
#define ETHERDMA_OUT_LD (1<<1)
#define ETHERDMA_OUT_FD (1<<0)
#define RCV_ERRS \
(ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
#define TX_ERRS \
(ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
#define IS_RCV_ROK(X) (((X) & (1<<2)) >> 2) /* Receive Okay */
#define IS_RCV_FM(X) (((X) & (1<<3)) >> 3) /* Is Filter Match */
#define IS_RCV_MP(X) (((X) & (1<<4)) >> 4) /* Is it MP */
#define IS_RCV_BP(X) (((X) & (1<<5)) >> 5) /* Is it BP */
#define IS_RCV_VLT(X) (((X) & (1<<6)) >> 6) /* VLAN Tag Detect */
#define IS_RCV_CF(X) (((X) & (1<<7)) >> 7) /* Control Frame */
#define IS_RCV_OVR_ERR(X) (((X) & (1<<8)) >> 8) /* Receive Overflow */
#define IS_RCV_CRC_ERR(X) (((X) & (1<<9)) >> 9) /* CRC Error */
#define IS_RCV_CV_ERR(X) (((X) & (1<<10))>>10) /* Code Violation */
#define IS_RCV_DB_ERR(X) (((X) & (1<<11))>>11) /* Dribble Bits */
#define IS_RCV_LE_ERR(X) (((X) & (1<<12))>>12) /* Length error */
#define IS_RCV_LOR_ERR(X) (((X) & (1<<13))>>13) /* Length Out of
Range */
#define IS_RCV_CES_ERR(X) (((X) & (1<<14))>>14) /* Preamble error */
#define RCVPKT_LENGTH(X) (((X) & 0xFFFF0000)>>16) /* Length of the
received packet */
#define IS_TX_TOK(X) (((X) & (1<<6) ) >> 6 ) /* Transmit Okay */
#define IS_TX_MP(X) (((X) & (1<<7) ) >> 7 ) /* Multicast */
#define IS_TX_BP(X) (((X) & (1<<8) ) >> 8 ) /* Broadcast */
#define IS_TX_UND_ERR(X) (((X) & (1<<9) ) >> 9 ) /* Transmit FIFO
Underflow */
#define IS_TX_OF_ERR(X) (((X) & (1<<10)) >>10 ) /* Oversized frame */
#define IS_TX_ED_ERR(X) (((X) & (1<<11)) >>11 ) /* Excessive
deferral */
#define IS_TX_EC_ERR(X) (((X) & (1<<12)) >>12 ) /* Excessive
collisions */
#define IS_TX_LC_ERR(X) (((X) & (1<<13)) >>13 ) /* Late Collision */
#define IS_TX_TD_ERR(X) (((X) & (1<<14)) >>14 ) /* Transmit deferred*/
#define IS_TX_CRC_ERR(X) (((X) & (1<<15)) >>15 ) /* CRC Error */
#define IS_TX_LE_ERR(X) (((X) & (1<<16)) >>16 ) /* Length Error */
#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17) /* Collision Count */
#endif /* BANYAN_ETHER_H */
Index: 79s334.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/rc32300/79s334.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- 79s334.h 17 Jan 2002 21:06:46 -0000 1.2
+++ 79s334.h 29 Apr 2002 23:05:12 -0000 1.3
@@ -36,7 +36,8 @@
/* NVRAM */
#define NVRAM_BASE 0x12000000
-#define NVRAM_SIZE 512
+#define NVRAM_ENVSIZE_OFF 4
+#define NVRAM_ENVSTART_OFF 0x40
/* LCD 4-digit display */
#define LCD_CLEAR 0x14000400
@@ -44,8 +45,6 @@
#define LCD_DIGIT1 0x14000008
#define LCD_DIGIT2 0x14000007
#define LCD_DIGIT3 0x14000003
-
-extern int idtprintf(const char *fmt, ...);
/* Interrupts routed on 79S334A board (see rc32334.h) */
#define RC32334_SCC8530_IRQ 2
Index: rc32300.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/rc32300/rc32300.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- rc32300.h 24 Jan 2002 20:13:54 -0000 1.3
+++ rc32300.h 29 Apr 2002 23:05:12 -0000 1.4
@@ -40,6 +40,8 @@
#include <asm/rc32300/79eb355.h>
#endif
+extern int idtprintf(const char *fmt, ...);
+
/* cpu pipeline flush */
static inline void rc32300_sync(void)
{
@@ -63,37 +65,29 @@
* swapping should be done when accessing the internal
* registers.
*/
-static inline u8 rc32300_inb(unsigned long pa)
-{
- return *((volatile u8 *)(mips_io_port_base + pa));
-}
-static inline u16 rc32300_inw(unsigned long pa)
-{
- return *((volatile u16 *)(mips_io_port_base + pa));
-}
-static inline u32 rc32300_inl(unsigned long pa)
+static inline u8 rc32300_readb(unsigned long pa)
{
- return *((volatile u32 *)(mips_io_port_base + pa));
+ return *((volatile u8 *)KSEG1ADDR(pa));
}
-static inline void rc32300_outb(u8 val, unsigned long pa)
+static inline u16 rc32300_readw(unsigned long pa)
{
- *((volatile u8 *)(mips_io_port_base + pa)) = val;
+ return *((volatile u16 *)KSEG1ADDR(pa));
}
-static inline void rc32300_outw(u16 val, unsigned long pa)
+static inline u32 rc32300_readl(unsigned long pa)
{
- *((volatile u16 *)(mips_io_port_base + pa)) = val;
+ return *((volatile u32 *)KSEG1ADDR(pa));
}
-static inline void rc32300_outl(u32 val, unsigned long pa)
+static inline void rc32300_writeb(u8 val, unsigned long pa)
{
- *((volatile u32 *)(mips_io_port_base + pa)) = val;
+ *((volatile u8 *)KSEG1ADDR(pa)) = val;
}
-static inline u32 rc32300_readl(unsigned long va)
+static inline void rc32300_writew(u16 val, unsigned long pa)
{
- return *((volatile u32 *)va);
+ *((volatile u16 *)KSEG1ADDR(pa)) = val;
}
-static inline void rc32300_writel(u32 val, unsigned long va)
+static inline void rc32300_writel(u32 val, unsigned long pa)
{
- *((volatile u32 *)va) = val;
+ *((volatile u32 *)KSEG1ADDR(pa)) = val;
}
/*
Index: rc32334.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/rc32300/rc32334.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- rc32334.h 17 Jan 2002 20:22:51 -0000 1.1
+++ rc32334.h 29 Apr 2002 23:05:12 -0000 1.2
@@ -90,16 +90,6 @@
#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
-/* 16550 UARTs */
-#ifdef __MIPSEB__
-#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
-#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
-#else
-#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
-#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
-#endif
-#define RC32300_BASE_BAUD (IDT_BUS_FREQ * 1000 * 1000 / 16)
-
/*
* DMA
*
@@ -169,6 +159,19 @@
#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
+
+/* 16550 UARTs */
+#ifdef __MIPSEB__
+#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
+#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
+#else
+#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
+#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
+#endif
+#define RC32300_BASE_BAUD (IDT_BUS_FREQ * 1000 * 1000 / 16)
+
+#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
+#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
#endif /* _RC32334_H_ */
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