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[Linux-mips-commits]CVS: linux/arch/mips/rc32300/79S334 idtdisplay.c,NONE,1.1 Makefile,1.1,1.2 irq.c,1.8,1.9 pci_fixup.c,1.5,1.6 pci_ops.c,1.4,1.5 setup.c,1.8,1.9 prom.c,1.4,NONE
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From: Steve L. <slo...@us...> - 2002-04-29 23:05:15
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Update of /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334
In directory usw-pr-cvs1:/tmp/cvs-serv16874/arch/mips/rc32300/79S334
Modified Files:
Makefile irq.c pci_fixup.c pci_ops.c setup.c
Added Files:
idtdisplay.c
Removed Files:
prom.c
Log Message:
Initial IDT 79EB355 support.
--- NEW FILE: idtdisplay.c ---
/*
*
* BRIEF MODULE DESCRIPTION
* 79S334A 4 digits display.
*
* Copyright 2002 THOMSON multimedia.
* Author: Stephane Fillod & Guillaume Lorand
* fi...@th...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/config.h>
#include <linux/version.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/miscdevice.h>
#include <linux/init.h>
#include <asm/uaccess.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/rc32300/rc32300.h>
#include <asm/rc32300/idtdisplay.h>
/**
* @name module parameters
* @param minor minor number of the device (major is gived by misc device)
* @param delay delay in milliseconds between scrolling on the display
*/
//@{
MODULE_PARM(minor, "i") ;
MODULE_PARM(delay, "i") ;
//@}
/**
* @name locales variables
*/
//@{
static unsigned int minor __initdata = IDTDISPLAY_MINOR ; /*< minor number of the device */
static unsigned int delay = IDTDISPLAY_DELAY ; /*< delay between scrolling in ms */
static DECLARE_MUTEX(idtdisp_sem) ;
//@}
/**
* internal function which clean the display
*/
static inline void idtdisp_clean(void)
{
readb(KSEG1ADDR(LCD_CLEAR)) ;
}
/**
* internal function which display a char on the display
* @param i display number
* @param c character to write
*/
static inline void idtdisp_char(int i, char c)
{
switch(i) {
case 0: writeb(c, KSEG1ADDR(LCD_DIGIT0)) ; break ;
case 1: writeb(c, KSEG1ADDR(LCD_DIGIT1)) ; break ;
case 2: writeb(c, KSEG1ADDR(LCD_DIGIT2)) ; break ;
case 3: writeb(c, KSEG1ADDR(LCD_DIGIT3)) ; break ;
default: writeb('?', KSEG1ADDR(LCD_DIGIT0)) ; break ;
}
}
/**
* internal function which display a string on the display
* @param s string to write
*/
static inline void idtdisp_str(char *s)
{
int i;
if(s == NULL) {
idtdisp_clean();
return;
}
for(i = 0; i < 4 && s[i]; i++)
idtdisp_char(i, s[i]);
}
/**
* open the display device
* @return always 0
*/
static int idtdisp_open(struct inode *inode, struct file *file) ;
/**
* close the display device
* @return always 0
*/
static int idtdisp_release(struct inode *inode, struct file *file) ;
/**
* write to the display device
* @return an errno code if it failed or else the number of writen bytes
*/
static ssize_t idtdisp_write(struct file *file, const char *buffer, size_t count, loff_t *ppos) ;
/**
* clean the display device
* @return an errno code if it failed or else the number of readen bytes
*/
static ssize_t idtdisp_read(struct file *file, char *buffer, size_t count, loff_t *ppos) ;
/**
* perform ioctl request on the display device
* @return an errno code if it failed or 0 if it succed.
*/
static int idtdisp_ioctl( struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg ) ;
/**
* initialize the display device
* @return the result of misc registration
*/
int __init idtdisp_init(void) ;
/**
* release previous allocation
*/
static void __exit idtdisp_exit (void) ;
static struct file_operations displaydev_fops = {
owner: THIS_MODULE,
read : idtdisp_read,
write: idtdisp_write,
ioctl: idtdisp_ioctl,
open: idtdisp_open,
release: idtdisp_release,
};
static struct miscdevice displaydev = {
minor: IDTDISPLAY_MINOR,
name : "idtdisplay",
fops : &displaydev_fops,
};
/*
* Now all the various file operations that we export.
*/
static int idtdisp_open(struct inode *inode, struct file *file)
{
MOD_INC_USE_COUNT;
return 0;
}
static int idtdisp_release(struct inode *inode, struct file *file)
{
MOD_DEC_USE_COUNT;
return 0;
}
static ssize_t idtdisp_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
{
char contents [IDTDISPLAY_BUF_SIZE] ;
int buf_size = (count > IDTDISPLAY_BUF_SIZE) ? IDTDISPLAY_BUF_SIZE : count;
int cpt = 0 ;
int retval;
if (copy_from_user (contents, buffer, buf_size))
return -EFAULT;
if (down_interruptible (&idtdisp_sem))
return -EINTR;
idtdisp_str(&contents[cpt]);
while (cpt++ < buf_size-4) {
current->state = TASK_INTERRUPTIBLE;
retval = schedule_timeout(MS_TO_HZ(delay)) ;
if (retval != 0)
break;
idtdisp_str(&contents[cpt]);
}
up(&idtdisp_sem) ;
return cpt+4 > buf_size ? buf_size : cpt+4;
}
static ssize_t idtdisp_read (struct file *file, char *buffer, size_t count, loff_t *ppos)
{
idtdisp_clean();
return 0;
}
static int idtdisp_ioctl( struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg )
{
switch(cmd) {
case IDTDISPLAY_IOCTL_DELAY:
if (arg > 5000)
return -EINVAL;
delay = arg ;
break ;
case IDTDISPLAY_IOCTL_CLEAN:
idtdisp_clean();
break;
case IDTDISPLAY_IOCTL_WRITE_CHAR:
{
struct idtdisp_wc_struct wc;
if (copy_from_user(&wc, (struct idtdisp_wc_struct*)arg, sizeof(struct idtdisp_wc_struct)))
return -EFAULT ;
if (down_interruptible (&idtdisp_sem))
return -EINTR;
idtdisp_char(wc.nb, wc.ch);
up (&idtdisp_sem) ;
break;
}
case IDTDISPLAY_IOCTL_WRITE_4:
{
char w4[4] ;
if (copy_from_user(w4, (char *)arg, 4) )
return -EFAULT ;
if (down_interruptible (&idtdisp_sem))
return -EINTR;
idtdisp_str(w4);
up (&idtdisp_sem) ;
break;
}
default:
return -ENOSYS;
break ;
}
return 0;
}
int __init idtdisp_init(void)
{
int ret;
displaydev.minor = minor ;
ret = misc_register(&displaydev);
return ret ;
}
static void __exit idtdisp_exit (void)
{
misc_deregister(&displaydev);
}
/**
* @name init/exit functions
* fuction use by insmod to run and stop the module
*/
//@{
module_init(idtdisp_init);
module_exit(idtdisp_exit);
//@}
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/Makefile,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- Makefile 15 Jan 2002 00:34:07 -0000 1.1
+++ Makefile 29 Apr 2002 23:05:11 -0000 1.2
@@ -17,7 +17,7 @@
O_TARGET := idt-79S334.o
-obj-y := irq.o prom.o setup.o
+obj-y := irq.o setup.o idtdisplay.o
obj-$(CONFIG_PCI) += pci_fixup.o pci_ops.o
include $(TOPDIR)/Rules.make
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/irq.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- irq.c 24 Jan 2002 20:13:34 -0000 1.8
+++ irq.c 29 Apr 2002 23:05:11 -0000 1.9
@@ -106,17 +106,17 @@
};
#define READ_PEND(g) \
- rc32300_inl(IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
+ rc32300_readl(IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
#define WRITE_PEND(g,val) \
- rc32300_outl((val), IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
+ rc32300_writel((val), IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
#define READ_MASK(g) \
- rc32300_inl(IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
+ rc32300_readl(IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
#define WRITE_MASK(g,val) \
- rc32300_outl((val), IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
+ rc32300_writel((val), IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
#define READ_CLEAR(g) \
- rc32300_inl(IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
+ rc32300_readl(IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
#define WRITE_CLEAR(g,val) \
- rc32300_outl((val), IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
+ rc32300_writel((val), IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
static inline int irq_to_group(unsigned int irq_nr)
{
Index: pci_fixup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/pci_fixup.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- pci_fixup.c 8 Feb 2002 00:33:55 -0000 1.5
+++ pci_fixup.c 29 Apr 2002 23:05:11 -0000 1.6
@@ -94,7 +94,7 @@
/*
* Enable CPU and IP Bus Error exceptions, and disable WatchDog.
*/
- rc32300_outl(0x18, CPU_IP_BUSERR_CNTL);
+ rc32300_writel(0x18, CPU_IP_BUSERR_CNTL);
}
void __init pcibios_fixup_irqs(void)
Index: pci_ops.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/pci_ops.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- pci_ops.c 24 Jan 2002 20:13:34 -0000 1.4
+++ pci_ops.c 29 Apr 2002 23:05:11 -0000 1.5
@@ -63,7 +63,7 @@
extern char * __init prom_getcmdline(void);
#define PCI_CFG_SET(slot,func,off) \
- rc32300_outl((0x80000000 | ((slot)<<11) | ((func)<<8) | (off)), \
+ rc32300_writel((0x80000000 | ((slot)<<11) | ((func)<<8) | (off)), \
PCI_CFG_CNTL)
static int
@@ -85,9 +85,9 @@
rc32300_sync();
if (type == PCI_ACCESS_WRITE)
- rc32300_outl(*data, PCI_CFG_DATA);
+ rc32300_writel(*data, PCI_CFG_DATA);
else
- *data = rc32300_inl(PCI_CFG_DATA);
+ *data = rc32300_readl(PCI_CFG_DATA);
rc32300_sync();
/*
@@ -239,13 +239,13 @@
u32 val;
printk("RC32334 PCI Bridge Config:\n");
- printk("PCI_MEM1_BASE: 0x%08x\n", rc32300_inl(PCI_MEM1_BASE));
- printk("PCI_MEM2_BASE: 0x%08x\n", rc32300_inl(PCI_MEM2_BASE));
- printk("PCI_MEM3_BASE: 0x%08x\n", rc32300_inl(PCI_MEM3_BASE));
- printk("PCI_IO1_BASE: 0x%08x\n", rc32300_inl(PCI_IO1_BASE));
- printk("PCI_ARBITRATION:0x%08x\n", rc32300_inl(PCI_ARBITRATION));
- printk("PCI_CPU_MEM1_BASE:0x%08x\n", rc32300_inl(PCI_CPU_MEM1_BASE));
- printk("PCI_CPU_IO_BASE:0x%08x\n", rc32300_inl(PCI_CPU_IO_BASE));
+ printk("PCI_MEM1_BASE: 0x%08x\n", rc32300_readl(PCI_MEM1_BASE));
+ printk("PCI_MEM2_BASE: 0x%08x\n", rc32300_readl(PCI_MEM2_BASE));
+ printk("PCI_MEM3_BASE: 0x%08x\n", rc32300_readl(PCI_MEM3_BASE));
+ printk("PCI_IO1_BASE: 0x%08x\n", rc32300_readl(PCI_IO1_BASE));
+ printk("PCI_ARBITRATION:0x%08x\n", rc32300_readl(PCI_ARBITRATION));
+ printk("PCI_CPU_MEM1_BASE:0x%08x\n", rc32300_readl(PCI_CPU_MEM1_BASE));
+ printk("PCI_CPU_IO_BASE:0x%08x\n", rc32300_readl(PCI_CPU_IO_BASE));
for (i=0; i<17; i++) {
config_read(0, 0, i*4, &val);
@@ -258,7 +258,7 @@
char *argptr;
/* allow writes to bridge config space */
- rc32300_outl(4, PCI_ARBITRATION);
+ rc32300_writel(4, PCI_ARBITRATION);
config_write(0, 0, PCI_VENDOR_ID,
PCI_VENDOR_ID_IDT | (PCI_DEVICE_ID_IDT_RC32334 << 16));
@@ -288,7 +288,7 @@
/* retry timeout, trdy timeout */
config_write(0, 0, PCI_INTERRUPT_LINE+4, 0x00008080);
- rc32300_outl(0x00000000, PCI_CFG_CNTL);
+ rc32300_writel(0x00000000, PCI_CFG_CNTL);
/*
* CPU -> PCI address translation. Make CPU physical and
@@ -322,21 +322,21 @@
*/
/* mem space 1 */
- rc32300_outl(rc32334_res_pci_mem1.start | SWAP_BIT, PCI_MEM1_BASE);
+ rc32300_writel(rc32334_res_pci_mem1.start | SWAP_BIT, PCI_MEM1_BASE);
/* mem space 2 */
- rc32300_outl(rc32334_res_pci_mem2.start | SWAP_BIT, PCI_MEM2_BASE);
+ rc32300_writel(rc32334_res_pci_mem2.start | SWAP_BIT, PCI_MEM2_BASE);
/* mem space 3 */
- rc32300_outl(rc32334_res_pci_mem3.start | SWAP_BIT, PCI_MEM3_BASE);
+ rc32300_writel(rc32334_res_pci_mem3.start | SWAP_BIT, PCI_MEM3_BASE);
/* i/o space */
- rc32300_outl(rc32334_res_pci_io.start | SWAP_BIT, PCI_IO1_BASE);
+ rc32300_writel(rc32334_res_pci_io.start | SWAP_BIT, PCI_IO1_BASE);
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "pciextarb")) == NULL) {
/* use internal arbiter, 0=round robin, 1=fixed */
- rc32300_outl(0, PCI_ARBITRATION);
+ rc32300_writel(0, PCI_ARBITRATION);
} else {
/* use external arbiter */
- rc32300_outl(2, PCI_ARBITRATION);
+ rc32300_writel(2, PCI_ARBITRATION);
}
/*
@@ -345,8 +345,8 @@
* Let PCI see system memory at 0x00000000 physical
*/
- rc32300_outl(0x0 | SWAP_BIT, PCI_CPU_MEM1_BASE); /* mem space */
- rc32300_outl(0x0 | SWAP_BIT, PCI_CPU_IO_BASE); /* i/o space */
+ rc32300_writel(0x0 | SWAP_BIT, PCI_CPU_MEM1_BASE); /* mem space */
+ rc32300_writel(0x0 | SWAP_BIT, PCI_CPU_IO_BASE); /* i/o space */
rc32300_sync();
}
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/setup.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- setup.c 8 Feb 2002 00:33:55 -0000 1.8
+++ setup.c 29 Apr 2002 23:05:11 -0000 1.9
@@ -64,7 +64,10 @@
int i, len;
char str[256];
static int lcd_digit_reg[4] = {
- LCD_DIGIT0, LCD_DIGIT1, LCD_DIGIT2, LCD_DIGIT3
+ KSEG1ADDR(LCD_DIGIT0),
+ KSEG1ADDR(LCD_DIGIT1),
+ KSEG1ADDR(LCD_DIGIT2),
+ KSEG1ADDR(LCD_DIGIT3)
};
va_start(args, fmt);
@@ -72,22 +75,15 @@
va_end(args);
len = len > 4 ? 4 : len;
- inb(LCD_CLEAR); // clear the display
+ readb(KSEG1ADDR(LCD_CLEAR)); // clear the display
for (i = 0; i < len; i++) {
if (str[i])
- outb(str[i], lcd_digit_reg[i]);
+ writeb(str[i], lcd_digit_reg[i]);
}
return len;
}
-struct resource rc32334_res_ram = {
- "RAM",
- 0,
- RAM_SIZE,
- IORESOURCE_MEM
-};
-
struct resource rc32334_res_pci_mem1;
struct resource rc32334_res_pci_mem2;
struct resource rc32334_res_pci_mem3;
@@ -137,10 +133,13 @@
extern void rc32300_ack_irq(unsigned int irq_nr);
printk("RC32334 %s bus error:\n", data ? "Data" : "Instruction");
- printk(" EPC == %08lx, RA == %08lx\n", regs->cp0_epc, regs->regs[31]);
- printk(" CPU bus address == %08x\n", rc32300_readl(CPU_BUSERR_ADDR));
- printk(" IP bus address == %08x\n", rc32300_inl(CPU_IP_BUSERR_ADDR));
- cntl = rc32300_inl(CPU_IP_BUSERR_CNTL);
+ printk(" EPC == %08lx, RA == %08lx\n",
+ regs->cp0_epc, regs->regs[31]);
+ printk(" CPU bus address == %08x\n",
+ rc32300_readl(CPU_BUSERR_ADDR));
+ printk(" IP bus address == %08x\n",
+ rc32300_readl(CPU_IP_BUSERR_ADDR));
+ cntl = rc32300_readl(CPU_IP_BUSERR_CNTL);
printk(" Bus error occured on a %s on %s bus\n",
cntl & 1 ? "read" : "write",
cntl & 4 ? "CPU" : "IP");
@@ -149,9 +148,9 @@
rc32300_ack_irq(GROUP4_IRQ_BASE+4); // ack timer 4 rollover intr
rc32300_ack_irq(GROUP4_IRQ_BASE+5); // ack timer 5 rollover intr
rc32300_ack_irq(GROUP1_IRQ_BASE); // ack bus error intr
- rc32300_outl(cntl & ~0x07, CPU_IP_BUSERR_CNTL);
+ rc32300_writel(cntl & ~0x07, CPU_IP_BUSERR_CNTL);
- //die_if_kernel("Oops", regs);
+ die_if_kernel("Oops", regs);
force_sig(SIGBUS, current);
}
@@ -171,24 +170,24 @@
* Disable CPU and IP Bus Error exceptions (PCI scan will
* cause bus timeouts), and disable WatchDog.
*/
- rc32300_outl(0x98, CPU_IP_BUSERR_CNTL);
+ rc32300_writel(0x98, CPU_IP_BUSERR_CNTL);
- rc32300_outl(0, TIMER0_CNTL + 4*TIMER_REG_OFFSET);
- rc32300_outl(0, TIMER0_CNTL + 5*TIMER_REG_OFFSET);
- rc32300_outl(0x3fff, TIMER0_COMPARE + 4*TIMER_REG_OFFSET);
- rc32300_outl(0x3fff, TIMER0_COMPARE + 5*TIMER_REG_OFFSET);
- rc32300_outl(1, TIMER0_CNTL + 4*TIMER_REG_OFFSET);
- rc32300_outl(1, TIMER0_CNTL + 5*TIMER_REG_OFFSET);
+ rc32300_writel(0, TIMER0_CNTL + 4*TIMER_REG_OFFSET);
+ rc32300_writel(0, TIMER0_CNTL + 5*TIMER_REG_OFFSET);
+ rc32300_writel(0x3fff, TIMER0_COMPARE + 4*TIMER_REG_OFFSET);
+ rc32300_writel(0x3fff, TIMER0_COMPARE + 5*TIMER_REG_OFFSET);
+ rc32300_writel(1, TIMER0_CNTL + 4*TIMER_REG_OFFSET);
+ rc32300_writel(1, TIMER0_CNTL + 5*TIMER_REG_OFFSET);
#if 0
printk(__FUNCTION__ ": Timer4 Cntl = 0x%08x\n",
- rc32300_inl(TIMER0_CNTL + 4*TIMER_REG_OFFSET));
+ rc32300_readl(TIMER0_CNTL + 4*TIMER_REG_OFFSET));
printk(__FUNCTION__ ": Timer4 Cmp = 0x%08x\n",
- rc32300_inl(TIMER0_COMPARE + 4*TIMER_REG_OFFSET));
+ rc32300_readl(TIMER0_COMPARE + 4*TIMER_REG_OFFSET));
printk(__FUNCTION__ ": Timer5 Cntl = 0x%08x\n",
- rc32300_inl(TIMER0_CNTL + 5*TIMER_REG_OFFSET));
+ rc32300_readl(TIMER0_CNTL + 5*TIMER_REG_OFFSET));
printk(__FUNCTION__ ": Timer5 Cmp = 0x%08x\n",
- rc32300_inl(TIMER0_COMPARE + 5*TIMER_REG_OFFSET));
+ rc32300_readl(TIMER0_COMPARE + 5*TIMER_REG_OFFSET));
request_irq(GROUP4_IRQ_BASE+4, bus_error_interrupt, SA_INTERRUPT,
"RC32334 CPU Bus Error", NULL);
@@ -228,7 +227,7 @@
bus_error_init();
- inb(LCD_CLEAR); // clear the 4-digit LCD display
+ readb(KSEG1ADDR(LCD_CLEAR)); // clear the 4-digit LCD display
#ifdef CONFIG_BLK_DEV_INITRD
ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
@@ -244,37 +243,37 @@
printk(__FUNCTION__ ": CPU_BUSERR_ADDR = 0x%08x\n",
rc32300_readl(CPU_BUSERR_ADDR));
printk(__FUNCTION__ ": CPU_IP_BTA = 0x%08x\n",
- rc32300_inl(CPU_IP_BTA));
+ rc32300_readl(CPU_IP_BTA));
printk(__FUNCTION__ ": CPU_IP_ADDR_LATCH = 0x%08x\n",
- rc32300_inl(CPU_IP_ADDR_LATCH));
+ rc32300_readl(CPU_IP_ADDR_LATCH));
printk(__FUNCTION__ ": CPU_IP_ARBITRATION = 0x%08x\n",
- rc32300_inl(CPU_IP_ARBITRATION));
+ rc32300_readl(CPU_IP_ARBITRATION));
printk(__FUNCTION__ ": CPU_IP_BUSERR_CNTL = 0x%08x\n",
- rc32300_inl(CPU_IP_BUSERR_CNTL));
+ rc32300_readl(CPU_IP_BUSERR_CNTL));
printk(__FUNCTION__ ": CPU_IP_BUSERR_ADDR = 0x%08x\n",
- rc32300_inl(CPU_IP_BUSERR_ADDR));
+ rc32300_readl(CPU_IP_BUSERR_ADDR));
printk(__FUNCTION__ ": CPU_IP_SYSID = 0x%08x\n",
- rc32300_inl(CPU_IP_SYSID));
+ rc32300_readl(CPU_IP_SYSID));
printk(__FUNCTION__ ": MEM_BASE_BANK0 = 0x%08x\n",
- rc32300_inl(MEM_BASE_BANK0));
+ rc32300_readl(MEM_BASE_BANK0));
printk(__FUNCTION__ ": MEM_MASK_BANK0 = 0x%08x\n",
- rc32300_inl(MEM_MASK_BANK0));
+ rc32300_readl(MEM_MASK_BANK0));
printk(__FUNCTION__ ": MEM_CNTL_BANK0 = 0x%08x\n",
- rc32300_inl(MEM_CNTL_BANK0));
+ rc32300_readl(MEM_CNTL_BANK0));
printk(__FUNCTION__ ": MEM_BASE_BANK1 = 0x%08x\n",
- rc32300_inl(MEM_BASE_BANK1));
+ rc32300_readl(MEM_BASE_BANK1));
printk(__FUNCTION__ ": MEM_MASK_BANK1 = 0x%08x\n",
- rc32300_inl(MEM_MASK_BANK1));
+ rc32300_readl(MEM_MASK_BANK1));
printk(__FUNCTION__ ": MEM_CNTL_BANK1 = 0x%08x\n",
- rc32300_inl(MEM_CNTL_BANK1));
+ rc32300_readl(MEM_CNTL_BANK1));
printk(__FUNCTION__ ": MEM_CNTL_BANK2 = 0x%08x\n",
- rc32300_inl(MEM_CNTL_BANK2));
+ rc32300_readl(MEM_CNTL_BANK2));
printk(__FUNCTION__ ": MEM_CNTL_BANK3 = 0x%08x\n",
- rc32300_inl(MEM_CNTL_BANK3));
+ rc32300_readl(MEM_CNTL_BANK3));
printk(__FUNCTION__ ": MEM_CNTL_BANK4 = 0x%08x\n",
- rc32300_inl(MEM_CNTL_BANK4));
+ rc32300_readl(MEM_CNTL_BANK4));
printk(__FUNCTION__ ": MEM_CNTL_BANK5 = 0x%08x\n",
- rc32300_inl(MEM_CNTL_BANK5));
+ rc32300_readl(MEM_CNTL_BANK5));
#endif
#ifdef CONFIG_PCI
--- prom.c DELETED ---
|
