[Linux-mips-commits]CVS: linux/include/asm-mips/vr41xx e15.h,1.1,1.2

[Leblanc f. <fle...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/vr41xx
In directory usw-pr-cvs1:/tmp/cvs-serv14927/include/asm-mips/vr41xx

Modified Files:
	e15.h 
Log Message:
Casio e15 support improvement.


Index: e15.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/vr41xx/e15.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- e15.h	19 Mar 2002 14:22:21 -0000	1.1
+++ e15.h	23 Apr 2002 13:14:29 -0000	1.2
@@ -7,14 +7,18 @@
  *
  * Copyright 2002 Yoichi Yuasa
  *                yu...@hh...
- * Copyright 2002 francois Leblanc <fra...@ce...>
  *          
- *
  *  This program is free software; you can redistribute it and/or modify it
  *  under the terms of the GNU General Public License as published by the
  *  Free Software Foundation; either version 2 of the License, or (at your
  *  option) any later version.
  */
+/*
+ * Changes:
+ * Francois Leblanc <fra...@ce...> Wed, 27 Mar 2002
+ * - Report dependant config from vr41xx-platdep.h here.
+ * 
+ */
 #ifndef __CASIO_E15_H
 #define __CASIO_E15_H
 
@@ -30,10 +34,62 @@
 #define VR41XX_ISA_IO_BASE		0x14000000
 #define VR41XX_ISA_IO_SIZE		0x04000000
 
-#define IO_PORT_BASE			KSEG1ADDR(VR41XX_ISA_IO_BASE)
-#define IO_PORT_RESOURCE_START		0
-#define IO_PORT_RESOURCE_END		VR41XX_ISA_IO_SIZE
-#define IO_MEM_RESOURCE_START		VR41XX_ISA_MEM_BASE
-#define IO_MEM_RESOURCE_END		(VR41XX_ISA_MEM_BASE + VR41XX_ISA_MEM_SIZE)
+#define IO_PORT_BASE            KSEG1ADDR(VR41XX_ISA_IO_BASE)
+#define IO_PORT_RESOURCE_START  0
+#define IO_PORT_RESOURCE_END    VR41XX_ISA_IO_SIZE
+#define IO_MEM_RESOURCE_START   VR41XX_ISA_MEM_BASE
+#define IO_MEM_RESOURCE_END     (VR41XX_ISA_MEM_BASE + VR41XX_ISA_MEM_SIZE)
+
+/*
+ * Board specific hardware description
+ */
+#define VIDEORAM_BASE     (KSEG1 + 0x0a000000)
+#define VIDEORAM_SIZE     (256 * 1024) /* ??? */
+#define FB_X_RES          240
+#define FB_X_VIRTUAL_RES  512
+#define FB_Y_RES          320
+#define FB_BPP            4
+#define FB_IS_GREY        1
+#define FB_IS_INVERSE     0 //1
+
+// GPIO[27] is speaker power on/off bit
+#define VR41XX_ENABLE_SPEAKER()		\
+	{				\
+		int flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODH |= VR41XX_GIUPIODH_GPIO27; \
+		restore_flags(flags);	\
+	}
+#define VR41XX_DISABLE_SPEAKER()		\
+	{				\
+		int flags;	\
+		save_and_cli(flags);	\
+		*VR41XX_GIUPIODH &= ~VR41XX_GIUPIODH_GPIO27; \
+		restore_flags(flags);	\
+	}
+
+/*
+ * LCD control management 
+ */
+extern void gpiolcd_setup(void);
+extern int gpiolcd_backlight(int n);
+extern int get_gpiolcd_backlight(void);
+extern int gpiolcd_contrast(int n);
+extern int get_gpiolcd_contrast(void);
+extern int gpiolcd_lcdpower(int on);
+#define	LCD_SETUP() gpiolcd_setup()
+#define	LCD_BACKLIGHT(n) gpiolcd_backlight(n) 
+#define	GET_LCD_BACKLIGHT() get_gpiolcd_backlight()
+#define	LCD_CONTRAST(n) gpiolcd_contrast(n)
+#define	GET_LCD_CONTRAST() get_gpiolcd_contrast()
+#define	LCD_POWER(n) gpiolcd_lcdpower(n)
+
+/* GPIO buttons mapping from GPIO0 to GPIO31 */
+#define GPIO_BTN_MAP { \
+	0, 0, 0, 0, 0, BTN_POWER_GPIO, BTN_ACTION, BTN_EXIT, \
+	BTN_AP3, BTN_AP2, BTN_AP1, BTN_AP4, BTN_UP, BTN_DOWN, BTN_SYNC, \
+	0, 0, BTN_NOTIFICATION, 0, BTN_NOTIFICATION, 0, 0, 0, \
+	0, 0, 0, 0, 0, BTN_NORTH, BTN_WEST, BTN_EAST \
+}
 
 #endif /* __CASIO_E15_H */