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[Linux-mips-commits]CVS: linux/arch/mips/cobalt via.c,1.4,1.5 Makefile,1.14,1.15 int-handler.S,1.5,1.6 irq.c,1.13,1.14 pci.c,1.7,1.8 promcon.c,1.1,1.2 setup.c,1.19,1.20
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From: Paul M. <le...@us...> - 2002-04-21 20:56:26
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Update of /cvsroot/linux-mips/linux/arch/mips/cobalt
In directory usw-pr-cvs1:/tmp/cvs-serv19938/arch/mips/cobalt
Modified Files:
Makefile int-handler.S irq.c pci.c promcon.c setup.c
Added Files:
via.c
Log Message:
Make cobalt work again. (Hopefully the end of OSS syncing for today.)
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/Makefile,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -d -r1.14 -r1.15
--- Makefile 6 Jan 2002 00:07:31 -0000 1.14
+++ Makefile 21 Apr 2002 20:56:23 -0000 1.15
@@ -17,8 +17,9 @@
O_TARGET := cobalt.o
obj-y += rtc_dallas.o irq.o int-handler.o \
- reset.o setup.o ide.o
+ reset.o setup.o ide.o via.o
+obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_NEW_PCI) += pci_ops.o pci_fixups.o
obj-$(CONFIG_REMOTE_DEBUG) += promcon.o
Index: int-handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/int-handler.S,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- int-handler.S 19 Dec 2001 01:07:25 -0000 1.5
+++ int-handler.S 21 Apr 2002 20:56:23 -0000 1.6
@@ -1,42 +1,24 @@
/*
- * arch/mips/cobalt/int-handler.S
+ * Cobalt interrupt handler
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ld...@ag...)
+ *
*/
+
+#include <linux/config.h>
#include <asm/asm.h>
#include <asm/mipsregs.h>
+#include <asm/cobalt/cobalt.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
/*
- * Descriptions of interrupts on different typs of Cobalt MIPS-based products.
- *
- * Qube1:
- * H/W int0: Galileo CPU interrupt (pin 61)
- * H/W int1: Coprocessor interrupt
- * H/W int2: Ethernet interrupt
- * H/W int3: Spare
- * H/W int4: VIA interrupt (pin 145)
- * H/W int5: Galileo PCI interrupt (pin 196)
- * H/W NMI: VIA NMI (pin 146)
- *
- * RaQ1:
- * H/W int0: Galileo CPU interrupt (pin 61)
- * H/W int1: Ethernet interrupt
- * H/W int2: 2nd Ethernet interrupt
- * H/W int3: Serial interrupt
- * H/W int4: VIA interrupt (pin 145)
- * H/W int5: Galileo PCI interrupt (pin 196)
- * H/W NMI: VIA NMI (pin 146)
- *
- * Qube2/RaQ2:
- * H/W int0: Galileo CPU interrupt (pin 61)
- * H/W int1: Ethernet interrupt
- * H/W int2: 2nd ethernet interrupt
- * H/W int3: Serial interrupt
- * H/W int4: VIA interrupt
- * H/W int5: Galileo PCI interrupt (pin 196)
- * H/W NMI: VIA NMI (pin 146)
- *
- * cobalt_handle_int: Interrupt handler for the twenty-seven board.
+ * cobalt_handle_int: Interrupt handler for Cobalt boards
*/
.text
.set noreorder
@@ -45,139 +27,79 @@
NESTED(cobalt_handle_int, PT_SIZE, sp)
SAVE_ALL
CLI
-
- /*
- * MIPS CPU's store the interrupt information in the CAUSE and STATUS
- * registers. The CAUSE register contains the pending interrupts, and
- * the STATUS register has the current interrupt mask.
- *
- * Interrupt Interrupt CAUSE Pending STATUS Mask
- * Type Number Bit Name Bit Name
- * --------- --------- --- ---- --- ----
- * Software 0 8 IP0 8 IM0
- * Software 1 9 IP1 9 IM1
- * Hardware 0 10 IP2 10 IM2
- * Hardware 1 11 IP3 11 IM3
- * Hardware 2 12 IP4 12 IM4
- * Hardware/
- * Coprocessor 3 13 IP5 13 IM5
- * Hardware 4 14 IP6 14 IM6
- * Hardware/
- * Timer 5 15 IP7 15 IM7
- *
- * So, get the CAUSE and STATUS registers, apply the interrupt mask to
- * the pending interrupts (via an AND)
- * Get pending Interrupts
- */
.set at
/*
* Get pending Interrupts
*/
- mfc0 t0, CP0_CAUSE # get irq mask
- mfc0 t1, CP0_STATUS # get enabled interrupts
- and t0, t1
-
-/* Such a kind of cascade is optimal for R5000 */
-
- andi t1, t0,STATUSF_IP2 /* Check for Galileo timer */
- bnez t1, ll_galileo_irq
+ mfc0 s0,CP0_CAUSE # get irq mask
- andi t1, t0,STATUSF_IP6 /* Check for Via chip */
- bnez t1, ll_via_irq
- andi t1, t0,STATUSF_IP3
- bnez t1, ll_ethernet0_irq
-/*
- * This should be conditional, and not used for the cube-1, but
- * there is not a config flag that is useful.
- */
+ andi a0,s0,CAUSEF_IP2 /* Check for Galileo timer */
+ beq a0,zero,1f
+ andi a0,s0,CAUSEF_IP6 /* Check for Via chip */
- andi t1, t0,STATUSF_IP4
- bnez t1, ll_ethernet1_irq
- andi t1, t0,STATUSF_IP5
- bnez t1, ll_serial_irq
- andi t1, t0,STATUSF_IP7
- bnez t1, ll_pci_irq
+ /* Galileo interrupt */
+ jal galileo_irq
+ move a0,sp
+ j ret_from_irq
nop
- /* wrong alarm ... */
- j spurious_interrupt
- nop
- END(cobalt_handle_int)
+1:
+ beq a0,zero,1f /* Check IP6 */
+ andi a0,s0,CAUSEF_IP3
- .align 5
- .set reorder
- ll_galileo_irq: move a0,sp
- jal cobalt_gt64111_irq
- nop
+ /* Via interrupt */
+ jal via_irq
+ move a0,sp
j ret_from_irq
nop
- .align 5
- .set reorder
-ll_via_irq:
- move a0, sp
- jal cobalt_via_irq
- nop
- j ret_from_irq
- nop
+1:
+ beq a0,zero,1f /* Check IP3 */
+ andi a0,s0,CAUSEF_IP4
- .align 5
- .set reorder
-ll_ethernet0_irq:
- mfc0 s0, CP0_STATUS # mask interrupt
- ori t0, s0, (STATUSF_IP3 | STATUSF_IP4)
- xori t0, (STATUSF_IP3 | STATUSF_IP4)
- mtc0 t0, CP0_STATUS
- li a0, 4
- move a1, sp
+ /* Ethernet 0 interrupt */
+ li a0,4
jal do_IRQ
- nop
- mtc0 s0,CP0_STATUS
+ move a1,sp
+
j ret_from_irq
nop
- .align 5
- .set reorder
-ll_serial_irq:
- li a0,7
- move a1,sp
+1:
+ beq a0,zero,1f /* Check IP4 */
+ andi a0,s0,CAUSEF_IP5
+
+ /* Ethernet 1 interrupt */
+ li a0,13
jal do_IRQ
- nop
+ move a1,sp
+
j ret_from_irq
nop
+1:
+ beq a0,zero,1f /* Check IP5 */
+ andi a0,s0,CAUSEF_IP7
- .align 5
- .set reorder
-ll_ethernet1_irq:
- mfc0 s0, CP0_STATUS # mask interrupt
-
- ori t0, s0, (STATUSF_IP3 | STATUSF_IP4)
- xori t0, (STATUSF_IP3 | STATUSF_IP4)
-
- mtc0 t0, CP0_STATUS
- li a0, 13
- move a1, sp
+ /* Serial interrupt */
+ li a0,7
jal do_IRQ
- nop
- mtc0 s0, CP0_STATUS
+ move a1,sp
+
j ret_from_irq
nop
+1:
+ beq a0,zero,1f /* Check IP7 */
+ nop
-#
-# This is pretty weird. The "pci" interrupt on the hardware
-# skematic is from the PCI side of the galileo, so we would
-# only get interrupts here if WE write the control register
-# that normally enables the cpu to send interrupts to the PCI.
-#
-# If you want to interrupt a PCI card, look elsewhere.
-#
- .align 5
- .set reorder
-ll_pci_irq:
- li a0, 7
- move a1, sp
+ /* PCI interrupt */
+ li a0,9
jal do_IRQ
- nop
+ move a1,sp
+
+1:
j ret_from_irq
nop
+
+ END(cobalt_handle_int)
+
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/irq.c,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- irq.c 2 Jan 2002 18:19:35 -0000 1.13
+++ irq.c 21 Apr 2002 20:56:23 -0000 1.14
@@ -1,104 +1,223 @@
/*
- * Interrupt handling for the VIA ISA bridge.
+ * IRQ vector handles
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ld...@ag...)
*
- * Everything the same ... just different ...
*/
-#include <linux/init.h>
+
#include <linux/kernel.h>
-#include <asm/atomic.h>
-#include <linux/irq.h>
-#include <asm/cobalt/cobalt.h>
-#include <asm/ptrace.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+
+#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
+#include <asm/system.h>
-extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
+#include <asm/cobalt/cobalt.h>
+
+/* Cobalt Exception handler */
extern void cobalt_handle_int(void);
-extern void init_i8259_irqs(void);
-#ifdef CONFIG_REMOTE_DEBUG
-extern void set_debug_traps(void);
-extern void breakpoint(void);
-#endif
+/* Via masking routines */
+extern void unmask_irq(unsigned int irqr);
+extern void mask_irq(unsigned int irq);
-#undef DEBUG
-asmlinkage void cobalt_via_irq(struct pt_regs *regs)
-{
- char mstat, sstat;
+/*
+ * We have two types of interrupts that we handle, ones that come
+ * in through the CPU interrupt lines, and ones that come in on
+ * the via chip. The CPU mappings are:
+ * 0,1 - S/W (ignored)
+ * 2 - Galileo chip (timer)
+ * 3 - Tulip 0 + NCR SCSI
+ * 4 - Tulip 1
+ * 5 - 16550 UART
+ * 6 - VIA southbridge PIC
+ * 7 - PCI
+ *
+ * The VIA chip is a master/slave 8259 setup and has the
+ * following interrupts
+ * 8 - RTC
+ * 14 - IDE0
+ * 15 - IDE1
+ *
+ * In the table we use a 1 to indicate that we use a VIA interrupt
+ * line, and IE_IRQx to indicate that we use a CPU interrupt line
+ *
+ * We map all of these onto linux IRQ #s 0-15 and forget the rest
+ */
+#define NOINT_LINE 0
+#define CPUINT_LINE(x) IE_IRQ##x
+#define VIAINT_LINE 1
- /* Read Master Status */
- isa_writeb(0x0C, 0x20);
- mstat = isa_readb(0x20);
+#define COBALT_IRQS 16
-#ifdef DEBUG
- printk("Via: Cause=%x Status=%x mstat=%x ",
- regs->cp0_cause, regs->cp0_status, mstat);
-#endif
+static unsigned short irqnr_to_type[COBALT_IRQS] =
+{ CPUINT_LINE(0), NOINT_LINE, VIAINT_LINE, NOINT_LINE,
+ CPUINT_LINE(1), NOINT_LINE, NOINT_LINE, CPUINT_LINE(3),
+ VIAINT_LINE, CPUINT_LINE(5), NOINT_LINE, NOINT_LINE,
+ NOINT_LINE, CPUINT_LINE(2), VIAINT_LINE, VIAINT_LINE };
- if (mstat < 0) {
- mstat &= 0x7f;
- if (mstat != 2) {
- do_IRQ(mstat, regs);
- isa_writeb(mstat | 0x20, 0x20);
- } else {
- sstat = isa_readb(0xA0);
+/*
+ * Cobalt CPU irq
+ */
- /* Slave interrupt */
- isa_writeb(0x0C, 0xA0);
- sstat = isa_readb(0xA0);
+static void enable_cpu_irq(unsigned int irq)
+{
+ unsigned long flags;
-#ifdef DEBUG
- printk("Via: Cause=%x Status=%x sstat=%x ",
- regs->cp0_cause, regs->cp0_status, sstat);
-#endif
- if (sstat < 0) {
- do_IRQ((sstat + 8) & 0x7f, regs);
- isa_writeb(0x22, 0x20);
- isa_writeb((sstat & 0x7f) | 0x20, 0xA0);
- } else {
- printk("Spurious slave interrupt...\n");
- }
- }
- } else
- printk("Spurious master interrupt...");
+ save_and_cli(flags);
+ change_cp0_status(irqnr_to_type[irq], irqnr_to_type[irq]);
+ restore_flags(flags);
}
-#define GALILEO_INTCAUSE 0xb4000c18
-#define GALILEO_T0EXP 0x00000100
+static unsigned startup_cpu_irq(unsigned int irq)
+{
+ enable_cpu_irq(irq);
-asmlinkage void cobalt_gt64111_irq(struct pt_regs *regs)
+ return 0;
+}
+
+static void disable_cpu_irq(unsigned int irq)
{
- unsigned long irq_src = *((unsigned long *) GALILEO_INTCAUSE);
+ unsigned long flags;
-#if 0
- printk("Galileo: Cause=%x Status=%x IRQsrc=%x\n",
- regs->cp0_cause, regs->cp0_status, irq_src);
-#endif
+ save_and_cli(flags);
+ change_cp0_status(irqnr_to_type[irq], ~(irqnr_to_type[irq]));
+ restore_flags(flags);
+}
- /* Check for timer irq ... */
- if (irq_src & GALILEO_T0EXP) {
- do_IRQ(0, regs);
- *((volatile unsigned long *) GALILEO_INTCAUSE) = 0;
- } else {
- long cause = read_32bit_cp0_register(CP0_CAUSE),
- status = read_32bit_cp0_register(CP0_STATUS);
+#define shutdown_cpu_irq disable_cpu_irq
+#define mask_and_ack_cpu_irq disable_cpu_irq
- printk("Spurious Galileo interrupt...");
- printk("Galileo: Cause=%lx Status=%lx IRQsrc=%lx\n", cause, status, irq_src);
- }
+static void end_cpu_irq(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+ enable_cpu_irq(irq);
+}
+
+static struct hw_interrupt_type cobalt_cpu_irq_type = {
+ "Cobalt CPU",
+ startup_cpu_irq,
+ shutdown_cpu_irq,
+ enable_cpu_irq,
+ disable_cpu_irq,
+ mask_and_ack_cpu_irq,
+ end_cpu_irq,
+ NULL
+};
+
+
+/*
+ * Cobalt VIA irq
+ */
+
+static void enable_via_irq(unsigned int irq)
+{
+ unsigned long flags;
+
+ save_and_cli(flags);
+ unmask_irq(irq);
+ restore_flags(flags);
}
+static unsigned startup_via_irq(unsigned int irq)
+{
+ enable_via_irq(irq);
+
+ return 0;
+}
+
+static void disable_via_irq(unsigned int irq)
+{
+ unsigned long flags;
+
+ save_and_cli(flags);
+ mask_irq(irq);
+ restore_flags(flags);
+}
+
+#define shutdown_via_irq disable_via_irq
+#define mask_and_ack_via_irq disable_via_irq
+
+static void end_via_irq(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+ enable_via_irq(irq);
+}
+
+static struct hw_interrupt_type cobalt_via_irq_type = {
+ "Cobalt VIA",
+ startup_via_irq,
+ shutdown_via_irq,
+ enable_via_irq,
+ disable_via_irq,
+ mask_and_ack_via_irq,
+ end_via_irq,
+ NULL
+};
+
+
+static struct irqaction via_irq2 = {
+ no_action, 0, 0, "slave cascade", NULL, NULL
+};
+
+static struct resource pic1_io_resource = {
+ "VIA PIC Master", 0x20, 0x3f, IORESOURCE_BUSY
+};
+
+static struct resource pic2_io_resource = {
+ "VIA PIC Slave", 0xa0, 0xbf, IORESOURCE_BUSY
+};
+
+
void __init init_IRQ(void)
{
- set_except_vector(0, cobalt_handle_int);
+ int i;
+ /* Initialise all of the IRQ descriptors */
init_generic_irq();
- init_i8259_irqs();
-#ifdef CONFIG_REMOTE_DEBUG
- set_debug_traps();
- breakpoint();
-#endif
+ /* Map the irqnr to the type int we have */
+ for (i=0; i < COBALT_IRQS; i++) {
+ if (irqnr_to_type[i] >= CPUINT_LINE(0))
+ /* cobalt_cpu_irq_type */
+ irq_desc[i].handler = &cobalt_cpu_irq_type;
+ else if (irqnr_to_type[i] == VIAINT_LINE)
+ /* VIA/8259 irq_type */
+ irq_desc[i].handler = &cobalt_via_irq_type;
+ else {} /* Leave it as disabled/no handler */
+ }
+
+ /* Setup the VIA interrupts */
+ request_resource(&ioport_resource, &pic1_io_resource);
+ request_resource(&ioport_resource, &pic2_io_resource);
+ setup_irq(2, &via_irq2);
+
+ /* This may be too simple.. FIX it later */
+ VIA_PORT_WRITE(0x20, 0x10);
+ VIA_PORT_WRITE(0x21, 0x00);
+ VIA_PORT_WRITE(0x21, 0x00);
+
+ VIA_PORT_WRITE(0xa0, 0x10);
+ VIA_PORT_WRITE(0xa1, 0x00);
+ VIA_PORT_WRITE(0xa1, 0x00);
+
+ /* Mask all cpu interrupts
+ (except IE4, we already masked those at VIA level) */
+ clear_cp0_status(ST0_IM);
+ set_cp0_status(IE_IRQ4);
+
+ cli();
+
+ set_except_vector(0, cobalt_handle_int);
}
Index: pci.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/pci.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- pci.c 30 Nov 2001 18:34:09 -0000 1.7
+++ pci.c 21 Apr 2002 20:56:23 -0000 1.8
@@ -1,10 +1,15 @@
/*
+ * Cobalt Qube/Raq PCI support
+ *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Cobalt Qube specific PCI support.
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ld...@ag...)
+ *
*/
+
#include <linux/config.h>
#include <linux/types.h>
#include <linux/pci.h>
@@ -17,8 +22,6 @@
#ifdef CONFIG_PCI
-#define SELF 0
-
static void qube_expansion_slot_bist(void)
{
unsigned char ctrl;
@@ -42,7 +45,7 @@
static void qube_expansion_slot_fixup(void)
{
unsigned short pci_cmd;
- unsigned long ioaddr_base = 0x10108000; /* It's magic, ask Doug. */
+ unsigned long ioaddr_base = 0x108000; /* It's magic, ask Doug. */
unsigned long memaddr_base = 0x12000000;
int i;
@@ -82,94 +85,62 @@
alignme = 0x400;
rval = ((*basep + (alignme - 1)) & ~(alignme - 1));
*basep = (rval + size);
- pcibios_write_config_dword(0,(0x0a<<3), regaddr, rval | aspace);
+ pcibios_write_config_dword(0, (0x0a<<3), regaddr, rval | aspace);
}
qube_expansion_slot_bist();
}
-#define DEFAULT_BMIBA 0xcc00 /* in case ROM did not init it */
-
static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
{
unsigned short cfgword;
unsigned char lt;
- unsigned int bmiba;
- int try_again = 1;
/* Enable Bus Mastering and fast back to back. */
pci_read_config_word(dev, PCI_COMMAND, &cfgword);
cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
pci_write_config_word(dev, PCI_COMMAND, cfgword);
- /* Enable interfaces. ROM only enables primary one. */
- {
-#ifdef CONFIG_BLK_DEV_COBALT_SECONDARY
- unsigned char iface_enable = 0xb;
-#else
- unsigned char iface_enable = 0xa;
-#endif
- pci_write_config_byte(dev, 0x40, iface_enable);
- }
+ /* Enable both ide interfaces. ROM only enables primary one. */
+ pci_write_config_byte(dev, 0x40, 0xb);
/* Set latency timer to reasonable value. */
pci_read_config_byte(dev, PCI_LATENCY_TIMER, <);
- if (lt < 64)
+ if(lt < 64)
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
-
- /* Get the bmiba base address. */
- do {
- pci_read_config_dword(dev, 0x20, &bmiba);
- bmiba &= 0xfff0; /* extract port base address */
- if (bmiba) {
- break;
- } else {
- printk("ide: BM-DMA base register is invalid (0x%08x)\n",bmiba);
- if (inb(DEFAULT_BMIBA) != 0xff || !try_again)
- break;
- printk("ide: setting BM-DMA base register to 0x%08x\n",DEFAULT_BMIBA);
- pci_write_config_dword(dev, 0x20, DEFAULT_BMIBA|1);
- }
- } while (try_again--);
-
- bmiba += 0x10000000;
-
- dev->resource[4].start = bmiba;
}
static void qube_raq_tulip_fixup(struct pci_dev *dev)
{
unsigned short pci_cmd;
extern int cobalt_is_raq;
- unsigned int tmp;
/* Fixup the first tulip located at device PCICONF_ETH0 */
- if (dev->devfn == PCI_DEVSHFT(COBALT_PCICONF_ETH0)) {
+ if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_ETH0) {
/*
* Now tell the Ethernet device that we expect an interrupt at
* IRQ 13 and not the default 189.
*
* The IRQ of the first Tulip is different on Qube and RaQ
- * hardware except for the weird first RaQ bringup board,
*/
- if (! cobalt_is_raq) {
+ if (!cobalt_is_raq) {
/* All Qube's route this the same way. */
pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
- COBALT_ETHERNET_IRQ);
+ COBALT_QUBE_ETH_IRQ);
} else {
/* Setup the first Tulip on the RAQ */
-#ifndef RAQ_BOARD_1_WITH_HWHACKS
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 4);
-#else
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 13);
-#endif
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+ COBALT_RAQ_ETH0_IRQ);
+ }
+ dev->resource[0].start = 0x100000;
+ dev->resource[0].end = 0x10007f;
+ if (dev->resource[1].start < 0x10000000) {
+ dev->resource[1].start = 0xe9ffec00;
+ dev->resource[1].end = 0xe9ffefff;
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0xe9ffec00);
}
/* Fixup the second tulip located at device PCICONF_ETH1 */
- } else if (dev->devfn == PCI_DEVSHFT(COBALT_PCICONF_ETH1)) {
- /* XXX Check for the second Tulip on the RAQ(Already got it!) */
- pci_read_config_dword(dev, PCI_VENDOR_ID, &tmp);
- if(tmp == 0xffffffff || tmp == 0x00000000)
- return;
+ } else if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_ETH1) {
/* Enable the second Tulip device. */
pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
@@ -177,19 +148,14 @@
pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
/* Give it it's IRQ. */
- /* NOTE: RaQ board #1 has a bunch of green wires which swapped
- * the IRQ line values of Tulip 0 and Tulip 1. All other
- * boards have eth0=4,eth1=13. -DaveM
- */
-#ifndef RAQ_BOARD_1_WITH_HWHACKS
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 13);
-#else
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 4);
-#endif
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+ COBALT_RAQ_ETH1_IRQ);
+
/* And finally, a usable I/O space allocation, right after what
* the first Tulip uses.
*/
- pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x10101001);
+ dev->resource[0].start = 0x101000;
+ dev->resource[0].end = 0x10107f;
}
}
@@ -197,7 +163,6 @@
{
unsigned short pci_cmd;
extern int cobalt_is_raq;
- unsigned int tmp;
/*
* Tell the SCSI device that we expect an interrupt at
@@ -206,18 +171,15 @@
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_SCSI_IRQ);
if (cobalt_is_raq) {
- /* Check for the SCSI on the RAQ */
- pci_read_config_dword(dev, PCI_VENDOR_ID, &tmp);
- if(tmp == 0xffffffff || tmp == 0x00000000)
- return;
/* Enable the device. */
pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
- pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE);
+ pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
+ | PCI_COMMAND_INVALIDATE);
pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
- /* Give it it's IRQ. */
+ /* Give it it's RAQ IRQ. */
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 4);
/* And finally, a usable I/O space allocation, right after what
@@ -252,7 +214,7 @@
/* New Galileo, assumes PCI stop line to VIA is connected. */
*((volatile unsigned int *)0xb4000c04) = 0x00004020;
} else if (galileo_id == 0x1 || galileo_id == 0x2) {
- unsigned int timeo;
+ signed int timeo;
/* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
timeo = *((volatile unsigned int *)0xb4000c04);
/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
@@ -263,11 +225,8 @@
static void
qube_pcibios_fixup(struct pci_dev *dev)
{
- extern int cobalt_is_raq;
unsigned int tmp;
-
- if (! cobalt_is_raq) {
/* See if there is a device in the expansion slot, if so
* fixup IRQ, fix base addresses, and enable master +
* I/O + memory accesses in config space.
@@ -275,27 +234,17 @@
pcibios_read_config_dword(0, 0x0a<<3, PCI_VENDOR_ID, &tmp);
if(tmp != 0xffffffff && tmp != 0x00000000)
qube_expansion_slot_fixup();
- } else {
- /* And if we are a 2800 we have to setup the expansion slot
- * too.
- */
- pcibios_read_config_dword(0, 0x0a<<3, PCI_VENDOR_ID, &tmp);
- if(tmp != 0xffffffff && tmp != 0x00000000)
- qube_expansion_slot_fixup();
- }
}
struct pci_fixup pcibios_fixups[] = {
- /* TBD:: Add each device here and divvy up pcibios_fixup */
{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, qube_raq_via_bmIDE_fixup },
{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, qube_raq_tulip_fixup },
{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_GALILEO, PCI_ANY_ID, qube_raq_galileo_fixup },
- /* Not sure about what scsi chips are available on the RAQ, put an
- entry for all */
{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, qube_raq_scsi_fixup },
{ PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, qube_pcibios_fixup }
};
+
static __inline__ int pci_range_ck(struct pci_dev *dev)
{
if ((dev->bus->number == 0)
@@ -303,6 +252,7 @@
|| ((PCI_SLOT (dev->devfn) > 6)
&& (PCI_SLOT (dev->devfn) <= 12))))
return 0; /* OK device number */
+
return -1; /* NOT ok device number */
}
@@ -313,7 +263,9 @@
((*PCI_CFG_CTRL) = (0x80000000 | (PCI_SLOT ((dev)->devfn) << 11) | \
(PCI_FUNC ((dev)->devfn) << 8) | (where)))
-static int qube_pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
+static int qube_pci_read_config_dword (struct pci_dev *dev,
+ int where,
+ u32 *val)
{
if (where & 0x3)
return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -326,7 +278,9 @@
return PCIBIOS_SUCCESSFUL;
}
-static int qube_pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
+static int qube_pci_read_config_word (struct pci_dev *dev,
+ int where,
+ u16 *val)
{
if (where & 0x1)
return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -339,7 +293,9 @@
return PCIBIOS_SUCCESSFUL;
}
-static int qube_pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
+static int qube_pci_read_config_byte (struct pci_dev *dev,
+ int where,
+ u8 *val)
{
if (pci_range_ck (dev)) {
*val = 0xff;
@@ -350,9 +306,11 @@
return PCIBIOS_SUCCESSFUL;
}
-static int qube_pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
+static int qube_pci_write_config_dword (struct pci_dev *dev,
+ int where,
+ u32 val)
{
- if (where & 0x3)
+ if(where & 0x3)
return PCIBIOS_BAD_REGISTER_NUMBER;
if (pci_range_ck (dev))
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -361,7 +319,10 @@
return PCIBIOS_SUCCESSFUL;
}
-static int qube_pci_write_config_word(struct pci_dev *dev, int where, u16 val)
+static int
+qube_pci_write_config_word (struct pci_dev *dev,
+ int where,
+ u16 val)
{
unsigned long tmp;
@@ -377,7 +338,10 @@
return PCIBIOS_SUCCESSFUL;
}
-static int qube_pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
+static int
+qube_pci_write_config_byte (struct pci_dev *dev,
+ int where,
+ u8 val)
{
unsigned long tmp;
@@ -391,6 +355,7 @@
return PCIBIOS_SUCCESSFUL;
}
+
struct pci_ops qube_pci_ops = {
qube_pci_read_config_byte,
qube_pci_read_config_word,
@@ -405,7 +370,10 @@
printk("PCI: Probing PCI hardware\n");
ioport_resource.start = 0x00000000;
- ioport_resource.end = 0x1cffffff;
+ ioport_resource.end = 0x0fffffff;
+
+ iomem_resource.start = 0x01000000;
+ iomem_resource.end = 0xffffffff;
pci_scan_bus(0, &qube_pci_ops, NULL);
}
@@ -423,28 +391,32 @@
pci_read_config_word(dev, PCI_STATUS, &status);
printk("PCI: Enabling device %s (%04x %04x)\n", dev->slot_name, cmd, status);
/* We'll sort this out when we know it isn't enabled ;) */
- return 0; /* pcibios_enable_resources */
+
+ return 0;
}
-void pcibios_align_resource(void *data, struct resource *res,unsigned long size)
+void pcibios_align_resource(void *data, struct resource *res,
+ unsigned long size)
{
- panic("Uhhoh called pcibios_align_resource");
+ panic("Uhhoh called pcibios_align_resource\n");
}
void pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
- panic("Uhhoh called pcibios_update_resource");
+
+ panic("Uhhoh called pcibios_update_resource\n");
}
void __init pcibios_fixup_bus(struct pci_bus *bus)
{
- /* We don't appear to have sub-busses to fixup here */
+ /* We don't have sub-busses to fixup here */
}
-unsigned __init int pcibios_assign_all_busses(void)
+unsigned int __init pcibios_assign_all_busses(void)
{
return 1;
}
+
#endif /* CONFIG_PCI */
Index: promcon.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/promcon.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- promcon.c 2 Jul 2001 18:03:24 -0000 1.1
+++ promcon.c 21 Apr 2002 20:56:23 -0000 1.2
@@ -1,3 +1,15 @@
+/*
+ * PROM console for Cobalt Raq2
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ld...@ag...)
+ *
+ */
+
#include <linux/init.h>
#include <linux/console.h>
#include <linux/kdev_t.h>
@@ -8,21 +20,20 @@
#include <asm/serial.h>
#include <asm/io.h>
-static unsigned long port = 0x1c800000;
+static unsigned long port = 0xc800000;
static __inline__ void ns16550_cons_put_char(char ch, unsigned long ioaddr)
{
char lsr;
- do { lsr = inb(ioaddr + UART_LSR);
+ do {
+ lsr = inb(ioaddr + UART_LSR);
} while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
outb(ch, ioaddr + UART_TX);
}
static __inline__ char ns16550_cons_get_char(unsigned long ioaddr)
{
- char lsr;
-
while ((inb(ioaddr + UART_LSR) & UART_LSR_DR) == 0)
udelay(1);
return inb(ioaddr + UART_RX);
@@ -36,13 +47,16 @@
ier = inb(port + UART_IER);
outb(0x00, port + UART_IER);
for (i=0; i < count; i++, s++) {
+
if(*s == '\n')
ns16550_cons_put_char('\r', port);
ns16550_cons_put_char(*s, port);
}
- do { lsr = inb(port + UART_LSR);
+ do {
+ lsr = inb(port + UART_LSR);
} while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
+
outb(ier, port + UART_IER);
}
@@ -56,7 +70,8 @@
ns16550_cons_put_char(kgdb_char, port);
}
-static kdev_t ns16550_console_dev(struct console *c)
+static kdev_t
+ns16550_console_dev(struct console *c)
{
return MKDEV(TTY_MAJOR, 64 + c->index);
}
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/setup.c,v
retrieving revision 1.19
retrieving revision 1.20
diff -u -d -r1.19 -r1.20
--- setup.c 2 Jan 2002 19:12:16 -0000 1.19
+++ setup.c 21 Apr 2002 20:56:23 -0000 1.20
@@ -1,18 +1,19 @@
/*
- * Setup pointers to hardware dependand routines.
+ * Setup pointers to hardware dependent routines.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ld...@ag...)
+ *
*/
+
#include <linux/config.h>
-#include <linux/ioport.h>
-#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
-#include <linux/timex.h>
+#include <linux/mc146818rtc.h>
#include <linux/init.h>
#include <linux/ide.h>
@@ -23,23 +24,25 @@
#include <asm/cobalt/cobalt.h>
#include <asm/pci.h>
#include <asm/processor.h>
-#include <asm/ptrace.h>
#include <asm/reboot.h>
extern void cobalt_machine_restart(char *command);
extern void cobalt_machine_halt(void);
extern void cobalt_machine_power_off(void);
-
extern void rtc_dallas_init(unsigned long base);
+extern struct ide_ops std_ide_ops;
-extern struct ide_ops cobalt_ide_ops;
-
-char arcs_cmdline[CL_SIZE] = { "console=ttyS0,115200 root=/dev/hda1"};
+char arcs_cmdline[CL_SIZE] = { "console=ttyS0,115200 root=/dev/hda1" };
void __init bus_error_init(void)
{
}
+const char *get_system_type(void)
+{
+ return "MIPS Cobalt";
+}
+
#define GALILEO_T0_VAL 0xb4000850
#define GALILEO_TIMER_CTRL 0xb4000864
#define GALILEO_CPU_MASK 0xb4000c1c
@@ -47,23 +50,16 @@
#define GALILEO_ENTC0 0x01
#define GALILEO_SELTC0 0x02
-static void __init cobalt_calibrate_timer(void)
+static void __init cobalt_timer_setup(struct irqaction *irq)
{
+ /* Load timer value for 150 Hz */
volatile unsigned long *timer_reg = (volatile unsigned long *)GALILEO_T0_VAL;
- /* Default to 150MHZ, since this is what we are shipping. */
*timer_reg = 500000;
-}
-
-static void __init cobalt_timer_setup(struct irqaction *irq)
-{
- /* Load timer value for 150 Hz */
- cobalt_calibrate_timer();
+ /* Register our timer interrupt */
setup_irq(0, irq);
- change_cp0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1 | IE_IRQ0);
-
/* Enable timer ints */
*((volatile unsigned long *) GALILEO_TIMER_CTRL) =
(unsigned long) (GALILEO_ENTC0 | GALILEO_SELTC0);
@@ -73,8 +69,6 @@
static void __init cobalt_time_init(void)
{
- //mips_counter_frequency = 83000000;
-
/* we have ds1396 RTC chip */
rtc_dallas_init(VIA_CMOS_ADDR);
@@ -94,8 +88,6 @@
/*
* IO/MEM resources.
*/
- set_io_port_base(COBALT_LOCAL_IO_SPACE);
- isa_slot_offset = 0xb0000000;
#ifdef CONFIG_NEW_PCI
ioport_resource.start = 0x10000000;
@@ -114,8 +106,16 @@
board_timer_setup = cobalt_timer_setup;
#ifdef CONFIG_BLK_DEV_IDE
- ide_ops = &cobalt_ide_ops;
+ ide_ops = &std_ide_ops;
#endif
+ set_io_port_base(0xb0000000);
+
+ /*
+ * This is a prom style console. We just poke at the
+ * UART to make it talk.
+ * Only use this console if you really screw up and can't
+ * get to the stage of setting up a real serial console.
+ */
/*ns16550_setup_console();*/
/* We have to do this early, here, before the value could
@@ -127,14 +127,9 @@
&& cobalt_serial_type == 0x1);
}
-const char *get_system_type(void)
-{
- return "Cobalt"; /* But which exactly? */
-}
-
-/* prom_init() is called just after the cpu type is determined, from
- init_arch(). */
-void __init prom_init(int argc, char **arg)
+/* Prom init. We read our one and only communication with the
+ firmware. Grab the amount of installed memory */
+void __init prom_init(int argc)
{
mips_machgroup = MACH_GROUP_COBALT;
@@ -143,5 +138,5 @@
void __init prom_free_prom_memory(void)
{
- /* Something to do here?? */
+ /* Nothing to do! */
}
|
