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[Linux-mips-commits]CVS: linux/arch/mips/kernel head.S,1.15,1.16 setup.c,1.55,1.56 signal.c,1.6,1.7 smp.c,1.15,1.16 syscall.c,1.3,1.4 time.c,1.12,1.13 traps.c,1.31,1.32
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From: Paul M. <le...@us...> - 2002-04-21 19:30:12
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Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv29521/arch/mips/kernel
Modified Files:
head.S setup.c signal.c smp.c syscall.c time.c traps.c
Log Message:
Further OSS syncing.
Index: head.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/head.S,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- head.S 21 Apr 2002 18:03:11 -0000 1.15
+++ head.S 21 Apr 2002 19:30:07 -0000 1.16
@@ -21,7 +21,7 @@
#include <asm/asm.h>
#include <asm/current.h>
#include <asm/offset.h>
-#include <asm/pgtable.h>
+#include <asm/pgtable-bits.h>
#include <asm/processor.h>
#include <asm/regdef.h>
#include <asm/cachectl.h>
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.55
retrieving revision 1.56
diff -u -d -r1.55 -r1.56
--- setup.c 11 Apr 2002 01:46:46 -0000 1.55
+++ setup.c 21 Apr 2002 19:30:07 -0000 1.56
@@ -39,9 +39,6 @@
#include <asm/io.h>
#include <asm/stackframe.h>
#include <asm/system.h>
-#ifdef CONFIG_SGI_IP22
-#include <asm/sgialib.h>
-#endif
#ifndef CONFIG_SMP
struct cpuinfo_mips cpu_data[1];
@@ -267,7 +264,7 @@
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
MIPS_CPU_32FPR | MIPS_CPU_WATCH |
- MIPS_CPU_VCE;
+ MIPS_CPU_VCE | MIPS_CPU_FPUEX;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_VR41XX:
@@ -283,13 +280,15 @@
case PRID_IMP_R4300:
mips_cpu.cputype = CPU_R4300;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR | MIPS_CPU_FPUEX;
mips_cpu.tlbsize = 32;
break;
case PRID_IMP_R4600:
mips_cpu.cputype = CPU_R4600;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_FPUEX;
mips_cpu.tlbsize = 48;
break;
#if 0
@@ -302,7 +301,8 @@
*/
mips_cpu.cputype = CPU_R4650;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_FPUEX;
mips_cpu.tlbsize = 48;
break;
#endif
@@ -336,14 +336,14 @@
mips_cpu.cputype = CPU_R4700;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR;
+ MIPS_CPU_32FPR | MIPS_CPU_FPUEX;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_TX49:
mips_cpu.cputype = CPU_TX49XX;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR;
+ MIPS_CPU_32FPR | MIPS_CPU_FPUEX;
mips_cpu.tlbsize = 48;
mips_cpu.icache.ways = 4;
mips_cpu.dcache.ways = 4;
@@ -352,28 +352,31 @@
mips_cpu.cputype = CPU_R5000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR;
+ MIPS_CPU_32FPR | MIPS_CPU_FPUEX;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_R5432:
mips_cpu.cputype = CPU_R5432;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_WATCH;
+ MIPS_CPU_32FPR | MIPS_CPU_WATCH |
+ MIPS_CPU_FPUEX;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_R5500:
mips_cpu.cputype = CPU_R5500;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_WATCH;
+ MIPS_CPU_32FPR | MIPS_CPU_WATCH |
+ MIPS_CPU_FPUEX;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_NEVADA:
mips_cpu.cputype = CPU_NEVADA;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_DIVEC;
+ MIPS_CPU_32FPR | MIPS_CPU_DIVEC |
+ MIPS_CPU_FPUEX;
mips_cpu.tlbsize = 48;
mips_cpu.icache.ways = 2;
mips_cpu.dcache.ways = 2;
@@ -382,7 +385,8 @@
mips_cpu.cputype = CPU_R5900;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU |
- MIPS_CPU_COUNTER | MIPS_CPU_DIVEC;
+ MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
+ MIPS_CPU_FPUEX;
mips_cpu.tlbsize = 48;
mips_cpu.icache.ways = 2;
mips_cpu.dcache.ways = 2;
@@ -392,20 +396,22 @@
case PRID_IMP_R6000:
mips_cpu.cputype = CPU_R6000;
mips_cpu.isa_level = MIPS_CPU_ISA_II;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU |
+ MIPS_CPU_FPUEX;
mips_cpu.tlbsize = 32;
break;
case PRID_IMP_R6000A:
mips_cpu.cputype = CPU_R6000A;
mips_cpu.isa_level = MIPS_CPU_ISA_II;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU |
+ MIPS_CPU_FPUEX;
mips_cpu.tlbsize = 32;
break;
case PRID_IMP_RM7000:
mips_cpu.cputype = CPU_RM7000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR;
+ MIPS_CPU_32FPR | MIPS_CPU_FPUEX;
/*
* Undocumented RM7000: Bit 29 in the info register of
* the RM7000 v2.0 indicates if the TLB has 48 or 64
@@ -420,7 +426,8 @@
mips_cpu.cputype = CPU_R8000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_FPU | MIPS_CPU_32FPR;
+ MIPS_CPU_FPU | MIPS_CPU_32FPR |
+ MIPS_CPU_FPUEX;
mips_cpu.tlbsize = 384; /* has wierd TLB: 3-way x 128 */
break;
case PRID_IMP_R10000:
@@ -428,7 +435,8 @@
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
MIPS_CPU_FPU | MIPS_CPU_32FPR |
- MIPS_CPU_COUNTER | MIPS_CPU_WATCH;
+ MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
+ MIPS_CPU_FPUEX;
mips_cpu.tlbsize = 64;
break;
case PRID_IMP_RC32334:
@@ -474,7 +482,8 @@
if (config1 & (1 << 2))
mips_cpu.options |= MIPS_CPU_MIPS16;
if (config1 & 1)
- mips_cpu.options |= MIPS_CPU_FPU;
+ mips_cpu.options |= MIPS_CPU_FPU |
+ MIPS_CPU_FPUEX;
mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
break;
case PRID_IMP_5KC:
@@ -491,7 +500,8 @@
if (config1 & (1 << 2))
mips_cpu.options |= MIPS_CPU_MIPS16;
if (config1 & 1)
- mips_cpu.options |= MIPS_CPU_FPU;
+ mips_cpu.options |= MIPS_CPU_FPU |
+ MIPS_CPU_FPUEX;
mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
break;
default:
@@ -527,7 +537,8 @@
if (config1 & (1 << 2))
mips_cpu.options |= MIPS_CPU_MIPS16;
if (config1 & 1)
- mips_cpu.options |= MIPS_CPU_FPU;
+ mips_cpu.options |= MIPS_CPU_FPU |
+ MIPS_CPU_FPUEX;
mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
break;
default:
@@ -546,7 +557,8 @@
MIPS_CPU_MCHECK;
#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
/* FPU in pass1 is known to have issues. */
- mips_cpu.options |= MIPS_CPU_FPU;
+ mips_cpu.options |= MIPS_CPU_FPU |
+ MIPS_CPU_FPUEX;
#endif
break;
default:
@@ -562,8 +574,8 @@
mips_cpu.isa_level = MIPS_CPU_ISA_M64;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
MIPS_CPU_4KTLB | MIPS_CPU_FPU |
- MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
- MIPS_CPU_MCHECK;
+ MIPS_CPU_FPUEX | MIPS_CPU_COUNTER |
+ MIPS_CPU_DIVEC | MIPS_CPU_MCHECK;
mips_cpu.scache.ways = 8;
break;
}
@@ -636,8 +648,8 @@
for (i = 0; i < boot_mem_map.nr_map; i++) {
printk(" memory: %08Lx @ %08Lx ",
- (unsigned long long) boot_mem_map.map[i].size,
- (unsigned long long) boot_mem_map.map[i].addr);
+ (u64) boot_mem_map.map[i].size,
+ (u64) boot_mem_map.map[i].addr);
switch (boot_mem_map.map[i].type) {
case BOOT_MEM_RAM:
printk("(usable)\n");
@@ -710,8 +722,8 @@
{
void atlas_setup(void);
void baget_setup(void);
- void ddb_setup(void);
void cobalt_setup(void);
+ void ddb_setup(void);
void decstation_setup(void);
void deskstation_setup(void);
void jazz_setup(void);
@@ -738,6 +750,7 @@
unsigned long tmp;
unsigned long* initrd_header;
#endif
+
int i;
#ifdef CONFIG_BLK_DEV_FD
Index: signal.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/signal.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- signal.c 18 Mar 2002 22:34:34 -0000 1.6
+++ signal.c 21 Apr 2002 19:30:07 -0000 1.7
@@ -17,14 +17,14 @@
#include <linux/signal.h>
#include <linux/errno.h>
#include <linux/wait.h>
-#include <linux/ptrace.h>
#include <linux/unistd.h>
#include <asm/asm.h>
#include <asm/bitops.h>
#include <asm/cpu.h>
+#include <asm/offset.h>
#include <asm/pgalloc.h>
-#include <asm/stackframe.h>
+#include <asm/ptrace.h>
#include <asm/uaccess.h>
#include <asm/ucontext.h>
@@ -384,14 +384,15 @@
int err = 0;
u64 reg;
- err |= __put_user(regs->cp0_epc, &sc->sc_pc);
+ reg = regs->cp0_epc; err |= __put_user(reg, &sc->sc_pc);
err |= __put_user(regs->cp0_status, &sc->sc_status);
#define save_gp_reg(i) { \
reg = regs->regs[i]; \
err |= __put_user(reg, &sc->sc_regs[i]); \
} while(0)
- __put_user(0, &sc->sc_regs[0]); save_gp_reg(1); save_gp_reg(2);
+ reg = 0; err |= __put_user(reg, &sc->sc_regs[0]);
+ save_gp_reg(1); save_gp_reg(2);
save_gp_reg(3); save_gp_reg(4); save_gp_reg(5); save_gp_reg(6);
save_gp_reg(7); save_gp_reg(8); save_gp_reg(9); save_gp_reg(10);
save_gp_reg(11); save_gp_reg(12); save_gp_reg(13); save_gp_reg(14);
@@ -402,8 +403,8 @@
save_gp_reg(31);
#undef save_gp_reg
- err |= __put_user(regs->hi, &sc->sc_mdhi);
- err |= __put_user(regs->lo, &sc->sc_mdlo);
+ reg = regs->hi; err |= __put_user(reg, &sc->sc_mdhi);
+ reg = regs->lo; err |= __put_user(reg, &sc->sc_mdlo);
err |= __put_user(regs->cp0_cause, &sc->sc_cause);
err |= __put_user(regs->cp0_badvaddr, &sc->sc_badvaddr);
Index: smp.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/smp.c,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- smp.c 26 Feb 2002 17:34:14 -0000 1.15
+++ smp.c 21 Apr 2002 19:30:07 -0000 1.16
@@ -308,6 +308,7 @@
local_flush_tlb_page(vma, page);
}
+EXPORT_SYMBOL(smp_num_cpus);
EXPORT_SYMBOL(flush_tlb_page);
EXPORT_SYMBOL(cpu_data);
EXPORT_SYMBOL(synchronize_irq);
Index: syscall.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/syscall.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- syscall.c 17 Sep 2001 16:47:38 -0000 1.3
+++ syscall.c 21 Apr 2002 19:30:07 -0000 1.4
@@ -28,7 +28,6 @@
#include <asm/offset.h>
#include <asm/ptrace.h>
#include <asm/signal.h>
-#include <asm/stackframe.h>
#include <asm/uaccess.h>
extern asmlinkage void syscall_trace(void);
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/time.c,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- time.c 5 Feb 2002 17:36:46 -0000 1.12
+++ time.c 21 Apr 2002 19:30:07 -0000 1.13
@@ -39,6 +39,11 @@
extern volatile unsigned long wall_jiffies;
/*
+ * whether we emulate local_timer_interrupts for SMP machines.
+ */
+int emulate_local_timer_interrupt;
+
+/*
* By default we provide the null RTC ops
*/
static unsigned long null_rtc_get_time(void)
@@ -283,6 +288,42 @@
/*
+ * local_timer_interrupt() does profiling and process accounting
+ * on a per-CPU basis.
+ *
+ * In UP mode, it is invoked from the (global) timer_interrupt.
+ *
+ * In SMP mode, it might invoked by per-CPU timer interrupt, or
+ * a broadcasted inter-processor interrupt which itself is triggered
+ * by the global timer interrupt.
+ */
+void local_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+ if (!user_mode(regs)) {
+ if (prof_buffer && current->pid) {
+ extern int _stext;
+ unsigned long pc = regs->cp0_epc;
+
+ pc -= (unsigned long) &_stext;
+ pc >>= prof_shift;
+ /*
+ * Dont ignore out-of-bounds pc values silently,
+ * put them into the last histogram slot, so if
+ * present, they will show up as a sharp peak.
+ */
+ if (pc > prof_len-1)
+ pc = prof_len-1;
+ atomic_inc((atomic_t *)&prof_buffer[pc]);
+ }
+ }
+
+#ifdef CONFIG_SMP
+ /* in UP mode, update_process_times() is invoked by do_timer() */
+ update_process_times(user_mode(regs));
+#endif
+}
+
+/*
* high-level timer interrupt service routines. This function
* is set as irqaction->handler and is invoked through do_IRQ.
*/
@@ -309,24 +350,6 @@
}
- if(!user_mode(regs)) {
- if (prof_buffer && current->pid) {
- extern int _stext;
- unsigned long pc = regs->cp0_epc;
-
- pc -= (unsigned long) &_stext;
- pc >>= prof_shift;
- /*
- * Dont ignore out-of-bounds pc values silently,
- * put them into the last histogram slot, so if
- * present, they will show up as a sharp peak.
- */
- if (pc > prof_len-1)
- pc = prof_len-1;
- atomic_inc((atomic_t *)&prof_buffer[pc]);
- }
- }
-
/*
* call the generic timer interrupt handling
*/
@@ -359,6 +382,31 @@
if (!jiffies) {
timerhi = timerlo = 0;
}
+
+#if !defined(CONFIG_SMP)
+ /*
+ * In UP mode, we call local_timer_interrupt() to do profiling
+ * and process accouting.
+ *
+ * In SMP mode, local_timer_interrupt() is invoked by appropriate
+ * low-level local timer interrupt handler.
+ */
+ local_timer_interrupt(0, NULL, regs);
+
+#else /* CONFIG_SMP */
+
+ if (emulate_local_timer_interrupt) {
+ /*
+ * this is the place where we send out inter-process
+ * interrupts and let each CPU do its own profiling
+ * and process accouting.
+ *
+ * Obviously we need to call local_timer_interrupt() for
+ * the current CPU too.
+ */
+ panic("Not implemented yet!!!");
+ }
+#endif /* CONFIG_SMP */
}
asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs)
@@ -377,6 +425,21 @@
do_softirq();
}
+asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs)
+{
+ int cpu = smp_processor_id();
+
+ irq_enter(cpu, irq);
+ kstat.irqs[cpu][irq]++;
+
+ /* we keep interrupt disabled all the time */
+ local_timer_interrupt(irq, NULL, regs);
+
+ irq_exit(cpu, irq);
+
+ if (softirq_pending(cpu))
+ do_softirq();
+}
/*
* time_init() - it does the following things.
Index: traps.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/traps.c,v
retrieving revision 1.31
retrieving revision 1.32
diff -u -d -r1.31 -r1.32
--- traps.c 26 Feb 2002 17:34:14 -0000 1.31
+++ traps.c 21 Apr 2002 19:30:07 -0000 1.32
@@ -852,6 +852,8 @@
extern char except_vec_ejtag_debug;
unsigned long i;
+ per_cpu_trap_init();
+
/* Copy the generic exception handler code to it's final destination. */
memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
@@ -914,7 +916,7 @@
set_except_vector(12, handle_ov);
set_except_vector(13, handle_tr);
- if (mips_cpu.options & MIPS_CPU_FPU)
+ if (mips_cpu.options & MIPS_CPU_FPUEX)
set_except_vector(15, handle_fpe);
if (mips_cpu.options & MIPS_CPU_MCHECK)
set_except_vector(24, handle_mcheck);
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