[Linux-mips-commits]CVS: linux/arch/mips/au1000/pb1000 setup.c,1.18,1.19

[Pete P. <pp...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000
In directory usw-pr-cvs1:/tmp/cvs-serv29952/arch/mips/au1000/pb1000

Modified Files:
	setup.c 
Log Message:
Replaced inl/outl macros with the readl/writel equivalents.


Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000/setup.c,v
retrieving revision 1.18
retrieving revision 1.19
diff -u -d -r1.18 -r1.19
--- setup.c	15 Feb 2002 19:47:25 -0000	1.18
+++ setup.c	17 Apr 2002 23:56:39 -0000	1.19
@@ -121,8 +121,8 @@
 #endif
 
 	// set AUX clock to 12MHz * 8 = 96 MHz
-	outl(8, SYS_AUXPLL);
-	outl(0, SYS_PINSTATERD);
+	writel(8, SYS_AUXPLL);
+	writel(0, SYS_PINSTATERD);
 	udelay(100);
 
 #if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
@@ -138,19 +138,19 @@
 #endif
 
 	/* zero and disable FREQ2 */
-	sys_freqctrl = inl(SYS_FREQCTRL0);
+	sys_freqctrl = readl(SYS_FREQCTRL0);
 	sys_freqctrl &= ~0xFFF00000;
-	outl(sys_freqctrl, SYS_FREQCTRL0);
+	writel(sys_freqctrl, SYS_FREQCTRL0);
 
 	/* zero and disable USBH/USBD clocks */
-	sys_clksrc = inl(SYS_CLKSRC);
+	sys_clksrc = readl(SYS_CLKSRC);
 	sys_clksrc &= ~0x00007FE0;
-	outl(sys_clksrc, SYS_CLKSRC);
+	writel(sys_clksrc, SYS_CLKSRC);
 
-	sys_freqctrl = inl(SYS_FREQCTRL0);
+	sys_freqctrl = readl(SYS_FREQCTRL0);
 	sys_freqctrl &= ~0xFFF00000;
 
-	sys_clksrc = inl(SYS_CLKSRC);
+	sys_clksrc = readl(SYS_CLKSRC);
 	sys_clksrc &= ~0x00007FE0;
 
 	switch (prid & 0x000000FF)
@@ -159,17 +159,17 @@
 	case 0x01: /* HA */
 	case 0x02: /* HB */
 	/* CPU core freq to 48MHz to slow it way down... */
-	outl(4, SYS_CPUPLL);
+	writel(4, SYS_CPUPLL);
 
 	/*
 	 * Setup 48MHz FREQ2 from CPUPLL for USB Host
 	 */
 	/* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
 	sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
-	outl(sys_freqctrl, SYS_FREQCTRL0);
+	writel(sys_freqctrl, SYS_FREQCTRL0);
 
 	/* CPU core freq to 384MHz */
-	outl(0x20, SYS_CPUPLL);
+	writel(0x20, SYS_CPUPLL);
 
 	printk("Au1000: 48MHz OHCI workaround enabled\n");
 		break;
@@ -177,7 +177,7 @@
 	default:  /* HC and newer */
 	// FREQ2 = aux/2 = 48 MHz
 	sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
-	outl(sys_freqctrl, SYS_FREQCTRL0);
+	writel(sys_freqctrl, SYS_FREQCTRL0);
 		break;
 	}
 
@@ -190,64 +190,64 @@
 #ifdef CONFIG_AU1000_USB_DEVICE
 	sys_clksrc |= ((4<<7) | (0<<6) | (0<<5));
 #endif
-	outl(sys_clksrc, SYS_CLKSRC);
+	writel(sys_clksrc, SYS_CLKSRC);
 
 #ifdef CONFIG_USB_OHCI
 	// enable host controller and wait for reset done
-	outl(0x08, USB_HOST_CONFIG);
+	writel(0x08, USB_HOST_CONFIG);
 	udelay(1000);
-	outl(0x0E, USB_HOST_CONFIG);
+	writel(0x0E, USB_HOST_CONFIG);
 	udelay(1000);
-	inl(USB_HOST_CONFIG); // throw away first read
-	while (!(inl(USB_HOST_CONFIG) & 0x10))
-		inl(USB_HOST_CONFIG);
+	readl(USB_HOST_CONFIG); // throw away first read
+	while (!(readl(USB_HOST_CONFIG) & 0x10))
+		readl(USB_HOST_CONFIG);
 #endif
 	
 	// configure pins GPIO[14:9] as GPIO
-	pin_func = inl(SYS_PINFUNC) & (u32)(~0x8080);
+	pin_func = readl(SYS_PINFUNC) & (u32)(~0x8080);
 
 #ifndef CONFIG_AU1000_USB_DEVICE
 	// 2nd USB port is USB host
 	pin_func |= 0x8000;
 #endif
-	outl(pin_func, SYS_PINFUNC);
-	outl(0x2800, SYS_TRIOUTCLR);
-	outl(0x0030, SYS_OUTPUTCLR);
+	writel(pin_func, SYS_PINFUNC);
+	writel(0x2800, SYS_TRIOUTCLR);
+	writel(0x0030, SYS_OUTPUTCLR);
 #endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
 
 	// make gpio 15 an input (for interrupt line) 
-	pin_func = inl(SYS_PINFUNC) & (u32)(~0x100);
+	pin_func = readl(SYS_PINFUNC) & (u32)(~0x100);
 	// we don't need I2S, so make it available for GPIO[31:29] 
 	pin_func |= (1<<5);
-	outl(pin_func, SYS_PINFUNC);
+	writel(pin_func, SYS_PINFUNC);
 
-	outl(0x8000, SYS_TRIOUTCLR);
+	writel(0x8000, SYS_TRIOUTCLR);
 	
 #ifdef CONFIG_FB
 	conswitchp = &dummy_con;
 #endif
 
-	static_cfg0 = inl(MEM_STCFG0) & (u32)(~0xc00);
-	outl(static_cfg0, MEM_STCFG0);
+	static_cfg0 = readl(MEM_STCFG0) & (u32)(~0xc00);
+	writel(static_cfg0, MEM_STCFG0);
 
 	// configure RCE2* for LCD
-	outl(0x00000004, MEM_STCFG2);
+	writel(0x00000004, MEM_STCFG2);
 
 	// MEM_STTIME2
-	outl(0x09000000, MEM_STTIME2);
+	writel(0x09000000, MEM_STTIME2);
 
 	// Set 32-bit base address decoding for RCE2*
-	outl(0x10003ff0, MEM_STADDR2);
+	writel(0x10003ff0, MEM_STADDR2);
 
 	// PCI CPLD setup
 	// expand CE0 to cover PCI
-	outl(0x11803e40, MEM_STADDR1);
+	writel(0x11803e40, MEM_STADDR1);
 
 	// burst visibility on 
-	outl(inl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
+	writel(readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
 
-	outl(0x83, MEM_STCFG1);         // ewait enabled, flash timing
-	outl(0x33030a10, MEM_STTIME1);   // slower timing for FPGA
+	writel(0x83, MEM_STCFG1);         // ewait enabled, flash timing
+	writel(0x33030a10, MEM_STTIME1);   // slower timing for FPGA
 
 #ifdef CONFIG_FB_E1356
 	if ((argptr = strstr(argptr, "video=")) == NULL) {
@@ -258,19 +258,19 @@
 
 
 #ifdef CONFIG_PCI
-	outl(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
-	outl(0, SDRAM_MBAR);        // set mbar to 0
-	outl(0x2, SDRAM_CMD);       // enable memory accesses
+	writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
+	writel(0, SDRAM_MBAR);        // set mbar to 0
+	writel(0x2, SDRAM_CMD);       // enable memory accesses
 	au_sync_delay(1);
 #endif
 
 #ifndef CONFIG_SERIAL_NONSTANDARD
 	/* don't touch the default serial console */
-	outl(0, UART0_ADDR + UART_CLK);
+	writel(0, UART0_ADDR + UART_CLK);
 #endif
-	outl(0, UART1_ADDR + UART_CLK);
-	outl(0, UART2_ADDR + UART_CLK);
-	outl(0, UART3_ADDR + UART_CLK);
+	writel(0, UART1_ADDR + UART_CLK);
+	writel(0, UART2_ADDR + UART_CLK);
+	writel(0, UART3_ADDR + UART_CLK);
 
 #ifdef CONFIG_BLK_DEV_IDE
 	{
@@ -283,14 +283,14 @@
 	// setup irda clocks
 	// aux clock, divide by 2, clock from 2/4 divider
 	writel(readl(SYS_CLKSRC) | 0x7, SYS_CLKSRC);
-	pin_func = inl(SYS_PINFUNC) & (u32)(~(1<<2)); // clear IRTXD
-	outl(pin_func, SYS_PINFUNC);
+	pin_func = readl(SYS_PINFUNC) & (u32)(~(1<<2)); // clear IRTXD
+	writel(pin_func, SYS_PINFUNC);
 
-	while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
-	outl(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
+	while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
+	writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
 	au_sync();
-	while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
-	outl(0, SYS_TOYTRIM);
+	while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
+	writel(0, SYS_TOYTRIM);
 
 	/* Enable Au1000 BCLK switching - note: sed1356 must not use
 	 * its BCLK (Au1000 LCLK) for any timings */
@@ -301,7 +301,7 @@
 	case 0x02: /* HB */
 		break;
 	default:  /* HC and newer */
-		outl(0x00000060, 0xb190003c);
+		writel(0x00000060, 0xb190003c);
 		break;
 	}
 }