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[Linux-mips-commits]CVS: linux/arch/mips/au1000/common clocks.c,1.3,1.4 dma.c,1.6,1.7 irq.c,1.15,1.16 serial.c,1.7,1.8 time.c,1.10,1.11 usbdev.c,1.8,1.9
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From: Pete P. <pp...@us...> - 2002-03-23 02:13:04
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Update of /cvsroot/linux-mips/linux/arch/mips/au1000/common
In directory usw-pr-cvs1:/tmp/cvs-serv19624/common
Modified Files:
clocks.c dma.c irq.c serial.c time.c usbdev.c
Log Message:
* replace inb/oub macros with the corresponding readb/writeb ones
* changed starting pci io bus address to be 0, instead of 0x50000000
* set mips_io_port_base to be the virtual (ioremapped) address of the
pci io window
Index: clocks.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/clocks.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- clocks.c 15 Feb 2002 19:47:24 -0000 1.3
+++ clocks.c 23 Mar 2002 02:13:01 -0000 1.4
@@ -75,9 +75,9 @@
unsigned int static_cfg0;
unsigned int sys_busclk =
(get_au1000_speed()/1000) /
- ((int)(inl(SYS_POWERCTRL)&0x03) + 2);
+ ((int)(readl(SYS_POWERCTRL)&0x03) + 2);
- static_cfg0 = inl(MEM_STCFG0);
+ static_cfg0 = readl(MEM_STCFG0);
if (static_cfg0 & (1<<11))
lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */
Index: dma.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/dma.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- dma.c 15 Feb 2002 19:47:24 -0000 1.6
+++ dma.c 23 Mar 2002 02:13:01 -0000 1.7
@@ -134,17 +134,17 @@
printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);
printk(KERN_INFO " mode = 0x%08x\n",
- inl(chan->io + DMA_MODE_SET));
+ readl(chan->io + DMA_MODE_SET));
printk(KERN_INFO " addr = 0x%08x\n",
- inl(chan->io + DMA_PERIPHERAL_ADDR));
+ readl(chan->io + DMA_PERIPHERAL_ADDR));
printk(KERN_INFO " start0 = 0x%08x\n",
- inl(chan->io + DMA_BUFFER0_START));
+ readl(chan->io + DMA_BUFFER0_START));
printk(KERN_INFO " start1 = 0x%08x\n",
- inl(chan->io + DMA_BUFFER1_START));
+ readl(chan->io + DMA_BUFFER1_START));
printk(KERN_INFO " count0 = 0x%08x\n",
- inl(chan->io + DMA_BUFFER0_COUNT));
+ readl(chan->io + DMA_BUFFER0_COUNT));
printk(KERN_INFO " count1 = 0x%08x\n",
- inl(chan->io + DMA_BUFFER1_COUNT));
+ readl(chan->io + DMA_BUFFER1_COUNT));
}
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/irq.c,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- irq.c 9 Mar 2002 01:40:52 -0000 1.15
+++ irq.c 23 Mar 2002 02:13:01 -0000 1.16
@@ -103,86 +103,86 @@
if (irq_nr > AU1000_LAST_INTC0_INT) {
switch (type) {
case INTC_INT_RISE_EDGE: /* 0:0:1 */
- outl(1<<(irq_nr-32), IC1_CFG2CLR);
- outl(1<<(irq_nr-32), IC1_CFG1CLR);
- outl(1<<(irq_nr-32), IC1_CFG0SET);
+ writel(1<<(irq_nr-32), IC1_CFG2CLR);
+ writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ writel(1<<(irq_nr-32), IC1_CFG0SET);
break;
case INTC_INT_FALL_EDGE: /* 0:1:0 */
- outl(1<<(irq_nr-32), IC1_CFG2CLR);
- outl(1<<(irq_nr-32), IC1_CFG1SET);
- outl(1<<(irq_nr-32), IC1_CFG0CLR);
+ writel(1<<(irq_nr-32), IC1_CFG2CLR);
+ writel(1<<(irq_nr-32), IC1_CFG1SET);
+ writel(1<<(irq_nr-32), IC1_CFG0CLR);
break;
case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
- outl(1<<(irq_nr-32), IC1_CFG2SET);
- outl(1<<(irq_nr-32), IC1_CFG1CLR);
- outl(1<<(irq_nr-32), IC1_CFG0SET);
+ writel(1<<(irq_nr-32), IC1_CFG2SET);
+ writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ writel(1<<(irq_nr-32), IC1_CFG0SET);
break;
case INTC_INT_LOW_LEVEL: /* 1:1:0 */
- outl(1<<(irq_nr-32), IC1_CFG2SET);
- outl(1<<(irq_nr-32), IC1_CFG1SET);
- outl(1<<(irq_nr-32), IC1_CFG0CLR);
+ writel(1<<(irq_nr-32), IC1_CFG2SET);
+ writel(1<<(irq_nr-32), IC1_CFG1SET);
+ writel(1<<(irq_nr-32), IC1_CFG0CLR);
break;
case INTC_INT_DISABLED: /* 0:0:0 */
- outl(1<<(irq_nr-32), IC1_CFG0CLR);
- outl(1<<(irq_nr-32), IC1_CFG1CLR);
- outl(1<<(irq_nr-32), IC1_CFG2CLR);
+ writel(1<<(irq_nr-32), IC1_CFG0CLR);
+ writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ writel(1<<(irq_nr-32), IC1_CFG2CLR);
break;
default: /* disable the interrupt */
printk("unexpected int type %d (irq %d)\n", type, irq_nr);
- outl(1<<(irq_nr-32), IC1_CFG0CLR);
- outl(1<<(irq_nr-32), IC1_CFG1CLR);
- outl(1<<(irq_nr-32), IC1_CFG2CLR);
+ writel(1<<(irq_nr-32), IC1_CFG0CLR);
+ writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ writel(1<<(irq_nr-32), IC1_CFG2CLR);
return;
}
if (int_req) /* assign to interrupt request 1 */
- outl(1<<(irq_nr-32), IC1_ASSIGNCLR);
+ writel(1<<(irq_nr-32), IC1_ASSIGNCLR);
else /* assign to interrupt request 0 */
- outl(1<<(irq_nr-32), IC1_ASSIGNSET);
- outl(1<<(irq_nr-32), IC1_SRCSET);
- outl(1<<(irq_nr-32), IC1_MASKCLR);
- outl(1<<(irq_nr-32), IC1_WAKECLR);
+ writel(1<<(irq_nr-32), IC1_ASSIGNSET);
+ writel(1<<(irq_nr-32), IC1_SRCSET);
+ writel(1<<(irq_nr-32), IC1_MASKCLR);
+ writel(1<<(irq_nr-32), IC1_WAKECLR);
}
else {
switch (type) {
case INTC_INT_RISE_EDGE: /* 0:0:1 */
- outl(1<<irq_nr, IC0_CFG2CLR);
- outl(1<<irq_nr, IC0_CFG1CLR);
- outl(1<<irq_nr, IC0_CFG0SET);
+ writel(1<<irq_nr, IC0_CFG2CLR);
+ writel(1<<irq_nr, IC0_CFG1CLR);
+ writel(1<<irq_nr, IC0_CFG0SET);
break;
case INTC_INT_FALL_EDGE: /* 0:1:0 */
- outl(1<<irq_nr, IC0_CFG2CLR);
- outl(1<<irq_nr, IC0_CFG1SET);
- outl(1<<irq_nr, IC0_CFG0CLR);
+ writel(1<<irq_nr, IC0_CFG2CLR);
+ writel(1<<irq_nr, IC0_CFG1SET);
+ writel(1<<irq_nr, IC0_CFG0CLR);
break;
case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
- outl(1<<irq_nr, IC0_CFG2SET);
- outl(1<<irq_nr, IC0_CFG1CLR);
- outl(1<<irq_nr, IC0_CFG0SET);
+ writel(1<<irq_nr, IC0_CFG2SET);
+ writel(1<<irq_nr, IC0_CFG1CLR);
+ writel(1<<irq_nr, IC0_CFG0SET);
break;
case INTC_INT_LOW_LEVEL: /* 1:1:0 */
- outl(1<<irq_nr, IC0_CFG2SET);
- outl(1<<irq_nr, IC0_CFG1SET);
- outl(1<<irq_nr, IC0_CFG0CLR);
+ writel(1<<irq_nr, IC0_CFG2SET);
+ writel(1<<irq_nr, IC0_CFG1SET);
+ writel(1<<irq_nr, IC0_CFG0CLR);
break;
case INTC_INT_DISABLED: /* 0:0:0 */
- outl(1<<irq_nr, IC0_CFG0CLR);
- outl(1<<irq_nr, IC0_CFG1CLR);
- outl(1<<irq_nr, IC0_CFG2CLR);
+ writel(1<<irq_nr, IC0_CFG0CLR);
+ writel(1<<irq_nr, IC0_CFG1CLR);
+ writel(1<<irq_nr, IC0_CFG2CLR);
break;
default: /* disable the interrupt */
printk("unexpected int type %d (irq %d)\n", type, irq_nr);
- outl(1<<irq_nr, IC0_CFG0CLR);
- outl(1<<irq_nr, IC0_CFG1CLR);
- outl(1<<irq_nr, IC0_CFG2CLR);
+ writel(1<<irq_nr, IC0_CFG0CLR);
+ writel(1<<irq_nr, IC0_CFG1CLR);
+ writel(1<<irq_nr, IC0_CFG2CLR);
return;
}
if (int_req) /* assign to interrupt request 1 */
- outl(1<<irq_nr, IC0_ASSIGNCLR);
+ writel(1<<irq_nr, IC0_ASSIGNCLR);
else /* assign to interrupt request 0 */
- outl(1<<irq_nr, IC0_ASSIGNSET);
- outl(1<<irq_nr, IC0_SRCSET);
- outl(1<<irq_nr, IC0_MASKCLR);
- outl(1<<irq_nr, IC0_WAKECLR);
+ writel(1<<irq_nr, IC0_ASSIGNSET);
+ writel(1<<irq_nr, IC0_SRCSET);
+ writel(1<<irq_nr, IC0_MASKCLR);
+ writel(1<<irq_nr, IC0_WAKECLR);
}
au_sync();
}
@@ -205,12 +205,12 @@
inline void local_enable_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- outl(1<<(irq_nr-32), IC1_MASKSET);
- outl(1<<(irq_nr-32), IC1_WAKESET);
+ writel(1<<(irq_nr-32), IC1_MASKSET);
+ writel(1<<(irq_nr-32), IC1_WAKESET);
}
else {
- outl(1<<irq_nr, IC0_MASKSET);
- outl(1<<irq_nr, IC0_WAKESET);
+ writel(1<<irq_nr, IC0_MASKSET);
+ writel(1<<irq_nr, IC0_WAKESET);
}
au_sync();
}
@@ -219,12 +219,12 @@
inline void local_disable_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- outl(1<<(irq_nr-32), IC1_MASKCLR);
- outl(1<<(irq_nr-32), IC1_WAKECLR);
+ writel(1<<(irq_nr-32), IC1_MASKCLR);
+ writel(1<<(irq_nr-32), IC1_WAKECLR);
}
else {
- outl(1<<irq_nr, IC0_MASKCLR);
- outl(1<<irq_nr, IC0_WAKECLR);
+ writel(1<<irq_nr, IC0_MASKCLR);
+ writel(1<<irq_nr, IC0_WAKECLR);
}
au_sync();
}
@@ -233,12 +233,12 @@
static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- outl(1<<(irq_nr-32), IC1_RISINGCLR);
- outl(1<<(irq_nr-32), IC1_MASKCLR);
+ writel(1<<(irq_nr-32), IC1_RISINGCLR);
+ writel(1<<(irq_nr-32), IC1_MASKCLR);
}
else {
- outl(1<<irq_nr, IC0_RISINGCLR);
- outl(1<<irq_nr, IC0_MASKCLR);
+ writel(1<<irq_nr, IC0_RISINGCLR);
+ writel(1<<irq_nr, IC0_MASKCLR);
}
au_sync();
}
@@ -247,12 +247,12 @@
static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- outl(1<<(irq_nr-32), IC1_FALLINGCLR);
- outl(1<<(irq_nr-32), IC1_MASKCLR);
+ writel(1<<(irq_nr-32), IC1_FALLINGCLR);
+ writel(1<<(irq_nr-32), IC1_MASKCLR);
}
else {
- outl(1<<irq_nr, IC0_FALLINGCLR);
- outl(1<<irq_nr, IC0_MASKCLR);
+ writel(1<<irq_nr, IC0_FALLINGCLR);
+ writel(1<<irq_nr, IC0_MASKCLR);
}
au_sync();
}
@@ -490,8 +490,8 @@
int irq = 0, i;
static unsigned long intc0_req0 = 0;
- intc0_req0 |= inl(IC0_REQ0INT);
-
+ intc0_req0 |= readl(IC0_REQ0INT);
+
if (!intc0_req0) return;
for (i=0; i<32; i++) {
@@ -510,7 +510,7 @@
int irq = 0, i;
static unsigned long intc0_req1 = 0;
- intc0_req1 = inl(IC0_REQ1INT);
+ intc0_req1 = readl(IC0_REQ1INT);
if (!intc0_req1) return;
@@ -546,7 +546,7 @@
volatile unsigned short levels, mdr;
unsigned char ide_status;
- intc1_req0 |= inl(IC1_REQ0INT);
+ intc1_req0 |= readl(IC1_REQ0INT);
if (!intc1_req0) return;
@@ -578,7 +578,7 @@
int irq = 0, i;
static unsigned long intc1_req1 = 0;
- intc1_req1 |= inl(IC1_REQ1INT);
+ intc1_req1 |= readl(IC1_REQ1INT);
if (!intc1_req1) return;
Index: serial.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/serial.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- serial.c 15 Feb 2002 19:47:24 -0000 1.7
+++ serial.c 23 Mar 2002 02:13:01 -0000 1.8
@@ -241,12 +241,12 @@
static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
{
- return (inl(info->port+offset) & 0xffff);
+ return (readl(info->port+offset) & 0xffff);
}
static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
{
- outl(value & 0xffff, info->port+offset);
+ writel(value & 0xffff, info->port+offset);
}
@@ -750,8 +750,8 @@
info->xmit.buf = (unsigned char *) page;
- if (inl(UART_MOD_CNTRL + state->port) != 0x3) {
- outl(3, UART_MOD_CNTRL + state->port);
+ if (readl(UART_MOD_CNTRL + state->port) != 0x3) {
+ writel(3, UART_MOD_CNTRL + state->port);
au_sync_delay(10);
}
#ifdef SERIAL_DEBUG_OPEN
@@ -988,7 +988,7 @@
info->flags &= ~ASYNC_INITIALIZED;
#ifndef CONFIG_REMOTE_DEBUG
- outl(0, UART_MOD_CNTRL + state->port);
+ writel(0, UART_MOD_CNTRL + state->port);
au_sync_delay(10);
#endif
restore_flags(flags);
@@ -2515,8 +2515,8 @@
if (!CONFIGURED_SERIAL_PORT(state))
return;
- if (inl(UART_MOD_CNTRL + state->port) != 0x3) {
- outl(3, UART_MOD_CNTRL + state->port);
+ if (readl(UART_MOD_CNTRL + state->port) != 0x3) {
+ writel(3, UART_MOD_CNTRL + state->port);
au_sync_delay(10);
}
@@ -2550,7 +2550,7 @@
serial_outp(info, UART_IER, 0);
#ifndef CONFIG_REMOTE_DEBUG
- outl(0, UART_MOD_CNTRL + state->port);
+ writel(0, UART_MOD_CNTRL + state->port);
au_sync_delay(10);
#endif
restore_flags(flags);
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/time.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- time.c 15 Feb 2002 19:47:24 -0000 1.10
+++ time.c 23 Mar 2002 02:13:01 -0000 1.11
@@ -129,7 +129,7 @@
return;
}
- pc0 = inl(SYS_TOYREAD);
+ pc0 = readl(SYS_TOYREAD);
if (pc0 < last_match20) {
/* counter overflowed */
time_elapsed = (0xffffffff - last_match20) + pc0;
@@ -146,7 +146,7 @@
}
last_pc0 = pc0;
- outl(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
+ writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
au_sync();
/* our counter ticks at 10.009765625 ms/tick, we we're running
@@ -176,27 +176,27 @@
save_and_cli(flags);
- counter = inl(SYS_COUNTER_CNTRL);
- outl(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
+ counter = readl(SYS_COUNTER_CNTRL);
+ writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
- while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
- outl(trim_divide-1, SYS_RTCTRIM); /* RTC now ticks at 32.768/16 kHz */
- while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
+ while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
+ writel(trim_divide-1, SYS_RTCTRIM); /* RTC now ticks at 32.768/16 kHz */
+ while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
- while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
- outl (0, SYS_TOYWRITE);
- while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
+ while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
+ writel (0, SYS_TOYWRITE);
+ while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
- start = inl(SYS_RTCREAD);
+ start = readl(SYS_RTCREAD);
start += 2;
/* wait for the beginning of a new tick */
- while (inl(SYS_RTCREAD) < start);
+ while (readl(SYS_RTCREAD) < start);
/* Start r4k counter. */
write_32bit_cp0_register(CP0_COUNT, 0);
end = start + (32768 / trim_divide)/2; /* wait 0.5 seconds */
- while (end > inl(SYS_RTCREAD));
+ while (end > readl(SYS_RTCREAD));
count = read_32bit_cp0_register(CP0_COUNT);
cpu_speed = count * 2;
Index: usbdev.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/usbdev.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- usbdev.c 15 Feb 2002 19:47:24 -0000 1.8
+++ usbdev.c 23 Mar 2002 02:13:01 -0000 1.9
@@ -591,7 +591,7 @@
spin_lock_irqsave(&ep->lock, flags);
- cs = inl(ep->reg->ctrl_stat) | USBDEV_CS_STALL;
+ cs = readl(ep->reg->ctrl_stat) | USBDEV_CS_STALL;
outl_sync(cs, ep->reg->ctrl_stat);
spin_unlock_irqrestore(&ep->lock, flags);
@@ -607,7 +607,7 @@
spin_lock_irqsave(&ep->lock, flags);
- cs = inl(ep->reg->ctrl_stat) & ~USBDEV_CS_STALL;
+ cs = readl(ep->reg->ctrl_stat) & ~USBDEV_CS_STALL;
outl_sync(cs, ep->reg->ctrl_stat);
spin_unlock_irqrestore(&ep->lock, flags);
@@ -635,8 +635,8 @@
spin_lock_irqsave(&ep->lock, flags);
bufptr = pkt->bufptr;
- while (inl(ep->reg->read_fifo_status) & USBDEV_FSTAT_FCNT_MASK) {
- *bufptr++ = inl(ep->reg->read_fifo) & 0xff;
+ while (readl(ep->reg->read_fifo_status) & USBDEV_FSTAT_FCNT_MASK) {
+ *bufptr++ = readl(ep->reg->read_fifo) & 0xff;
read_count++;
pkt->size++;
}
@@ -661,7 +661,7 @@
spin_lock_irqsave(&ep->lock, flags);
bufptr = pkt->bufptr;
- while ((inl(ep->reg->write_fifo_status) & USBDEV_FSTAT_FCNT_MASK) <
+ while ((readl(ep->reg->write_fifo_status) & USBDEV_FSTAT_FCNT_MASK) <
EP_FIFO_DEPTH) {
if (bufptr < pkt->buf + pkt->size) {
outl_sync(*bufptr++, ep->reg->write_fifo);
@@ -698,7 +698,7 @@
* working right, but flush it anyway just in case.
*/
flush_write_fifo(ep);
- cs = inl(ep->reg->ctrl_stat) & USBDEV_CS_STALL;
+ cs = readl(ep->reg->ctrl_stat) & USBDEV_CS_STALL;
cs |= (pkt->size << USBDEV_CS_TSIZE_BIT);
outl_sync(cs, ep->reg->ctrl_stat);
#ifdef USBDEV_PIO
@@ -731,7 +731,7 @@
dbg(__FUNCTION__ ": pkt=%p, ab=%d",
ep->inlist.head, get_dma_active_buffer(ep->indma));
- outl_sync(inl(ep->reg->ctrl_stat) & USBDEV_CS_STALL,
+ outl_sync(readl(ep->reg->ctrl_stat) & USBDEV_CS_STALL,
ep->reg->ctrl_stat);
//disable_dma(ep->indma);
free_packet(ep, &ep->inlist);
@@ -1084,7 +1084,7 @@
pkt_t *pkt = 0;
u32 cs;
- cs = inl(ep->reg->ctrl_stat);
+ cs = readl(ep->reg->ctrl_stat);
switch (fifo_num) {
case 0:
@@ -1151,7 +1151,7 @@
int i;
u32 status;
- status = inl(USB_DEV_INT_STATUS);
+ status = readl(USB_DEV_INT_STATUS);
outl_sync(status, USB_DEV_INT_STATUS); // ack'em
#ifdef USBDEV_PIO
@@ -1181,7 +1181,7 @@
u32 cs0, buff_done;
spin_lock(&ep->lock);
- cs0 = inl(ep->reg->ctrl_stat);
+ cs0 = readl(ep->reg->ctrl_stat);
// first check packet transmit done
if ((buff_done = get_dma_buffer_done(ep->indma)) != 0) {
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