[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/vr4122/common Makefile,NONE,1.1 bcu.c,NONE,1.1 cmu.c,NONE,1.1 dbg_io.c,NONE,1.1 icu.c,NONE,1.1 icu.h,NONE,1.1 pciu.c,NONE,1.1 pciu.h,NONE,1.1 siu.c,NONE,1.1 siu.h,NONE,1.1 vrc4173.c,NONE,1.1

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4122/common
In directory usw-pr-cvs1:/tmp/cvs-serv28915/arch/mips/vr41xx/vr4122/common

Added Files:
	Makefile bcu.c cmu.c dbg_io.c icu.c icu.h pciu.c pciu.h siu.c 
	siu.h vrc4173.c 
Log Message:
Imported Yoichi-san's Vr41xx patch, with some minor modifications.



--- NEW FILE: Makefile ---
#
# Makefile for common code of the NEC VR4122 and VR4131.
#
# Author: Yoichi Yuasa
#         yy...@mv... or so...@mv...
#
# Copyright 2001,2002 MontaVista Software Inc.
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#

.S.s:
	$(CPP) $(CFLAGS) $< -o $*.s
.S.o:
	$(CC) $(CFLAGS) -c $< -o $*.o

all: vr4122.o

O_TARGET := vr4122.o

export-objs	:= vrc4173.o
obj-y		:= bcu.o cmu.o icu.o siu.o

obj-$(CONFIG_PCI)		+= pciu.o
obj-$(CONFIG_VRC4173)		+= vrc4173.o
obj-$(CONFIG_REMOTE_DEBUG)	+= dbg_io.o

include $(TOPDIR)/Rules.make

--- NEW FILE: bcu.c ---
/*
 * FILE NAME
 *	arch/mips/vr41xx/vr4122/common/bcu.c
 *
 * BRIEF MODULE DESCRIPTION
 *	Bus Control Unit routines for the NEC VR4122 and VR4131.
 *
 * Author: Yoichi Yuasa
 *         yy...@mv... or so...@mv...
 *
 * Copyright 2002 MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
/*
 * Changes:
 *  MontaVista Software Inc. <yy...@mv...> or <so...@mv...>
 *  - New creation, NEC VR4122 and VR4131 are supported.
 */
#include <linux/types.h>

#include <asm/io.h>
#include <asm/param.h>
#include <asm/time.h>

#define CLKSPEEDREG			KSEG1ADDR(0x0f000014)
#define PMUTCLKDIVREG			KSEG1ADDR(0x0f0000cc)
#define calc_pclock(clksp)		((18432000 * 98) / ((clksp) & 0x001f))
#define calc_tclock(clksp,vtclock)	((vtclock) / (2 << (((clksp) & 0x1000) >> 12)))

unsigned long vr41xx_vtclock = 0;

static inline unsigned long calc_vtclock(u16 clksp, unsigned long pclock)
{
#ifdef CONFIG_VR4122_CLKSPEEDREG_FIX
	if ((clksp & 0x0700) == 0x0100) {
		u16 div;
		div = readw(PMUTCLKDIVREG);
		if ((div & 0x0007) == 0x0002)
			clksp = (clksp & ~0x0700) | 0x0200;
	}
#endif
	return pclock / ((clksp & 0x0700) >> 8);
}

void vr41xx_bcu_init(void)
{
	unsigned long pclock, tclock;
	u16 clksp;

	clksp = readw(CLKSPEEDREG);
	pclock = calc_pclock(clksp);
	printk(KERN_INFO "PClock: %ldHz\n", pclock);

	vr41xx_vtclock = calc_vtclock(clksp, pclock);
	printk(KERN_INFO "VTClock: %ldHz\n", vr41xx_vtclock);

	tclock = calc_tclock(clksp, vr41xx_vtclock);
	printk(KERN_INFO "TClock: %ldHz\n", tclock);

	mips_counter_frequency = tclock / 4;
}

--- NEW FILE: cmu.c ---
/*
 * FILE NAME
 *	arch/mips/vr41xx/vr4122/common/cmu.c
 *
 * BRIEF MODULE DESCRIPTION
 *	Clock Mask Unit routines for the NEC VR4122 and VR4131.
 *
 * Author: Yoichi Yuasa
 *         yy...@mv... or so...@mv...
 *
 * Copyright 2001,2002 MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
/*
 * Changes:
 *  MontaVista Software Inc. <yy...@mv...> or <so...@mv...>
 *  - New creation, NEC VR4122 and VR4131 are supported.
 */
#include <linux/spinlock.h>
#include <linux/types.h>

#include <asm/io.h>

#define CMUCLKMSK	KSEG1ADDR(0x0f000060)

rwlock_t vr41xx_cmu_lock = RW_LOCK_UNLOCKED;

void vr41xx_clock_supply(u16 mask)
{
	unsigned long flags;
	u16 val;

	write_lock_irqsave(&vr41xx_cmu_lock, flags);
	val = readw(CMUCLKMSK);
	val |= mask;
	writew(val, CMUCLKMSK);
	write_unlock_irqrestore(&vr41xx_cmu_lock, flags);
}

void vr41xx_clock_mask(u16 mask)
{
	unsigned long flags;
	u16 val;

	write_lock_irqsave(&vr41xx_cmu_lock, flags);
	val = readw(CMUCLKMSK);
	val &= ~mask;
	writew(val, CMUCLKMSK);
	write_unlock_irqrestore(&vr41xx_cmu_lock, flags);
}

--- NEW FILE: dbg_io.c ---

#include <linux/config.h>

#ifdef CONFIG_REMOTE_DEBUG

/* --- CONFIG --- */

/* we need uint32 uint8 */
typedef         unsigned char  uint8;
typedef         unsigned short uint16;
typedef         unsigned int   uint32;

/* --- END OF CONFIG --- */

#define         UART16550_BAUD_2400             2400
#define         UART16550_BAUD_4800             4800
#define         UART16550_BAUD_9600             9600
#define         UART16550_BAUD_19200            19200
#define         UART16550_BAUD_38400            38400
#define         UART16550_BAUD_57600            57600
#define         UART16550_BAUD_115200           115200

#define         UART16550_PARITY_NONE           0
#define         UART16550_PARITY_ODD            0x08
#define         UART16550_PARITY_EVEN           0x18
#define         UART16550_PARITY_MARK           0x28
#define         UART16550_PARITY_SPACE          0x38

#define         UART16550_DATA_5BIT             0x0
#define         UART16550_DATA_6BIT             0x1
#define         UART16550_DATA_7BIT             0x2
#define         UART16550_DATA_8BIT             0x3

#define         UART16550_STOP_1BIT             0x0
#define         UART16550_STOP_2BIT             0x4

/* ----------------------------------------------------- */

/* === CONFIG === */

/* [stevel] we use the IT8712 serial port for kgdb */
#define	DEBUG_BASE  0xAF000820 /* Vr4122 DSIU base address */
#define MAX_BAUD    115200

/* === END OF CONFIG === */

/* register offset */
#define         OFS_RCV_BUFFER          0
#define         OFS_TRANS_HOLD          0
#define         OFS_SEND_BUFFER         0
#define         OFS_INTR_ENABLE         1
#define         OFS_INTR_ID             2
#define         OFS_DATA_FORMAT         3
#define         OFS_LINE_CONTROL        3
#define         OFS_MODEM_CONTROL       4
#define         OFS_RS232_OUTPUT        4
#define         OFS_LINE_STATUS         5
#define         OFS_MODEM_STATUS        6
#define         OFS_RS232_INPUT         6
#define         OFS_SCRATCH_PAD         7

#define         OFS_DIVISOR_LSB         0
#define         OFS_DIVISOR_MSB         1


/* memory-mapped read/write of the port */
#define UART16550_READ(y)    (*((volatile uint8*)(DEBUG_BASE + y)))
#define UART16550_WRITE(y,z) ((*((volatile uint8*)(DEBUG_BASE + y))) = z)

void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
    uint16 mask;

    /* disable interrupts */
    UART16550_WRITE(OFS_INTR_ENABLE, 0);

    /* turn on the clocks to the serial port */
    mask = *((volatile uint16 *)(0xAF000808));
    mask &= ~0x0001;
    *((volatile uint16 *)(0xAF000808)) = mask;

    mask = *((volatile uint16 *)(0xAF000060));
    mask |= 0x0802;
    *((volatile uint16 *)(0xAF000060)) = mask;

    /* set up buad rate */
    { 
        uint32 divisor;
       
        /* set DIAB bit */
        UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
        
        /* set divisor */
        divisor = MAX_BAUD / baud;
        UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
        UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00)>>8);

        /* clear DIAB bit */
        UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
    }

    /* set data format */
    UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
}

static int remoteDebugInitialized = 0;

uint8 getDebugChar(void)
{
    if (!remoteDebugInitialized) {
	remoteDebugInitialized = 1;
	debugInit(UART16550_BAUD_115200,
		  UART16550_DATA_8BIT,
		  UART16550_PARITY_NONE,
		  UART16550_STOP_1BIT);
    }

    while((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
    return UART16550_READ(OFS_RCV_BUFFER);
}


int putDebugChar(uint8 byte)
{
    if (!remoteDebugInitialized) {
	remoteDebugInitialized = 1;
	debugInit(UART16550_BAUD_115200,
		  UART16550_DATA_8BIT,
		  UART16550_PARITY_NONE,
		  UART16550_STOP_1BIT);
    }

    while ((UART16550_READ(OFS_LINE_STATUS) &0x20) == 0);
    UART16550_WRITE(OFS_SEND_BUFFER, byte);
    return 1;
}

#endif

--- NEW FILE: icu.c ---
/*
 * FILE NAME
 *	arch/mips/vr41xx/vr4122/common/icu.c
 *
 * BRIEF MODULE DESCRIPTION
 *	Interrupt Control Unit routines for the NEC VR4122 and VR4131.
 *
 * Author: Yoichi Yuasa
 *         yy...@mv... or so...@mv...
 *
 * Copyright 2001,2002 MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
/*
 * Changes:
 *  MontaVista Software Inc. <yy...@mv...> or <so...@mv...>
 *  - New creation, NEC VR4122 and VR4131 are supported.
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/types.h>

#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/vr41xx.h>

#include "icu.h"

extern asmlinkage void vr41xx_handle_interrupt(void);
extern void __init init_generic_irq(void);
extern void mips_cpu_irq_init(u32 irq_base);
extern unsigned int do_IRQ(int irq, struct pt_regs *regs);

/*=======================================================================*/

static void enable_sysint1_irq(unsigned int irq)
{
	u16 val;

	val = readw(MSYSINT1REG);
	val |= (u16)1 << (irq - SYSINT1_IRQ_BASE);
	writew(val, MSYSINT1REG);
}

static void disable_sysint1_irq(unsigned int irq)
{
	u16 val;

	val = readw(MSYSINT1REG);
	val &= ~((u16)1 << (irq - SYSINT1_IRQ_BASE));
	writew(val, MSYSINT1REG);
}

static unsigned int startup_sysint1_irq(unsigned int irq)
{ 
	enable_sysint1_irq(irq);
	return 0; /* never anything pending */
}

#define shutdown_sysint1_irq	disable_sysint1_irq
#define ack_sysint1_irq		disable_sysint1_irq

static void end_sysint1_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_sysint1_irq(irq);
}

static struct hw_interrupt_type sysint1_irq_type = {
	"SYSINT1",
	startup_sysint1_irq,
	shutdown_sysint1_irq,
	enable_sysint1_irq,
	disable_sysint1_irq,
	ack_sysint1_irq,
	end_sysint1_irq,
	NULL
};

/*=======================================================================*/

static void enable_sysint2_irq(unsigned int irq)
{
	u16 val;

	val = readw(MSYSINT2REG);
	val |= (u16)1 << (irq - SYSINT2_IRQ_BASE);
	writew(val, MSYSINT2REG);
}

static void disable_sysint2_irq(unsigned int irq)
{
	u16 val;

	val = readw(MSYSINT2REG);
	val &= ~((u16)1 << (irq - SYSINT2_IRQ_BASE));
	writew(val, MSYSINT2REG);
}

static unsigned int startup_sysint2_irq(unsigned int irq)
{ 
	enable_sysint2_irq(irq);
	return 0; /* never anything pending */
}

#define shutdown_sysint2_irq	disable_sysint2_irq
#define ack_sysint2_irq		disable_sysint2_irq

static void end_sysint2_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_sysint2_irq(irq);
}

static struct hw_interrupt_type sysint2_irq_type = {
	"SYSINT2",
	startup_sysint2_irq,
	shutdown_sysint2_irq,
	enable_sysint2_irq,
	disable_sysint2_irq,
	ack_sysint2_irq,
	end_sysint2_irq,
	NULL
};

/*=======================================================================*/

static void enable_giuintl_irq(unsigned int irq)
{
	u16 val, mask;

	mask = (u16)1 << (irq - GIUINTL_IRQ_BASE);
	writew(mask, GIUINTSTATL);

	val = readw(MGIUINTLREG);
	val |= mask;
	writew(val, MGIUINTLREG);

	val = readw(GIUINTENL);
	val |= mask;
	writew(val, GIUINTENL);
}

static void disable_giuintl_irq(unsigned int irq)
{
	u16 val, mask;

	mask = (u16)1 << (irq - GIUINTL_IRQ_BASE);
	val = readw(GIUINTENL);
	val &= ~mask;
	writew(val, GIUINTENL);

	val = readw(MGIUINTLREG);
	val &= ~mask;
	writew(val, MGIUINTLREG);

	writew(mask, GIUINTSTATL);
}

static unsigned int startup_giuintl_irq(unsigned int irq)
{ 
	enable_giuintl_irq(irq);
	return 0; /* never anything pending */
}

#define shutdown_giuintl_irq	disable_giuintl_irq
#define ack_giuintl_irq		disable_giuintl_irq

static void end_giuintl_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_giuintl_irq(irq);
}

static struct hw_interrupt_type giuintl_irq_type = {
	"GIUINTL",
	startup_giuintl_irq,
	shutdown_giuintl_irq,
	enable_giuintl_irq,
	disable_giuintl_irq,
	ack_giuintl_irq,
	end_giuintl_irq,
	NULL
};

/*=======================================================================*/

static void enable_giuinth_irq(unsigned int irq)
{
	unsigned short val, mask;

	mask = (u16)1 << (irq - GIUINTH_IRQ_BASE);
	writew(mask, GIUINTSTATH);

	val = readw(MGIUINTHREG);
	val |= mask;
	writew(val, MGIUINTHREG);

	val = readw(GIUINTENH);
	val |= mask;
	writew(val, GIUINTENH);
}

static void disable_giuinth_irq(unsigned int irq)
{
	unsigned short val, mask;

	mask = (u16)1 << (irq - GIUINTH_IRQ_BASE);
	val= readw(GIUINTENH);
	val &= ~mask;
	writew(val, GIUINTENH);

	val = readw(MGIUINTHREG);
	val &= ~mask;
	writew(val, MGIUINTHREG);

	writew(mask, GIUINTSTATH);
}

static unsigned int startup_giuinth_irq(unsigned int irq)
{ 
	enable_giuinth_irq(irq);
	return 0; /* never anything pending */
}

#define shutdown_giuinth_irq	disable_giuinth_irq
#define ack_giuinth_irq		disable_giuinth_irq

static void end_giuinth_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_giuinth_irq(irq);
}

static struct hw_interrupt_type giuinth_irq_type = {
	"GIUINTH",
	startup_giuinth_irq,
	shutdown_giuinth_irq,
	enable_giuinth_irq,
	disable_giuinth_irq,
	ack_giuinth_irq,
	end_giuinth_irq,
	NULL
};

/*=======================================================================*/

static struct irqcascade vr41xx_irqcascade[32];

static struct irqaction cascade = {no_action, 0, 0, "cascade", NULL, NULL};
static int no_cascade_get_irq_number(int irq) { return -1; }

void vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq))
{
	if (GIUINTL_IRQ_BASE <= irq < GIUINTH_IRQ_LAST) {
		vr41xx_irqcascade[irq - GIUINTL_IRQ_BASE].cascade = 1;
		vr41xx_irqcascade[irq - GIUINTL_IRQ_BASE].get_irq_number = get_irq_number;
		setup_irq(irq, &cascade);
	}
}


static void __init vr41xx_icu_irq_init(void)
{
	int i;

	writew(0, MSYSINT1REG);
	writew(0, MSYSINT2REG);
	writew(0, MGIUINTLREG);
	writew(0, MGIUINTHREG);

	writew(0, GIUINTENL);
	writew(0, GIUINTENH);
	writew(0xffff, GIUINTSTATL);
	writew(0xffff, GIUINTSTATH);

	for (i = SYSINT1_IRQ_BASE; i <= GIUINTH_IRQ_LAST; i++) {
		if (i >= SYSINT1_IRQ_BASE && i <= SYSINT1_IRQ_LAST)
			irq_desc[i].handler = &sysint1_irq_type;
		else if (i >= SYSINT2_IRQ_BASE && i <= SYSINT2_IRQ_LAST)
			irq_desc[i].handler = &sysint2_irq_type;
		else if (i >= GIUINTL_IRQ_BASE && i <= GIUINTL_IRQ_LAST)
			irq_desc[i].handler = &giuintl_irq_type;
		else if (i >= GIUINTH_IRQ_BASE && i <= GIUINTH_IRQ_LAST)
			irq_desc[i].handler = &giuinth_irq_type;
	}

	for (i = 0; i < 32; i++) {
		vr41xx_irqcascade[i].cascade = 0;
		vr41xx_irqcascade[i].get_irq_number = no_cascade_get_irq_number;
	}

}

void __init init_IRQ(void)
{

	memset(irq_desc, 0, sizeof(irq_desc));

	init_generic_irq();
	mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
	vr41xx_icu_irq_init();
	vr41xx_board_irq_init();

	setup_irq(ICU_IRQ, &cascade);
	setup_irq(GIU_IRQ, &cascade);

	set_except_vector(0, vr41xx_handle_interrupt);
}

/*=======================================================================*/

static void giuint_do_IRQ(int giuint_irq, struct pt_regs *regs)
{
	struct irqcascade *irq;
	int cascade_irq;

	irq = &vr41xx_irqcascade[giuint_irq - GIUINTL_IRQ_BASE];
	if (irq->cascade) {
		cascade_irq = irq->get_irq_number(giuint_irq);
		disable_irq(giuint_irq);
		if (cascade_irq > 0)
			do_IRQ(cascade_irq, regs);
		enable_irq(giuint_irq);
	}
	else
		do_IRQ(giuint_irq, regs);
}

static inline void giuint_irqdispatch(u16 pendl, u16 pendh, struct pt_regs *regs)
{
	int i;

	if (pendl) {
		for (i = 0; i < 16; i++) {
			if (pendl & (0x0001 << i)) {
				giuint_do_IRQ(GIUINTL_IRQ_BASE + i, regs);
				return;
			}
		}
	}
	else if (pendh) {
		for (i = 0; i < 16; i++) {
			if (pendh & (0x0001 << i)) {
				giuint_do_IRQ(GIUINTH_IRQ_BASE + i, regs);
				return;
			}
		}
	}
}

asmlinkage void icu_irqdispatch(struct pt_regs *regs)
{
	u16 pend1, pend2, pendl, pendh;
	u16 mask1, mask2, maskl, maskh;
	int i;

	pend1 = readw(SYSINT1REG);
	mask1 = readw(MSYSINT1REG);

	pend2 = readw(SYSINT2REG);
	mask2 = readw(MSYSINT2REG);

	pendl = readw(GIUINTLREG);
	maskl = readw(MGIUINTLREG);

	pendh = readw(GIUINTHREG);
	maskh = readw(MGIUINTHREG);

	pend1 &= mask1;
	pend2 &= mask2;
	pendl &= maskl;
	pendh &= maskh;

	if (pend1) {
		if ((pend1 & 0x01ff) == 0x0100) {
			giuint_irqdispatch(pendl, pendh, regs);
		}
		else {
			for (i = 0; i < 16; i++) {
				if (pend1 & (0x0001 << i)) {
					do_IRQ(SYSINT1_IRQ_BASE + i, regs);
					break;
				}
			}
		}
		return;
	}
	else if (pend2) {
		for (i = 0; i < 16; i++) {
			if (pend2 & (0x0001 << i)) {
				do_IRQ(SYSINT2_IRQ_BASE + i, regs);
				break;
			}
		}
	}
}

--- NEW FILE: icu.h ---
/*
 * FILE NAME
 *	arch/mips/vr41xx/vr4122/common/icu.h
 *
 * BRIEF MODULE DESCRIPTION
 *	Include file for Interrupt Control Unit of the NEC VR4122 and VR4131.
 *
 * Author: Yoichi Yuasa
 *         yy...@mv... or so...@mv...
 *
 * Copyright 2002 MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
/*
 * Changes:
 *  MontaVista Software Inc. <yy...@mv...> or <so...@mv...>
 *  - New creation, NEC VR4122 and VR4131 are supported.
 */
#ifndef __VR41XX_ICU_H
#define __VR41XX_ICU_H

#include <linux/config.h>
#include <asm/addrspace.h>

#define SYSINT1REG	KSEG1ADDR(0x0f000080)
#define GIUINTLREG	KSEG1ADDR(0x0f000088)
#define MSYSINT1REG	KSEG1ADDR(0x0f00008c)
#define MGIUINTLREG	KSEG1ADDR(0x0f000094)

#define NMIREG		KSEG1ADDR(0x0f000098)
#define SOFTINTREG	KSEG1ADDR(0x0f00009a)

#define SYSINT2REG	KSEG1ADDR(0x0f0000a0)
#define GIUINTHREG	KSEG1ADDR(0x0f0000a2)
#define MSYSINT2REG	KSEG1ADDR(0x0f0000a6)
#define MGIUINTHREG	KSEG1ADDR(0x0f0000a8)

#define GIUINTSTATL	KSEG1ADDR(0x0f000148)
#define GIUINTSTATH	KSEG1ADDR(0x0f00014a)
#define GIUINTENL	KSEG1ADDR(0x0f00014c)
#define GIUINTENH	KSEG1ADDR(0x0f00014e)
#define GIUINTTYPL	KSEG1ADDR(0x0f000150)
#define GIUINTTYPH	KSEG1ADDR(0x0f000152)
#define GIUINTALSELL	KSEG1ADDR(0x0f000154)
#define GIUINTALSELH	KSEG1ADDR(0x0f000156)
#define GIUINTHTSELL	KSEG1ADDR(0x0f000158)
#define GIUINTHTSELH	KSEG1ADDR(0x0f00015a)

#define MIPS_CPU_IRQ_BASE	0
#define SYSINT1_IRQ_BASE	8
#define SYSINT1_IRQ_LAST	23
#define SYSINT2_IRQ_BASE	24
#define SYSINT2_IRQ_LAST	39
#define GIUINTL_IRQ_BASE	40
#define GIUINTL_IRQ_LAST	55
#define GIUINTH_IRQ_BASE	56
#define GIUINTH_IRQ_LAST	71

#define ICU_IRQ			2
#define GIU_IRQ			(SYSINT1_IRQ_BASE + 8)

#endif /* __VR41XX_ICU_H */

--- NEW FILE: pciu.c ---
/*
 * FILE NAME
 *	arch/mips/vr41xx/vr4122/common/pciu.c
 *
 * BRIEF MODULE DESCRIPTION
 *	PCI Control Unit routines for the NEC VR4122 and VR4131.
 *
 * Author: Yoichi Yuasa
 *         yy...@mv... or so...@mv...
 *
 * Copyright 2001,2002 MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
/*
 * Changes:
 *  MontaVista Software Inc. <yy...@mv...> or <so...@mv...>
 *  - New creation, NEC VR4122 and VR4131 are supported.
 */
#include <linux/config.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/types.h>

#include <asm/io.h>
#include <asm/vr41xx.h>

#include "pciu.h"

extern unsigned long vr41xx_vtclock;

static inline int vr41xx_pci_config_access(struct pci_dev *dev, int where)
{
	unsigned char bus = dev->bus->number;
	unsigned int dev_fn = dev->devfn;

	if (bus == 0) {
		/*
		 * Type 0 configuration
		 */
		if (PCI_SLOT(dev_fn) < 11 || PCI_SLOT(dev_fn) > 31 || where > 255)
			return -1;

		writel((1UL << PCI_SLOT(dev_fn))|
		       (PCI_FUNC(dev_fn) << 8)	|
		       (where & 0xfc),
		       PCICONFAREG);
	}
	else {
		/*
		 * Type 1 configuration
		 */
		if (bus > 255 || PCI_SLOT(dev_fn) > 31 || where > 255)
			return -1;

		writel((bus << 16)	|
		       (dev_fn << 8)	|
		       (where & 0xfc)	|
		       1UL,
		       PCICONFAREG);
	}

	return 0;
}

static int vr41xx_pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
{
	u32 data;

	*val = 0xff;
	if (vr41xx_pci_config_access(dev, where) < 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	data = readl(PCICONFDREG);
	*val = (u8)(data >> ((where & 3) << 3));

	return PCIBIOS_SUCCESSFUL;

}

static int vr41xx_pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
{
	u32 data;

	*val = 0xffff;
	if (where & 1)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (vr41xx_pci_config_access(dev, where) < 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	data = readl(PCICONFDREG);
	*val = (u16)(data >> ((where & 2) << 3));

	return PCIBIOS_SUCCESSFUL;
}

static int vr41xx_pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
{
	*val = 0xffffffff;
	if (where & 3)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (vr41xx_pci_config_access(dev, where) < 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	*val = readl(PCICONFDREG);

	return PCIBIOS_SUCCESSFUL;
}

static int vr41xx_pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
{
	u32 data;
	int shift;

	if (vr41xx_pci_config_access(dev, where) < 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	data = readl(PCICONFDREG);
	shift = (where & 3) << 3;
	data &= ~(0xff << shift);
	data |= (((u32)val) << shift);

	writel(data, PCICONFDREG);

	return PCIBIOS_SUCCESSFUL;
}

static int vr41xx_pci_write_config_word(struct pci_dev *dev, int where, u16 val)
{
	u32 data;
	int shift;

	if (where & 1)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (vr41xx_pci_config_access(dev, where) < 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	data = readl(PCICONFDREG);
	shift = (where & 2) << 3;
	data &= ~(0xffff << shift);
	data |= (((u32)val) << shift);
	writel(data, PCICONFDREG);

	return PCIBIOS_SUCCESSFUL;
}

static int vr41xx_pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
{
	if (where & 3)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (vr41xx_pci_config_access(dev, where) < 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	writel(val, PCICONFDREG);

	return PCIBIOS_SUCCESSFUL;
}

struct pci_ops vr41xx_pci_ops = {
	vr41xx_pci_read_config_byte,
	vr41xx_pci_read_config_word,
	vr41xx_pci_read_config_dword,
	vr41xx_pci_write_config_byte,
	vr41xx_pci_write_config_word,
	vr41xx_pci_write_config_dword
};

void __init vr41xx_pciu_init(void)
{
	int n;

	/* Disable PCI interrupt */
	writew(0, MPCIINTREG);

	/* Select PCI clock */
	if (vr41xx_vtclock < MAX_PCI_CLOCK)
		writel(EQUAL_VTCLOCK, PCICLKSELREG);
	else if ((vr41xx_vtclock / 2) < MAX_PCI_CLOCK)
		writel(HALF_VTCLOCK, PCICLKSELREG);
	else if ((vr41xx_vtclock / 4) < MAX_PCI_CLOCK)
		writel(QUARTER_VTCLOCK, PCICLKSELREG);
	else
		printk(KERN_INFO "Warning: PCI Clock is over 33MHz.\n");

	/* Supply PCI clock by PCI bus */
	vr41xx_clock_supply(PCI_CLOCK);

	/* Set master memory & I/O windows */
	writel(0x100f9010, PCIMMAW1REG);
	writel(0x140fd014, PCIMMAW2REG);
	writel(0x160fd000, PCIMIOAWREG);

	/* Set target memory windows */
	writel(0x00081000, PCITAW1REG);
	writel(0UL, PCITAW2REG);
	pciu_write_config_dword(PCI_BASE_ADDRESS_0, 0UL);
	pciu_write_config_dword(PCI_BASE_ADDRESS_1, 0UL);

	/* Clear bus error */
	n = readl(BUSERRADREG);

	writel(100, PCITRDYVREG);
	pciu_write_config_dword(PCI_CACHE_LINE_SIZE, 0x00008004);

	writel(CONFIG_DONE, PCIENREG);
	pciu_write_config_dword(PCI_COMMAND,
	                        PCI_COMMAND_IO |
	                        PCI_COMMAND_MEMORY |
	                        PCI_COMMAND_MASTER |
	                        PCI_COMMAND_PARITY |
	                        PCI_COMMAND_SERR);
}

--- NEW FILE: pciu.h ---
/*
 * FILE NAME
 *	arch/mips/vr41xx/vr4122/common/pciu.h
 *
 * BRIEF MODULE DESCRIPTION
 *	Include file for PCI Control Unit of the NEC VR4122 and VR4131.
 *
 * Author: Yoichi Yuasa
 *         yy...@mv... or so...@mv...
 *
 * Copyright 2002 MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
/*
 * Changes:
 *  MontaVista Software Inc. <yy...@mv...> or <so...@mv...>
 *  - New creation, NEC VR4122 and VR4131 are supported.
 */
#ifndef __VR41XX_PCIU_H
#define __VR41XX_PCIU_H

#include <linux/config.h>
#include <asm/addrspace.h>

#define BIT(x)	(1 << (x))

#define PCIMMAW1REG			KSEG1ADDR(0x0f000c00)
#define PCIMMAW2REG			KSEG1ADDR(0x0f000c04)
#define PCITAW1REG			KSEG1ADDR(0x0f000c08)
#define PCITAW2REG			KSEG1ADDR(0x0f000c0c)
#define PCIMIOAWREG			KSEG1ADDR(0x0f000c10)
#define INTERNAL_BUS_BASE_ADDRESS	0xff000000
#define ADDRESS_MASK			0x000fe000
#define PCI_ACCESS_ENABLE		BIT(12)
#define PCI_ADDRESS_SETTING		0x000000ff

#define PCICONFDREG			KSEG1ADDR(0x0f000c14)
#define PCICONFAREG			KSEG1ADDR(0x0f000c18)
#define PCIMAILREG			KSEG1ADDR(0x0f000c1c)

#define BUSERRADREG			KSEG1ADDR(0x0f000c24)
#define ERROR_ADDRESS			0xfffffffc

#define INTCNTSTAREG			KSEG1ADDR(0x0f000c28)
#define MABTCLR				BIT(31)
#define TRDYCLR				BIT(30)
#define PARCLR				BIT(29)
#define MBCLR				BIT(28)
#define SERRCLR				BIT(27)

#define PCIEXACCREG			KSEG1ADDR(0x0f000c2c)
#define UNLOCK				BIT(1)
#define EAREQ				BIT(0)

#define PCIRECONTREG			KSEG1ADDR(0x0f000c30)
#define RTRYCNT				0x000000ff

#define PCIENREG			KSEG1ADDR(0x0f000c34)
#define CONFIG_DONE			BIT(2)

#define PCICLKSELREG			KSEG1ADDR(0x0f000c38)
#define EQUAL_VTCLOCK			0x00000002
#define HALF_VTCLOCK			0x00000000
#define QUARTER_VTCLOCK			0x00000001

#define PCITRDYVREG			KSEG1ADDR(0x0f000c3c)

#define PCICLKRUNREG			KSEG1ADDR(0x0f000c60)

#define PCIU_CONFIGREGS_BASE		KSEG1ADDR(0x0f000d00)
#define VENDORIDREG			KSEG1ADDR(0x0f000d00)
#define DEVICEIDREG			KSEG1ADDR(0x0f000d00)
#define COMMANDREG			KSEG1ADDR(0x0f000d04)
#define STATUSREG			KSEG1ADDR(0x0f000d04)
#define REVIDREG			KSEG1ADDR(0x0f000d08)
#define CLASSREG			KSEG1ADDR(0x0f000d08)
#define CACHELSREG			KSEG1ADDR(0x0f000d0c)
#define LATTIMEREG			KSEG1ADDR(0x0f000d0c)
#define MAILBAREG			KSEG1ADDR(0x0f000d10)
#define PCIMBA1REG			KSEG1ADDR(0x0f000d14)
#define PCIMBA2REG			KSEG1ADDR(0x0f000d18)
#define INTLINEREG			KSEG1ADDR(0x0f000d3c)
#define INTPINREG			KSEG1ADDR(0x0f000d3c)
#define RETVALREG			KSEG1ADDR(0x0f000d40)
#define PCIAPCNTREG			KSEG1ADDR(0x0f000d40)

#define MPCIINTREG			KSEG1ADDR(0x0f0000b2)

#define MAX_PCI_CLOCK			33333333

#define PCI_CLOCK			0x2000

static inline int pciu_read_config_byte(int where, u8 *val)
{
	u32 data;

	data = readl(PCIU_CONFIGREGS_BASE + where);
	*val = (u8)(data >> ((where & 3) << 3));

	return PCIBIOS_SUCCESSFUL;
}

static inline int pciu_read_config_word(int where, u16 *val)
{
	u32 data;

	if (where & 1)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	data = readl(PCIU_CONFIGREGS_BASE + where);
	*val = (u16)(data >> ((where & 2) << 3));

	return PCIBIOS_SUCCESSFUL;
}

static inline int pciu_read_config_dword(int where, u32 *val)
{
	if (where & 3)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	*val = readl(PCIU_CONFIGREGS_BASE + where);

	return PCIBIOS_SUCCESSFUL;
}

static inline int pciu_write_config_byte(int where, u8 val)
{
	writel(val, PCIU_CONFIGREGS_BASE + where);

	return 0;
}

static inline int pciu_write_config_word(int where, u16 val)
{
	writel(val, PCIU_CONFIGREGS_BASE + where);

	return 0;
}

static inline int pciu_write_config_dword(int where, u32 val)
{
	writel(val, PCIU_CONFIGREGS_BASE + where);

	return 0;
}

#endif /* __VR41XX_PCIU_H */

--- NEW FILE: siu.c ---
/*
 * FILE NAME
 *	arch/mips/vr41xx/vr4122/common/siu.c
 *
 * BRIEF MODULE DESCRIPTION
 *	Serial Interface Unit routines for NEC VR4122 and VR4131.
 *
 * Author: Yoichi Yuasa
 *         yy...@mv... or so...@mv...
 *
 * Copyright 2002 MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
/*
 * Changes:
 *  MontaVista Software Inc. <yy...@mv...> or <so...@mv...>
 *  - New creation, NEC VR4122 and VR4131 are supported.
 */
#include <linux/init.h>
#include <linux/types.h>
#include <linux/serial.h>

#include <asm/io.h>
#include <asm/vr41xx.h>

#include "siu.h"

void vr41xx_siu_ifselect(int interface, int module)
{
	u16 val;

	if (interface == SIU_IRDA) {
		/* Select IrDA */
		switch (module) {
		case IRDA_SHARP:
			val = SIUIRSEL_IRM_SHARP;
			break;
		case IRDA_TEMIC:
			val = SIUIRSEL_IRM_TEMIC;
			break;
		case IRDA_HP:
			val = SIUIRSEL_IRM_HP;
			break;
		}
		val |= SIUIRSEL_SIRSEL;
		writew(val, SIUIRSEL);
	}
	else {
		/* Select RS-232C */
		writew(0, SIUIRSEL);
	}
}

void __init vr41xx_siu_init(int line, int interface, int module)
{
	struct serial_struct s;

	vr41xx_siu_ifselect(interface, module);

	memset(&s, 0, sizeof(s));

	s.line = line;
	s.baud_base = SIU_BASE_BAUD;
	s.irq = SIU_IRQ;
	s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
	s.iomem_base = (unsigned char *)SIURB;
	s.iomem_reg_shift = 0;
	s.io_type = SERIAL_IO_MEM;
	if (early_serial_setup(&s) != 0)
		printk(KERN_ERR "SIU setup failed!\n");

	vr41xx_clock_supply(SIU_CLOCK);
}

void __init vr41xx_dsiu_init(int line)
{
	struct serial_struct s;

	memset(&s, 0, sizeof(s));

	s.line = line;
	s.baud_base = DSIU_BASE_BAUD;
	s.irq = DSIU_IRQ;
	s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
	s.iomem_base = (unsigned char *)DSIURB;
	s.iomem_reg_shift = 0;
	s.io_type = SERIAL_IO_MEM;
	if (early_serial_setup(&s) != 0)
		printk(KERN_ERR "DSIU setup failed!\n");

	vr41xx_clock_supply(DSIU_CLOCK);

	writew(INTDSIU, MDSIUINTREG);
}

--- NEW FILE: siu.h ---
/*
 * FILE NAME
 *	arch/mips/vr41xx/vr4122/common/siu.h
 *
 * BRIEF MODULE DESCRIPTION
 *	Include file for Serial Interface Unit of NEC VR4122 and VR4131.
 *
 * Author: Yoichi Yuasa
 *         yy...@mv... or so...@mv...
 *
 * Copyright 2002 MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
/*
 * Changes:
 *  MontaVista Software Inc. <yy...@mv...> or <so...@mv...>
 *  - New creation, NEC VR4122 and VR4131 are supported.
 */
#ifndef __VR41XX_SIU_H
#define __VR41XX_SIU_H

#include <linux/config.h>
#include <asm/addrspace.h>

#define SIURB			KSEG1ADDR(0x0f000800)
#define SIUTH			KSEG1ADDR(0x0f000800)
#define SIUDLL			KSEG1ADDR(0x0f000800)
#define SIUIE			KSEG1ADDR(0x0f000801)
#define SIUDLM			KSEG1ADDR(0x0f000801)
#define SIUIID			KSEG1ADDR(0x0f000802)
#define SIUFC			KSEG1ADDR(0x0f000802)
#define SIULC			KSEG1ADDR(0x0f000803)
#define SIUMC			KSEG1ADDR(0x0f000804)
#define SIULS			KSEG1ADDR(0x0f000805)
#define SIUMS			KSEG1ADDR(0x0f000806)
#define SIUSC			KSEG1ADDR(0x0f000807)
#define SIUIRSEL		KSEG1ADDR(0x0f000808)
#define SIUIRSEL_SIRSEL		0x01
#define SIUIRSEL_IRUSESEL	0x02
#define SIUIRSEL_IRMSEL		0x0c
#define SIUIRSEL_IRM_SHARP	0x00
#define SIUIRSEL_IRM_TEMIC	0x04
#define SIUIRSEL_IRM_HP		0x08
#define SIUIRSEL_TMICTX		0x10
#define SIUIRSEL_TMICMODE	0x20

#define SIURESET		KSEG1ADDR(0x0f000809)
#define SIUCSEL			KSEG1ADDR(0x0f00080a)

#define SIU_BASE_BAUD		1152000
#define SIU_CLOCK		0x0102
#define SIU_IRQ			17

#define DSIURB			KSEG1ADDR(0x0f000820)
#define DSIUTH			KSEG1ADDR(0x0f000820)
#define DSIUDLL			KSEG1ADDR(0x0f000820)
#define DSIUIE			KSEG1ADDR(0x0f000821)
#define DSIUIE			KSEG1ADDR(0x0f000821)
#define DSIUDLM			KSEG1ADDR(0x0f000821)
#define DSIUIID			KSEG1ADDR(0x0f000822)
#define DSIUFC			KSEG1ADDR(0x0f000822)
#define DSIULC			KSEG1ADDR(0x0f000823)
#define DSIUMC			KSEG1ADDR(0x0f000824)
#define DSIULS			KSEG1ADDR(0x0f000825)
#define DSIUMS			KSEG1ADDR(0x0f000826)
#define DSIUSC			KSEG1ADDR(0x0f000827)

#define MDSIUINTREG		KSEG1ADDR(0x0f000096)
#define INTDSIU			0x0800

#define DSIU_BASE_BAUD		1152000
#define DSIU_CLOCK		0x0802
#define DSIU_IRQ		29

#endif /* __VR41XX_SIU_H */

--- NEW FILE: vrc4173.c ---
/*
 * BRIEF MODULE DESCRIPTION
 *	Setup for NEC VRC4173.
 *
 * Copyright 2001,2002 MontaVista Software Inc.
 * Author: Yoichi Yuasa
 *		yy...@mv... or so...@mv...
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/config.h>

#ifdef CONFIG_PCI
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/module.h>

#include <asm/pci_channel.h>
#include <asm/vr4122/eagle.h>
#include <asm/vrc4173.h>

extern int early_read_config_byte(struct pci_channel *hose, int top_bus, int bus,
                                  int devfn, int offset, u8 *val);
extern int early_read_config_word(struct pci_channel *hose, int top_bus, int bus,
                                  int devfn, int offset, u16 *val);
extern int early_read_config_dword(struct pci_channel *hose, int top_bus, int bus,
                                   int devfn, int offset, u32 *val);
extern int early_write_config_byte(struct pci_channel *hose, int top_bus, int bus,
                                   int devfn, int offset, u8 val);
extern int early_write_config_word(struct pci_channel *hose, int top_bus, int bus,
                                   int devfn, int offset, u16 val);
extern int early_write_config_dword(struct pci_channel *hose, int top_bus, int bus,
                                    int devfn, int offset, u32 val);

struct pci_dev *vrc4173_pci_dev = NULL;
EXPORT_SYMBOL(vrc4173_pci_dev);

unsigned long vrc4173_io_port_base = 0;
EXPORT_SYMBOL(vrc4173_io_port_base);

void __init vrc4173_bcu_init(void)
{
	struct pci_channel *hose;
	int top_bus;
	int current_bus;
	u32 pci_devfn, cmdstat, base;
	u16 vid, did, cmu_mask;

	hose = mips_pci_channels;
	top_bus = 0;
	current_bus = 0;
	for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {

		early_read_config_word(hose, top_bus, current_bus, pci_devfn,
		                       PCI_VENDOR_ID, &vid);
		if (vid != PCI_VENDOR_ID_NEC)
			continue;

		early_read_config_word(hose, top_bus, current_bus, pci_devfn,
		                       PCI_DEVICE_ID, &did);
		if (did != PCI_DEVICE_ID_NEC_VRC4173_BCU)
			continue;

		/*
		 * Initialized NEC VRC4173 Bus Control Unit
		 */
		early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
		                        PCI_COMMAND, &cmdstat);
		early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
		                         PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
					 PCI_COMMAND_MEMORY |
					 PCI_COMMAND_MASTER);
		early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
		                        PCI_LATENCY_TIMER, 0x80);

		early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
		                         PCI_BASE_ADDRESS_0, VR4122_PCI_IO_START);

		early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
		                        PCI_BASE_ADDRESS_0, &base);
		base &= PCI_BASE_ADDRESS_IO_MASK;

		early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
		                        PCI_VRC4173_BUSCNT, VRC4173_BUSCNT_POSTON);

		/* CARDU1 IDSEL = AD12, CARDU2 IDSEL = AD13 */
		early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
		                        PCI_VRC4173_IDSELNUM, 0);

		outw(VRC4173_CMUCLKMSK_MSK48MOSC, base + VRC4173_CMUCLKMSK);
		cmu_mask = inw(base + VRC4173_CMUCLKMSK);
		cmu_mask |= VRC4173_CMUCLKMSK_MSK48MPIN;
		outw(cmu_mask, base + VRC4173_CMUCLKMSK);

		outw(0x000f, base + VRC4173_CMUSRST);
		cmu_mask = inw(base + VRC4173_CMUCLKMSK);
#ifdef CONFIG_USB_OHCI
		cmu_mask |= (VRC4173_CMUCLKMSK_MSK48MUSB | VRC4173_CMUCLKMSK_MSKUSB);
#endif
#ifdef CONFIG_PCMCIA
		cmu_mask |= (VRC4173_CMUCLKMSK_MSKCARD1 | VRC4173_CMUCLKMSK_MSKCARD2);
#endif
#ifdef CONFIG_SOUND
		cmu_mask |= VRC4173_CMUCLKMSK_MSKAC97;
#endif
		outw(cmu_mask, base + VRC4173_CMUCLKMSK);
		cmu_mask = inw(base + VRC4173_CMUCLKMSK);	/* dummy read */
		outw(0x0000, base + VRC4173_CMUSRST);
	}
}

#endif