[Linux-mips-commits]CVS: linux/arch/mips/sibyte/sb1 cache_error.c,1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips/sibyte/sb1

Modified Files:
	cache_error.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: cache_error.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1/cache_error.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- cache_error.c	28 Jan 2002 20:31:57 -0000	1.1
+++ cache_error.c	26 Feb 2002 17:34:15 -0000	1.2
@@ -48,9 +48,10 @@
 asmlinkage void sb1_cache_error(void)
 {
 	unsigned int errctl, cerr_i, cerr_d, cerr_dpa;
-	unsigned int eepc;
+	unsigned long eepc;
+
+	eepc = get_errorepc();
 
-	eepc = read_32bit_cp0_register(CP0_ERROREPC);
 	__asm__ __volatile__ (
 		".set push\n"
 		"#.set mips64\n"
@@ -60,17 +61,19 @@
 		".word 0x4001D801; move %2, $1; # mfc0 %2, $27, 1\n"
 		".word 0x4001D803; move %3, $1; # mfc0 %3, $27, 3\n"
 		".set pop\n"
-		: "=r" (errctl), "=r" (cerr_i), "=r" (cerr_d), "=r" (cerr_dpa));
+		: "=r" (errctl), "=r" (cerr_i),
+		  "=r" (cerr_d), "=r" (cerr_dpa));
 
 	printk("Cache error exception:\n");
-	printk(" cp0_errorepc == %08x\n", eepc);
-	printk(" cp0_errctl   == %08x\n", errctl);
+	printk(" cp0_errorepc == 0x%0lx\n", eepc);
+	printk(" cp0_errctl   == 0x%08x\n", errctl);
+
 	if (errctl & CP0_ERRCTL_DCACHE) {
-		printk(" cp0_cerr_d   == %08x\n", cerr_d);
-		printk(" cp0_cerr_dpa == %08x\n", cerr_dpa);
+		printk(" cp0_cerr_d   == 0x%08x\n", cerr_d);
+		printk(" cp0_cerr_dpa == 0x%08x\n", cerr_dpa);
 	}
 	if (errctl & CP0_ERRCTL_ICACHE) {
-		printk(" cp0_cerr_i   == %08x\n", cerr_i);
+		printk(" cp0_cerr_i   == 0x%08x\n", cerr_i);
 	}
 
 	panic("Can't handle the cache error!");