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[Linux-mips-commits]CVS: linux/arch/mips64/kernel head.S,1.4,1.5 r4k_switch.S,1.1,1.2 scall_o32.S,1.11,1.12 smp.c,1.14,1.15 traps.c,1.13,1.14 unaligned.c,1.4,1.5
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From: James S. <jsi...@us...> - 2002-02-26 17:34:23
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Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips64/kernel
Modified Files:
head.S r4k_switch.S scall_o32.S smp.c traps.c unaligned.c
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff
Index: head.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/head.S,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- head.S 19 Feb 2002 17:50:59 -0000 1.4
+++ head.S 26 Feb 2002 17:34:15 -0000 1.5
@@ -35,13 +35,13 @@
#ifdef CONFIG_SGI_IP27
/*
- * outputs the local nasid into t1.
+ * outputs the local nasid into res. IP27 stuff.
*/
- .macro GET_NASID_ASM
- dli t1, LOCAL_HUB_ADDR(NI_STATUS_REV_ID)
- ld t1, (t1)
- and t1, NSRI_NODEID_MASK
- dsrl t1, NSRI_NODEID_SHFT
+ .macro GET_NASID_ASM res
+ dli \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID)
+ ld \res, (\res)
+ and \res, NSRI_NODEID_MASK
+ dsrl \res, NSRI_NODEID_SHFT
.endm
#endif /* CONFIG_SGI_IP27 */
@@ -97,7 +97,7 @@
xori sp, 0xf
#ifdef CONFIG_SGI_IP27
- GET_NASID_ASM
+ GET_NASID_ASM t1
move t2, t1 # text and data are here
MAPPED_KERNEL_SETUP_TLB
#endif /* IP27 */
@@ -107,25 +107,24 @@
CLI # disable interrupts
la $28, init_task_union # init current pointer
- daddiu t0, $28, KERNEL_STACK_SIZE-32
- sd t0, kernelsp
- dsubu sp, t0, 4*SZREG # init stack pointer
- move t0, $28
+ daddiu sp, $28, KERNEL_STACK_SIZE-32
+ set_saved_sp sp, t0
-#ifdef CONFIG_SMP
- mtc0 t0, CP0_WATCHLO
- dsrl32 t0, t0, 0
- mtc0 t0, CP0_WATCHHI
-#endif
+ dsubu sp, 4*SZREG # init stack pointer
- jal init_arch
+ j init_arch
END(kernel_entry)
#ifdef CONFIG_SMP
+/*
+ * SMP slave cpus entry point. Board specific code for bootstrap calls this
+ * function after setting up the stack and gp registers.
+ */
+NESTED(smp_bootstrap, 16, sp)
#ifdef CONFIG_SGI_IP27
-NESTED(bootstrap, 16, sp)
- GET_NASID_ASM
- li t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + KLDIR_OFF_POINTER + K0BASE
+ GET_NASID_ASM t1
+ li t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \
+ KLDIR_OFF_POINTER + K0BASE
dsll t1, NASID_SHFT
or t0, t0, t1
ld t0, 0(t0) # t0 points to kern_vars struct
@@ -133,40 +132,29 @@
lh t2, KV_RW_NASID_OFFSET(t0)
MAPPED_KERNEL_SETUP_TLB
ARC64_TWIDDLE_PC
- CLI
- mfc0 t0, CP0_STATUS
- li t1, ~(ST0_CU1|ST0_CU2|ST0_CU3)
- and t0, t1
- or t0, (ST0_CU0|ST0_KX|ST0_SX|ST0_FR) # Bogosity: cu0 indicates kernel
- mtc0 t0, CP0_STATUS # thread in copy_thread.
- jal cboot
- END(bootstrap)
-#else
-
-/*
- * SMP slave cpus entry point. Board specific code for bootstrap calls this
- * function after setting up the stack and gp registers.
- */
- LEAF(smp_bootstrap)
- .set push
- .set noreorder
+#endif /* CONFIG_SGI_IP27 */
- mtc0 zero, CP0_WIRED
CLI
- mfc0 t0, CP0_STATUS
- li t1, ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_BEV)
- and t0, t1
- or t0, (ST0_CU0|ST0_FR|ST0_KX|ST0_SX);
- jal start_secondary
+
+ /*
+ * For the moment set ST0_KU so the CPU will not spit fire when
+ * executing 64-bit instructions. The full initialization of the
+ * CPU's status register is done later in per_cpu_trap_init().
+ */
+ mfc0 t0, CP0_STATUS
+ or t0, ST0_KX
mtc0 t0, CP0_STATUS
- .set pop
+
+ set_saved_sp sp, t0
+
+ jal start_secondary # XXX: IP27: cboot
+
END(smp_bootstrap)
-#endif /* CONFIG_SGI_IP27 */
#endif /* CONFIG_SMP */
__FINIT
- .comm kernelsp, 8, 8 # current stackpointer
+ declare_saved_sp
#undef PAGE_SIZE
#define PAGE_SIZE 0x1000
Index: r4k_switch.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/r4k_switch.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- r4k_switch.S 12 Dec 2001 18:33:06 -0000 1.1
+++ r4k_switch.S 26 Feb 2002 17:34:15 -0000 1.2
@@ -42,14 +42,10 @@
*/
move $28, a1
cpu_restore_nonscratch $28
-#ifndef CONFIG_SMP
- daddiu t0, $28, KERNEL_STACK_SIZE-32
- sd t0, kernelsp
-#else
- mtc0 a1, CP0_WATCHLO
- dsrl32 a1, a1, 0
- mtc0 a1, CP0_WATCHHI
-#endif
+
+ daddiu a1, $28, KERNEL_STACK_SIZE-32
+ set_saved_sp a1 t0
+
mfc0 t1, CP0_STATUS /* Do we really need this? */
li a3, 0xff00
and t1, a3
Index: scall_o32.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/scall_o32.S,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- scall_o32.S 2 Jan 2002 19:13:41 -0000 1.11
+++ scall_o32.S 26 Feb 2002 17:34:15 -0000 1.12
@@ -43,6 +43,12 @@
daddiu t1, 4 # skip to next instruction
beqz t0, not_o32_scall
sd t1, PT_EPC(sp)
+#if 0
+ SAVE_ALL
+ move a1, v0
+ PRINT("Scall %ld\n")
+ RESTORE_ALL
+#endif
/* XXX Put both in one cacheline, should save a bit. */
dsll t0, v0, 3 # offset into table
@@ -464,6 +470,19 @@
sys sys_ni_syscall 0
sys sys_gettid 0
sys sys32_readahead 5
+ sys sys_ni_syscall 0 /* reserved for setxattr */
+ sys sys_ni_syscall 0 /* 4225 res. for lsetxattr */
+ sys sys_ni_syscall 0 /* reserved for fsetxattr */
+ sys sys_ni_syscall 0 /* reserved for getxattr */
+ sys sys_ni_syscall 0 /* reserved for lgetxattr */
+ sys sys_ni_syscall 0 /* reserved for fgetxattr */
+ sys sys_ni_syscall 0 /* 4230 res. for listxattr */
+ sys sys_ni_syscall 0 /* reserved for llistxattr */
+ sys sys_ni_syscall 0 /* reserved for flistxattr */
+ sys sys_ni_syscall 0 /* reserved for removexattr */
+ sys sys_ni_syscall 0 /* reserved for lremovexattr */
+ sys sys_ni_syscall 0 /* 4235 res. for fremovexattr */
+
.endm
.macro sys function, nargs
Index: smp.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/smp.c,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -d -r1.14 -r1.15
--- smp.c 19 Feb 2002 17:54:59 -0000 1.14
+++ smp.c 26 Feb 2002 17:34:15 -0000 1.15
@@ -56,6 +56,7 @@
#endif
}
+#ifndef CONFIG_SGI_IP27
/*
* Hook for doing final board-specific setup after the generic smp setup
* is done
@@ -65,27 +66,21 @@
unsigned int cpu = smp_processor_id();
prom_init_secondary();
-
- /* Do stuff that trap_init() did for the first processor */
- clear_cp0_status(ST0_BEV);
- if (mips_cpu.options & MIPS_CPU_DIVEC) {
- set_cp0_cause(CAUSEF_IV);
- }
+ per_cpu_trap_init();
/*
* XXX parity protection should be folded in here when it's converted
* to an option instead of something based on .cputype
*/
- set_context(cpu << 23);
pgd_current[cpu] = init_mm.pgd;
cpu_data[cpu].udelay_val = loops_per_jiffy;
- cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
prom_smp_finish();
printk("Slave cpu booted successfully\n");
CPUMASK_SETB(cpu_online_map, cpu);
atomic_inc(&cpus_booted);
cpu_idle();
}
+#endif /* CONFIG_SGI_IP27 */
void __init smp_commence(void)
{
Index: traps.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/traps.c,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- traps.c 19 Feb 2002 17:43:02 -0000 1.13
+++ traps.c 26 Feb 2002 17:34:15 -0000 1.14
@@ -597,13 +597,24 @@
}
}
-static inline void go_64(void)
+void __init per_cpu_trap_init(void)
{
- unsigned int bits;
+ unsigned int cpu = smp_processor_id();
- bits = ST0_KX|ST0_SX|ST0_UX;
- set_cp0_status(bits);
- printk("Entering 64-bit mode.\n");
+ /* Some firmware leaves the BEV flag set, clear it. */
+ clear_cp0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_BEV);
+ set_cp0_status(ST0_CU0|ST0_FR|ST0_KX|ST0_SX|ST0_UX);
+
+ /*
+ * Some MIPS CPUs have a dedicated interrupt vector which reduces the
+ * interrupt processing overhead. Use it where available.
+ */
+ if (mips_cpu.options & MIPS_CPU_DIVEC)
+ set_cp0_cause(CAUSEF_IV);
+
+ cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
+ set_context(cpu << 23);
+ set_wired(0);
}
void __init trap_init(void)
@@ -617,10 +628,9 @@
unsigned long i;
int dummy;
- /* Some firmware leaves the BEV flag set, clear it. */
- clear_cp0_status(ST0_BEV);
+ per_cpu_trap_init();
- /* Copy the generic exception handler code to it's final destination. */
+ /* Copy the generic exception handlers to their final destination. */
memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
@@ -640,12 +650,7 @@
* Some MIPS CPUs have a dedicated interrupt vector which reduces the
* interrupt processing overhead. Use it where available.
*/
- if (mips_cpu.options & MIPS_CPU_DIVEC) {
- memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
- set_cp0_cause(CAUSEF_IV);
- }
-
- go_64(); /* In memoriam C128 ;-) */
+ memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
if (mips_cpu.options & MIPS_CPU_MCHECK)
set_except_vector(24, handle_mcheck);
Index: unaligned.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/unaligned.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- unaligned.c 2 Jan 2002 19:12:17 -0000 1.4
+++ unaligned.c 26 Feb 2002 17:34:15 -0000 1.5
@@ -361,15 +361,15 @@
return 1;
}
- die_if_kernel("Unhandled kernel unaligned access", regs);
+ die_if_kernel ("Unhandled kernel unaligned access", regs);
send_sig(SIGSEGV, current, 1);
return 0;
sigbus:
- die_if_kernel("Unhandled kernel unaligned access", regs);
+ die_if_kernel ("Unhandled kernel unaligned access", regs);
send_sig(SIGBUS, current, 1);
return 0;
sigill:
- die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs);
+ die_if_kernel ("Unhandled kernel unaligned access or invalid instruction", regs);
send_sig(SIGILL, current, 1);
return 0;
}
@@ -381,6 +381,10 @@
asmlinkage void do_ade(struct pt_regs *regs)
{
unsigned long pc;
+#if 0
+ printk("ade: Cpu%d[%s:%d:%0lx:%0lx]\n", smp_processor_id(),
+ current->comm, current->pid, regs->cp0_badvaddr, regs->cp0_epc);
+#endif
/*
* Did we catch a fault trying to load an instruction?
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