[Linux-mips-commits]CVS: linux/arch/mips/gt64120/momenco_ocelot irq.c,1.3,1.4

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/gt64120/momenco_ocelot
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips/gt64120/momenco_ocelot

Modified Files:
	irq.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/gt64120/momenco_ocelot/irq.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- irq.c	18 Dec 2001 00:34:13 -0000	1.3
+++ irq.c	26 Feb 2002 17:34:14 -0000	1.4
@@ -143,9 +143,8 @@
 
 	/*
 	 * Clear all of the interrupts while we change the able around a bit.
-	 * int-handler is not on bootstrap
 	 */
-	clear_cp0_status(ST0_IM | ST0_BEV);
+	clear_cp0_status(ST0_IM);
 	__cli();
 
 	/* Sets the first-level interrupt dispatcher. */