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[Linux-mips-commits]CVS: linux/arch/mips/au1000/pb1500 init.c,1.1,1.2 pci_fixup.c,1.1,1.2 pci_ops.c,1.1,1.2 setup.c,1.1,1.2
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From: Pete P. <pp...@us...> - 2002-02-15 19:47:31
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Update of /cvsroot/linux-mips/linux/arch/mips/au1000/pb1500
In directory usw-pr-cvs1:/tmp/cvs-serv7382/arch/mips/au1000/pb1500
Modified Files:
init.c pci_fixup.c pci_ops.c setup.c
Log Message:
* removed runtime copyright prints
* Added Pb1500 support (only pcmcia not working at this time) and
modified all drivers as necessary
* renamed most Au1000 registers to match latest databook
* better Au1000 usb hardware fixes for early silicon
* updated mtd driver to support Pb1500 partitioning
Index: init.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1500/init.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- init.c 4 Dec 2001 03:17:17 -0000 1.1
+++ init.c 15 Feb 2002 19:47:26 -0000 1.2
@@ -44,6 +44,11 @@
extern void __init prom_init_cmdline(void);
extern char *prom_getenv(char *envname);
+const char *get_system_type(void)
+{
+ return "Alchemy Pb1500";
+}
+
int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
{
unsigned char *memsize_str;
@@ -54,7 +59,7 @@
prom_envp = envp;
mips_machgroup = MACH_GROUP_ALCHEMY;
- mips_machtype = MACH_PB1000;
+ mips_machtype = MACH_PB1500;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
Index: pci_fixup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1500/pci_fixup.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- pci_fixup.c 4 Dec 2001 03:17:17 -0000 1.1
+++ pci_fixup.c 15 Feb 2002 19:47:26 -0000 1.2
@@ -2,7 +2,7 @@
* BRIEF MODULE DESCRIPTION
* Board specific pci fixups.
*
- * Copyright 2001 MontaVista Software Inc.
+ * Copyright 2001,2002 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* pp...@mv... or so...@mv...
*
@@ -45,6 +45,9 @@
#define DBG(x...)
#endif
+static void fixup_resource(int r_num, struct pci_dev *dev) ;
+static unsigned long virt_io_addr;
+
void __init pcibios_fixup_resources(struct pci_dev *dev)
{
/* will need to fixup IO resources */
@@ -52,6 +55,24 @@
void __init pcibios_fixup(void)
{
+ int i;
+ struct pci_dev *dev;
+
+ virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
+ Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
+
+ if (!virt_io_addr) {
+ printk(KERN_ERR "Unable to ioremap pci space\n");
+ return;
+ }
+
+ pci_for_each_dev(dev) {
+ for (i=0; i < DEVICE_COUNT_RESOURCE; i++) {
+ if (dev->resource[i].start) {
+ fixup_resource(i, dev);
+ }
+ }
+ }
}
void __init pcibios_fixup_irqs(void)
@@ -61,10 +82,38 @@
struct pci_dev *dev;
pci_for_each_dev(dev) {
+ if (dev->bus->number != 0)
+ return;
+
+ dev->irq = 0xff;
+ slot = PCI_SLOT(dev->devfn);
+ switch (slot) {
+ case 12:
+ case 13:
+ dev->irq = AU1000_PCI_INTA;
+ break;
+
+ }
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+ DBG("slot %d irq %d\n", slot, dev->irq);
}
}
unsigned int pcibios_assign_all_busses(void)
{
return 0;
}
+
+static void fixup_resource(int r_num, struct pci_dev *dev)
+{
+ unsigned long start, size, new_start;
+
+ if (dev->resource[r_num].flags & IORESOURCE_IO) {
+ start = dev->resource[r_num].start;
+ size = dev->resource[r_num].end - start;
+ new_start = virt_io_addr + (start - Au1500_PCI_IO_START);
+ dev->resource[r_num].start = new_start;
+ dev->resource[r_num].end = new_start + size;
+ }
+}
+
#endif
Index: pci_ops.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1500/pci_ops.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- pci_ops.c 4 Dec 2001 03:17:17 -0000 1.1
+++ pci_ops.c 15 Feb 2002 19:47:26 -0000 1.2
@@ -2,7 +2,7 @@
* BRIEF MODULE DESCRIPTION
* Pb1500 specific pci support.
*
- * Copyright 2001 MontaVista Software Inc.
+ * Copyright 2001,2002 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* pp...@mv... or so...@mv...
*
@@ -52,40 +52,101 @@
/* TBD */
static struct resource pci_io_resource = {
"pci IO space",
- 0,
- 0,
+ Au1500_PCI_IO_START,
+ Au1500_PCI_IO_END,
IORESOURCE_IO
};
static struct resource pci_mem_resource = {
"pci memory space",
- 0,
- 0,
+ Au1500_PCI_MEM_START,
+ Au1500_PCI_MEM_END,
IORESOURCE_MEM
};
extern struct pci_ops pb1500_pci_ops;
struct pci_channel mips_pci_channels[] = {
- {&pb1500_pci_ops, &pci_io_resource, &pci_mem_resource, 0, 1},
+ {&pb1500_pci_ops, &pci_io_resource, &pci_mem_resource, (10<<3),(16<<3)},
{(struct pci_ops *) NULL, (struct resource *) NULL,
(struct resource *) NULL, (int) NULL, (int) NULL}
};
-
-/*
- * "Bus 2" is really the first and only external slot on the pb1000.
- * We'll call that bus 0, and limit the accesses to that single
- * external slot only. The SDRAM is already initialized in setup.c.
- */
+static unsigned long cfg_addr;
static int config_access(unsigned char access_type, struct pci_dev *dev,
unsigned char where, u32 * data)
{
unsigned char bus = dev->bus->number;
- unsigned char dev_fn = dev->devfn;
- unsigned long config;
+ unsigned int dev_fn = dev->devfn;
+ unsigned int device, function;
+ unsigned long config, status;
+ static int first = 1;
- /* TBD */
+ /*
+ * 7:3 = slot
+ * 2:0 = function
+ */
+
+ if (bus != 0) {
+ *data = 0xffffffff;
+ return -1;
+ }
+
+ if (first) {
+ first = 0;
+ cfg_addr = ioremap(Au1500_EXT_CFG, 0x10000000);
+ if (!cfg_addr)
+ printk (KERN_ERR "PCI unable to ioremap cfg space\n");
+ }
+
+ device = (dev_fn >> 3) & 0x1f;
+ function = dev_fn & 0x7;
+
+#if 1
+ //if (!cfg_addr || (device < 10) || (device > 16)) {
+ if (!cfg_addr || (device > 16)) {
+ *data = 0xffffffff;
+ return -1;
+ }
+#endif
+
+ writel(((0x2000 << 16) | (readl(Au1500_PCI_STATCMD) & 0xffff)),
+ Au1500_PCI_STATCMD);
+ //writel(readl(Au1500_PCI_CFG) & ~PCI_ERROR, Au1500_PCI_CFG);
+ au_sync_udelay(1);
+
+ /* setup the lower 31 bits of the 36 bit address */
+ config = cfg_addr |
+ ((1<<device)<<11) | (function << 8) | (where & ~0x3);
+
+#if 0
+ printk("cfg access: config %x, dev_fn %x, device %x function %x\n",
+ config, dev_fn, device, function);
+#endif
+
+ if (access_type == PCI_ACCESS_WRITE) {
+ writel(*data, config);
+ } else {
+ *data = readl(config);
+ }
+ au_sync_udelay(1);
+
+ DBG("config_access: %d bus %d device %d at %x *data %x, conf %x\n",
+ access_type, bus, device, where, *data, config);
+
+ /* check master abort */
+ status = readl(Au1500_PCI_STATCMD);
+ if (status & (1<<29)) {
+ *data = 0xffffffff;
+ return -1;
+ } else if ((status >> 28) & 0xf) {
+ DBG("PCI ERR detected: status %x\n", status);
+ *data = 0xffffffff;
+ return -1;
+ }
+ else {
+ return PCIBIOS_SUCCESSFUL;
+ }
}
@@ -95,7 +156,9 @@
int ret;
ret = config_access(PCI_ACCESS_READ, dev, where, &data);
- *val = data & 0xff;
+ if (where & 1) data >>= 8;
+ if (where & 2) data >>= 16;
+ *val = data & 0xff;
return ret;
}
@@ -106,7 +169,8 @@
int ret;
ret = config_access(PCI_ACCESS_READ, dev, where, &data);
- *val = data & 0xffff;
+ if (where & 2) data >>= 16;
+ *val = data & 0xffff;
return ret;
}
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1500/setup.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- setup.c 4 Dec 2001 03:17:17 -0000 1.1
+++ setup.c 15 Feb 2002 19:47:26 -0000 1.2
@@ -67,8 +67,11 @@
extern struct ide_ops *ide_ops;
#endif
+#ifdef CONFIG_RTC
+extern struct rtc_ops pb1500_rtc_ops;
+#endif
+
void (*__wbflush) (void);
-extern struct rtc_ops no_rtc_ops;
extern char * __init prom_getcmdline(void);
extern void au1000_restart(char *);
extern void au1000_halt(void);
@@ -90,6 +93,11 @@
argptr = prom_getcmdline();
+ /* NOTE: The memory map is established by YAMON 2.08+ */
+
+ /* Various early Au1500 Errata corrected by this */
+ set_cp0_config(1<<19); /* Config[OD] */
+
#ifdef CONFIG_AU1000_SERIAL_CONSOLE
if ((argptr = strstr(argptr, "console=")) == NULL) {
argptr = prom_getcmdline();
@@ -97,7 +105,11 @@
}
#endif
- rtc_ops = &no_rtc_ops;
+#ifdef CONFIG_SOUND_AU1000
+ strcat(argptr, " au1000_audio=vra");
+ argptr = prom_getcmdline();
+#endif
+
__wbflush = au1500_wbflush;
_machine_restart = au1000_restart;
_machine_halt = au1000_halt;
@@ -105,9 +117,9 @@
// IO/MEM resources.
set_io_port_base(0);
- ioport_resource.start = 0;
+ ioport_resource.start = 0x10000000;
ioport_resource.end = 0xffffffff;
- iomem_resource.start = 0;
+ iomem_resource.start = 0x10000000;
iomem_resource.end = 0xffffffff;
#ifdef CONFIG_BLK_DEV_INITRD
@@ -117,8 +129,8 @@
#endif
// set AUX clock to 12MHz * 8 = 96 MHz
- outl(8, AUX_PLL_CNTRL);
- outl(0, PIN_STATE);
+ writel(8, SYS_AUXPLL);
+ outl(0, SYS_PINSTATERD);
udelay(100);
#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
@@ -134,44 +146,24 @@
#endif
/* zero and disable FREQ2 */
- sys_freqctrl = inl(FQ_CNTRL_1);
+ sys_freqctrl = readl(SYS_FREQCTRL0);
sys_freqctrl &= ~0xFFF00000;
- outl(sys_freqctrl, FQ_CNTRL_1);
+ writel(sys_freqctrl, SYS_FREQCTRL0);
/* zero and disable USBH/USBD clocks */
- sys_clksrc = inl(CLOCK_SOURCE_CNTRL);
+ sys_clksrc = readl(SYS_CLKSRC);
sys_clksrc &= ~0x00007FE0;
- outl(sys_clksrc, CLOCK_SOURCE_CNTRL);
+ writel(sys_clksrc, SYS_CLKSRC);
- sys_freqctrl = inl(FQ_CNTRL_1);
+ sys_freqctrl = readl(SYS_FREQCTRL0);
sys_freqctrl &= ~0xFFF00000;
- sys_clksrc = inl(CLOCK_SOURCE_CNTRL);
+ sys_clksrc = readl(SYS_CLKSRC);
sys_clksrc &= ~0x00007FE0;
-#ifdef CONFIG_AU1000_OHCI_FIX
- /* CPU core freq to 48MHz to slow it way down... */
- outl(4, CPU_PLL_CNTRL);
-
- /*
- * Setup 48MHz FREQ2 from CPUPLL for USB Host
- */
- /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
- sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
- outl(sys_freqctrl, FQ_CNTRL_1);
-
- /* CPU core freq to 384MHz */
- outl(0x20, CPU_PLL_CNTRL);
-
- printk("Au1000: 48MHz OHCI workaround enabled\n");
-
-#else // CONFIG_AU1000_OHCI_FIX
-
// FREQ2 = aux/2 = 48 MHz
sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
- outl(sys_freqctrl, FQ_CNTRL_1);
-
-#endif // CONFIG_AU1000_OHCI_FIX
+ writel(sys_freqctrl, SYS_FREQCTRL0);
/*
* Route 48MHz FREQ2 into USB Host and/or Device
@@ -182,65 +174,34 @@
#ifdef CONFIG_AU1000_USB_DEVICE
sys_clksrc |= ((4<<7) | (0<<6) | (0<<5));
#endif
- outl(sys_clksrc, CLOCK_SOURCE_CNTRL);
+ writel(sys_clksrc, SYS_CLKSRC);
-#ifdef CONFIG_USB_OHCI
- // enable host controller and wait for reset done
- outl(0x08, USB_HOST_CONFIG);
- udelay(1000);
- outl(0x0c, USB_HOST_CONFIG);
- udelay(1000);
- while (!(inl(USB_HOST_CONFIG) & 0x10))
- ;
-#endif
-
- // configure pins GPIO[14:9] as GPIO
- pin_func = inl(PIN_FUNCTION) & (u32)(~0x8080);
+ pin_func = readl(SYS_PINFUNC) & (u32)(~0x8000);
#ifndef CONFIG_AU1000_USB_DEVICE
// 2nd USB port is USB host
pin_func |= 0x8000;
#endif
- outl(pin_func, PIN_FUNCTION);
- outl(0x2800, TSTATE_STATE_SET);
- outl(0x0030, OUTPUT_STATE_CLEAR);
+ writel(pin_func, SYS_PINFUNC);
#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
- // make gpio 15 an input (for interrupt line)
- pin_func = inl(PIN_FUNCTION) & (u32)(~0x100);
- // we don't need I2S, so make it available for GPIO[31:29]
- pin_func |= (1<<5);
- outl(pin_func, PIN_FUNCTION);
- outl(0x8000, TSTATE_STATE_SET);
+#ifdef CONFIG_USB_OHCI
+ // enable host controller and wait for reset done
+ writel(0x08, USB_HOST_CONFIG);
+ udelay(1000);
+ writel(0x0c, USB_HOST_CONFIG);
+ udelay(1000);
+ readl(USB_HOST_CONFIG);
+ while (!(readl(USB_HOST_CONFIG) & 0x10))
+ ;
+ readl(USB_HOST_CONFIG);
+#endif
#ifdef CONFIG_FB
conswitchp = &dummy_con;
#endif
- static_cfg0 = inl(STATIC_CONFIG_0) & (u32)(~0xc00);
- outl(static_cfg0, STATIC_CONFIG_0);
-
- // configure RCE2* for LCD
- outl(0x00000004, STATIC_CONFIG_2);
-
- // STATIC_TIMING_2
- //outl(0x08061908, STATIC_TIMING_2);
- outl(0x09000000, STATIC_TIMING_2);
-
- // Set 32-bit base address decoding for RCE2*
- outl(0x10003ff0, STATIC_ADDRESS_2);
-
- // PCI CPLD setup
- // expand CE0 to cover PCI
- outl(0x11803e40, STATIC_ADDRESS_1);
-
- // burst visibility on
- outl(inl(STATIC_CONFIG_0) | 0x1000, STATIC_CONFIG_0);
-
- outl(0x83, STATIC_CONFIG_1); // ewait enabled, flash timing
- outl(0x33030a10, STATIC_TIMING_1); // slower timing for FPGA
-
#ifdef CONFIG_FB_E1356
if ((argptr = strstr(argptr, "video=")) == NULL) {
argptr = prom_getcmdline();
@@ -248,35 +209,48 @@
}
#endif // CONFIG_FB_E1356
-
#ifndef CONFIG_SERIAL_NONSTANDARD
/* don't touch the default serial console */
- outl(0, UART0_ADDR + UART_CLK);
+ writel(0, UART0_ADDR + UART_CLK);
#endif
- outl(0, UART1_ADDR + UART_CLK);
- outl(0, UART2_ADDR + UART_CLK);
- outl(0, UART3_ADDR + UART_CLK);
+ writel(0, UART3_ADDR + UART_CLK);
#ifdef CONFIG_BLK_DEV_IDE
- {
- argptr = prom_getcmdline();
- strcat(argptr, " ide0=noprobe");
- }
ide_ops = &std_ide_ops;
#endif
- // setup irda clocks
- // aux clock, divide by 2, clock from 2/4 divider
- writel(readl(CLOCK_SOURCE_CNTRL) | 0x7, CLOCK_SOURCE_CNTRL);
- pin_func = inl(PIN_FUNCTION) & (u32)(~(1<<2)); // clear IRTXD
- outl(pin_func, PIN_FUNCTION);
+#ifdef CONFIG_PCI
+ // Setup PCI bus controller
+ writel(0, Au1500_PCI_CMEM);
+ writel(0x00003fff, Au1500_CFG_BASE);
+ writel(0xf, Au1500_PCI_CFG);
+ writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
+ writel(0, Au1500_PCI_MWBASE_REV_CCL);
+ writel(0x02a00356, Au1500_PCI_STATCMD);
+ writel(0x00003c04, Au1500_PCI_HDRTYPE);
+ writel(0x00000008, Au1500_PCI_MBAR);
+ au_sync();
+#endif
- while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_E0S);
- outl(PC_CNTRL_E0 | PC_CNTRL_EN0, PC_COUNTER_CNTRL);
+ while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
+ writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
au_sync();
- while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_T0S);
- outl(0, PC0_TRIM);
+ while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
+ outl(0, SYS_TOYTRIM);
- printk("Alchemy Semi Pb1500 Board\n");
- printk("Au1500/Pb1500 port (C) 2001 MontaVista Software, Inc. (so...@mv...)\n");
+ /* Enable BCLK switching */
+ writel(0x00000060, 0xb190003c);
+
+#ifdef CONFIG_RTC
+ rtc_ops = &pb1500_rtc_ops;
+ // Enable the RTC if not already enabled
+ if (!(readb(0xac000028) & 0x20)) {
+ writeb(readb(0xac000028) | 0x20, 0xac000028);
+ }
+ // Put the clock in BCD mode
+ if (readb(0xac00002C) & 0x4) { /* reg B */
+ writeb(readb(0xac00002c) & ~0x4, 0xac00002c);
+ au_sync();
+ }
+#endif
}
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