[Linux-mips-commits]CVS: linux/arch/mips/au1000/pb1000 setup.c,1.17,1.18

[Pete P. <pp...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000
In directory usw-pr-cvs1:/tmp/cvs-serv7382/arch/mips/au1000/pb1000

Modified Files:
	setup.c 
Log Message:

* removed runtime copyright prints
* Added Pb1500 support (only pcmcia not working at this time) and
  modified all drivers as necessary
* renamed most Au1000 registers to match latest databook
* better Au1000 usb hardware fixes for early silicon
* updated mtd driver to support Pb1500 partitioning



Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000/setup.c,v
retrieving revision 1.17
retrieving revision 1.18
diff -u -d -r1.17 -r1.18
--- setup.c	2 Jan 2002 19:12:16 -0000	1.17
+++ setup.c	15 Feb 2002 19:47:25 -0000	1.18
@@ -82,18 +82,18 @@
 	__asm__ volatile ("sync");
 }
 
-void __init bus_error_init(void)
-{
-}
-
 void __init au1000_setup(void)
 {
 	char *argptr;
 	u32 pin_func, static_cfg0;
 	u32 sys_freqctrl, sys_clksrc;
+	u32 prid = read_32bit_cp0_register(CP0_PRID);
 	
 	argptr = prom_getcmdline();
 
+	/* Various early Au1000 Errata corrected by this */
+	set_cp0_config(1<<19); /* Config[OD] */
+
 #ifdef CONFIG_AU1000_SERIAL_CONSOLE
 	if ((argptr = strstr(argptr, "console=")) == NULL) {
 		argptr = prom_getcmdline();
@@ -109,9 +109,9 @@
 
 	// IO/MEM resources. 
 	set_io_port_base(0);
-	ioport_resource.start = 0;
+	ioport_resource.start = 0x10000000;
 	ioport_resource.end = 0xffffffff;
-	iomem_resource.start = 0;
+	iomem_resource.start = 0x10000000;
 	iomem_resource.end = 0xffffffff;
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -121,8 +121,8 @@
 #endif
 
 	// set AUX clock to 12MHz * 8 = 96 MHz
-	outl(8, AUX_PLL_CNTRL);
-	outl(0, PIN_STATE);
+	outl(8, SYS_AUXPLL);
+	outl(0, SYS_PINSTATERD);
 	udelay(100);
 
 #if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
@@ -138,44 +138,48 @@
 #endif
 
 	/* zero and disable FREQ2 */
-	sys_freqctrl = inl(FQ_CNTRL_1);
+	sys_freqctrl = inl(SYS_FREQCTRL0);
 	sys_freqctrl &= ~0xFFF00000;
-	outl(sys_freqctrl, FQ_CNTRL_1);
+	outl(sys_freqctrl, SYS_FREQCTRL0);
 
 	/* zero and disable USBH/USBD clocks */
-	sys_clksrc = inl(CLOCK_SOURCE_CNTRL);
+	sys_clksrc = inl(SYS_CLKSRC);
 	sys_clksrc &= ~0x00007FE0;
-	outl(sys_clksrc, CLOCK_SOURCE_CNTRL);
+	outl(sys_clksrc, SYS_CLKSRC);
 
-	sys_freqctrl = inl(FQ_CNTRL_1);
+	sys_freqctrl = inl(SYS_FREQCTRL0);
 	sys_freqctrl &= ~0xFFF00000;
 
-	sys_clksrc = inl(CLOCK_SOURCE_CNTRL);
+	sys_clksrc = inl(SYS_CLKSRC);
 	sys_clksrc &= ~0x00007FE0;
 
-#ifdef CONFIG_AU1000_OHCI_FIX
+	switch (prid & 0x000000FF)
+	{
+	case 0x00: /* DA */
+	case 0x01: /* HA */
+	case 0x02: /* HB */
 	/* CPU core freq to 48MHz to slow it way down... */
-	outl(4, CPU_PLL_CNTRL);
+	outl(4, SYS_CPUPLL);
 
 	/*
 	 * Setup 48MHz FREQ2 from CPUPLL for USB Host
 	 */
 	/* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
 	sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
-	outl(sys_freqctrl, FQ_CNTRL_1);
+	outl(sys_freqctrl, SYS_FREQCTRL0);
 
 	/* CPU core freq to 384MHz */
-	outl(0x20, CPU_PLL_CNTRL);
+	outl(0x20, SYS_CPUPLL);
 
 	printk("Au1000: 48MHz OHCI workaround enabled\n");
+		break;
 
-#else   // CONFIG_AU1000_OHCI_FIX
-
+	default:  /* HC and newer */
 	// FREQ2 = aux/2 = 48 MHz
 	sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
-	outl(sys_freqctrl, FQ_CNTRL_1);
-
-#endif  // CONFIG_AU1000_OHCI_FIX
+	outl(sys_freqctrl, SYS_FREQCTRL0);
+		break;
+	}
 
 	/*
 	 * Route 48MHz FREQ2 into USB Host and/or Device
@@ -186,64 +190,64 @@
 #ifdef CONFIG_AU1000_USB_DEVICE
 	sys_clksrc |= ((4<<7) | (0<<6) | (0<<5));
 #endif
-	outl(sys_clksrc, CLOCK_SOURCE_CNTRL);
+	outl(sys_clksrc, SYS_CLKSRC);
 
 #ifdef CONFIG_USB_OHCI
 	// enable host controller and wait for reset done
 	outl(0x08, USB_HOST_CONFIG);
 	udelay(1000);
-	outl(0x0c, USB_HOST_CONFIG);
+	outl(0x0E, USB_HOST_CONFIG);
 	udelay(1000);
+	inl(USB_HOST_CONFIG); // throw away first read
 	while (!(inl(USB_HOST_CONFIG) & 0x10))
-	    ;
+		inl(USB_HOST_CONFIG);
 #endif
 	
 	// configure pins GPIO[14:9] as GPIO
-	pin_func = inl(PIN_FUNCTION) & (u32)(~0x8080);
+	pin_func = inl(SYS_PINFUNC) & (u32)(~0x8080);
 
 #ifndef CONFIG_AU1000_USB_DEVICE
 	// 2nd USB port is USB host
 	pin_func |= 0x8000;
 #endif
-	outl(pin_func, PIN_FUNCTION);
-	outl(0x2800, TSTATE_STATE_SET);
-	outl(0x0030, OUTPUT_STATE_CLEAR);
+	outl(pin_func, SYS_PINFUNC);
+	outl(0x2800, SYS_TRIOUTCLR);
+	outl(0x0030, SYS_OUTPUTCLR);
 #endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
 
 	// make gpio 15 an input (for interrupt line) 
-	pin_func = inl(PIN_FUNCTION) & (u32)(~0x100);
+	pin_func = inl(SYS_PINFUNC) & (u32)(~0x100);
 	// we don't need I2S, so make it available for GPIO[31:29] 
 	pin_func |= (1<<5);
-	outl(pin_func, PIN_FUNCTION);
+	outl(pin_func, SYS_PINFUNC);
 
-	outl(0x8000, TSTATE_STATE_SET);
+	outl(0x8000, SYS_TRIOUTCLR);
 	
 #ifdef CONFIG_FB
 	conswitchp = &dummy_con;
 #endif
 
-	static_cfg0 = inl(STATIC_CONFIG_0) & (u32)(~0xc00);
-	outl(static_cfg0, STATIC_CONFIG_0);
+	static_cfg0 = inl(MEM_STCFG0) & (u32)(~0xc00);
+	outl(static_cfg0, MEM_STCFG0);
 
 	// configure RCE2* for LCD
-	outl(0x00000004, STATIC_CONFIG_2);
+	outl(0x00000004, MEM_STCFG2);
 
-	// STATIC_TIMING_2
-	//outl(0x08061908, STATIC_TIMING_2);
-	outl(0x09000000, STATIC_TIMING_2);
+	// MEM_STTIME2
+	outl(0x09000000, MEM_STTIME2);
 
 	// Set 32-bit base address decoding for RCE2*
-	outl(0x10003ff0, STATIC_ADDRESS_2);
+	outl(0x10003ff0, MEM_STADDR2);
 
 	// PCI CPLD setup
 	// expand CE0 to cover PCI
-	outl(0x11803e40, STATIC_ADDRESS_1);
+	outl(0x11803e40, MEM_STADDR1);
 
 	// burst visibility on 
-	outl(inl(STATIC_CONFIG_0) | 0x1000, STATIC_CONFIG_0);
+	outl(inl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
 
-	outl(0x83, STATIC_CONFIG_1);         // ewait enabled, flash timing
-	outl(0x33030a10, STATIC_TIMING_1);   // slower timing for FPGA
+	outl(0x83, MEM_STCFG1);         // ewait enabled, flash timing
+	outl(0x33030a10, MEM_STTIME1);   // slower timing for FPGA
 
 #ifdef CONFIG_FB_E1356
 	if ((argptr = strstr(argptr, "video=")) == NULL) {
@@ -278,16 +282,26 @@
 
 	// setup irda clocks
 	// aux clock, divide by 2, clock from 2/4 divider
-	writel(readl(CLOCK_SOURCE_CNTRL) | 0x7, CLOCK_SOURCE_CNTRL);
-	pin_func = inl(PIN_FUNCTION) & (u32)(~(1<<2)); // clear IRTXD
-	outl(pin_func, PIN_FUNCTION);
+	writel(readl(SYS_CLKSRC) | 0x7, SYS_CLKSRC);
+	pin_func = inl(SYS_PINFUNC) & (u32)(~(1<<2)); // clear IRTXD
+	outl(pin_func, SYS_PINFUNC);
 
-	while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_E0S);
-	outl(PC_CNTRL_E0 | PC_CNTRL_EN0, PC_COUNTER_CNTRL);
+	while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
+	outl(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
 	au_sync();
-	while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_T0S);
-	outl(0, PC0_TRIM);
+	while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
+	outl(0, SYS_TOYTRIM);
 
-	printk("Alchemy Semi Pb1000 Board\n");
-	printk("Au1000/Pb1000 port (C) 2001 MontaVista Software, Inc. (so...@mv...)\n");
+	/* Enable Au1000 BCLK switching - note: sed1356 must not use
+	 * its BCLK (Au1000 LCLK) for any timings */
+	switch (prid & 0x000000FF)
+	{
+	case 0x00: /* DA */
+	case 0x01: /* HA */
+	case 0x02: /* HB */
+		break;
+	default:  /* HC and newer */
+		outl(0x00000060, 0xb190003c);
+		break;
+	}
 }