From: James S. <jsi...@us...> - 2002-02-12 18:05:31
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Update of /cvsroot/linux-mips/linux/include/asm-mips64 In directory usw-pr-cvs1:/tmp/cvs-serv4009 Modified Files: pgtable.h Log Message: Reformat. Index: pgtable.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/pgtable.h,v retrieving revision 1.9 retrieving revision 1.10 diff -u -d -r1.9 -r1.10 --- pgtable.h 5 Feb 2002 17:34:13 -0000 1.9 +++ pgtable.h 12 Feb 2002 18:05:27 -0000 1.10 @@ -50,21 +50,7 @@ #define __flush_cache_all() ___flush_cache_all() #define flush_dcache_page(page) do { } while (0) -#ifndef CONFIG_CPU_R10000 -#define flush_cache_mm(mm) _flush_cache_mm(mm) -#define flush_cache_range(mm,start,end) _flush_cache_range(mm,start,end) -#define flush_cache_page(vma,page) _flush_cache_page(vma, page) -#define flush_page_to_ram(page) _flush_page_to_ram(page) - -#define flush_icache_range(start, end) _flush_cache_l1() - -#define flush_icache_page(vma, page) \ -do { \ - unsigned long addr; \ - addr = (unsigned long) page_address(page); \ - _flush_cache_page(vma, addr); \ -} while (0) -#else /* !CONFIG_CPU_R10000 */ +#ifdef CONFIG_CPU_R10000 /* * Since the r10k handles VCEs in hardware, most of the flush cache * routines are not needed. Only the icache on a processor is not @@ -85,6 +71,22 @@ if ((vma)->vm_flags & VM_EXEC) \ andes_flush_icache_page(page_address(page)); \ } while (0) + +#else + +#define flush_cache_mm(mm) _flush_cache_mm(mm) +#define flush_cache_range(mm,start,end) _flush_cache_range(mm,start,end) +#define flush_cache_page(vma,page) _flush_cache_page(vma, page) +#define flush_page_to_ram(page) _flush_page_to_ram(page) + +#define flush_icache_range(start, end) _flush_cache_l1() + +#define flush_icache_page(vma, page) \ +do { \ + unsigned long addr; \ + addr = (unsigned long) page_address(page); \ + _flush_cache_page(vma, addr); \ +} while (0) #endif /* !CONFIG_CPU_R10000 */ #define flush_cache_sigtramp(addr) _flush_cache_sigtramp(addr) |