[Linux-mips-commits]CVS: linux/arch/mips/mm c-mips32.c,1.3,1.4 c-sb1.c,1.10,1.11 tlb-r3k.c,1.6,1.7 tlb-r4k.c,1.9,1.10 tlb-sb1.c,1.5,1.6

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv26521

Modified Files:
	c-mips32.c c-sb1.c tlb-r3k.c tlb-r4k.c tlb-sb1.c 
Log Message:
Sync to OSS

Index: c-mips32.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-mips32.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- c-mips32.c	2001/11/30 18:34:09	1.3
+++ c-mips32.c	2002/01/28 23:15:25	1.4
@@ -649,27 +649,6 @@
 	setup_noscache_funcs();
 }
 
-static void __init probe_tlb(unsigned long config)
-{
-        unsigned long config1;
-
-        if (!(config & (1 << 31))) {
-	        /* 
-		 * Not a MIPS32 complainant CPU. 
-		 * Config 1 register not supported, we assume R4k style.
-		 */  
-	        mips_cpu.tlbsize = 48;
-	} else {
-	        config1 = read_mips32_cp0_config1();
-		if (!((config >> 7) & 3))
-		        panic("No MMU present");
-		else
-		        mips_cpu.tlbsize = ((config1 >> 25) & 0x3f) + 1;
-	}	
-
-	printk("Number of TLB entries %d.\n", mips_cpu.tlbsize);
-}
-
 void __init ld_mmu_mips32(void)
 {
 	unsigned long config = read_32bit_cp0_register(CP0_CONFIG);
@@ -683,7 +662,6 @@
 	probe_icache(config);
 	probe_dcache(config);
 	setup_scache(config);
-	probe_tlb(config);
 
 	_flush_cache_sigtramp = mips32_flush_cache_sigtramp;
 	_flush_icache_range = mips32_flush_icache_range;	/* Ouch */

Index: c-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-sb1.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- c-sb1.c	2001/12/11 18:40:07	1.10
+++ c-sb1.c	2002/01/28 23:15:25	1.11
@@ -257,6 +257,8 @@
  * If there's no context yet, or the page isn't executable, no icache flush
  * is needed
  */
+void sb1_flush_icache_all(void);
+
 static void sb1_flush_icache_page(struct vm_area_struct *vma, struct page *page)
 {
 	unsigned long addr;
@@ -265,14 +267,7 @@
 		return;
 	}
 
-	addr = (unsigned long)page_address(page);
-	/*
-	 * XXXKW addr is a Kseg0 address, whereas hidden higher up the call
-	 * stack, we may really need to flush a Useg address.  Our Icache is
-	 * virtually tagged, which means we have to be super conservative.
-	 *  See comments in sb1_flush_icache_rage.
-	 */
-	sb1_flush_icache_range(addr, addr + PAGE_SIZE);
+	sb1_flush_icache_all();
 }
 
 static inline void protected_flush_icache_line(unsigned long addr)

Index: tlb-r3k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-r3k.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- tlb-r3k.c	2001/12/11 18:17:25	1.6
+++ tlb-r3k.c	2002/01/28 23:15:25	1.7
@@ -118,7 +118,7 @@
 
 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 {
-	if (vma->vm_mm->context != 0) {
+	if (!vma || vma->vm_mm->context != 0) {
 		unsigned long flags;
 		int oldpid, newpid, idx;
 

Index: tlb-r4k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-r4k.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- tlb-r4k.c	2002/01/28 18:38:34	1.9
+++ tlb-r4k.c	2002/01/28 23:15:25	1.10
@@ -338,29 +338,19 @@
 	unsigned int prid, config1;
 
 	prid = read_32bit_cp0_register(CP0_PRID) & 0xff00;
-	switch (prid) {
-	case PRID_IMP_RM7000:
-	case PRID_IMP_RC32334:
-	case PRID_IMP_RC32355:
+	if (prid == PRID_IMP_RM7000 || !(config & (1 << 31)))
 		/* 
-		 * Not a MIPS32 compliant CPU.  Config 1 register not
+		 * Not a MIPS32 complianant CPU.  Config 1 register not
 		 * supported, we assume R4k style.  Cpu probing already figured
 		 * out the number of tlb entries.
 		 */  
 		return;
-	default:
-		/* config1 register available? */
-		if (!(config & (1 << 31)))
-			return;
-	}
-	
+
 	config1 = read_mips32_cp0_config1();
 	if (!((config >> 7) & 3))
 		panic("No MMU present");
 	else
 		mips_cpu.tlbsize = ((config1 >> 25) & 0x3f) + 1;
-
-	printk("Number of TLB entries %d.\n", mips_cpu.tlbsize);
 }
 
 void __init r4k_tlb_init(void)
@@ -378,7 +368,6 @@
 	set_pagemask(PM_4K);
 	write_32bit_cp0_register(CP0_WIRED, 0);
 	temp_tlb_entry = mips_cpu.tlbsize - 1;
-	printk("TLB has %d entries.\n", mips_cpu.tlbsize);
 	local_flush_tlb_all();
 
 	if ((mips_cpu.options & MIPS_CPU_4KEX)

Index: tlb-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-sb1.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- tlb-sb1.c	2001/12/02 19:05:29	1.5
+++ tlb-sb1.c	2002/01/28 23:15:25	1.6
@@ -171,7 +171,7 @@
 			}
 			set_entryhi(oldpid);
 		} else {
-			get_new_mmu_context(mm, smp_processor_id());
+			get_new_mmu_context(mm, cpu);
 			if (mm == current->active_mm)
 				set_entryhi(CPU_CONTEXT(cpu, mm) & 0xff);
 		}
@@ -182,14 +182,17 @@
 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 {
 	unsigned long flags;
-	__save_and_cli(flags);
+
 #ifdef CONFIG_SMP
 	/*
-	 * This variable is eliminated from CPU_CONTEXT() if SMP isn't defined, so
-	 * conditional it to get rid of silly "unused variable" compiler complaints
-	*/
+	 * This variable is eliminated from CPU_CONTEXT() if SMP isn't defined,
+	 * so conditional it to get rid of silly "unused variable" compiler
+	 * complaints
+	 */
 	int cpu = smp_processor_id();
 #endif
+
+	__save_and_cli(flags);
 	if (CPU_CONTEXT(cpu, vma->vm_mm) != 0) {
 		int oldpid, newpid, idx;
 #ifdef DEBUG_TLB