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[Linux-mips-commits]CVS: linux/arch/mips/sibyte/sb1 cache_error.c,NONE,1.1 Makefile,1.2,1.3 cache_err_handler.S,1.2,1.3
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From: James S. <jsi...@us...> - 2002-01-28 20:32:30
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Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1
In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips/sibyte/sb1
Modified Files:
Makefile cache_err_handler.S
Added Files:
cache_error.c
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.
--- NEW FILE: cache_error.c ---
/*
* Copyright (C) 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/kernel.h>
#include <asm/mipsregs.h>
/* SB1 definitions */
#define CP0_ERRCTL_RECOVERABLE (1 << 31)
#define CP0_ERRCTL_DCACHE (1 << 30)
#define CP0_ERRCTL_ICACHE (1 << 29)
#define CP0_ERRCTL_MULTIBUS (1 << 23)
#define CP0_ERRCTL_MC_TLB (1 << 15)
#define CP0_ERRCTL_MC_TIMEOUT (1 << 14)
#define CP0_CERRI_TAG_PARITY (1 << 29)
#define CP0_CERRI_DATA_PARITY (1 << 28)
#define CP0_CERRI_EXTERNAL (1 << 26)
#define CP0_CERRI_CACHE_IDX (0xff << 5)
#define CP0_CERRD_MULTIPLE (1 << 31)
#define CP0_CERRD_TAG_STATE (1 << 30)
#define CP0_CERRD_TAG_ADDRESS (1 << 29)
#define CP0_CERRD_DATA_SBE (1 << 28)
#define CP0_CERRD_DATA_DBE (1 << 27)
#define CP0_CERRD_EXTERNAL (1 << 26)
#define CP0_CERRD_LOAD (1 << 25)
#define CP0_CERRD_STORE (1 << 24)
#define CP0_CERRD_FILLWB (1 << 23)
#define CP0_CERRD_COHERENCY (1 << 22)
#define CP0_CERRD_DUPTAG (1 << 21)
#define CP0_CERRD_CACHE_IDX (0xff << 5)
asmlinkage void sb1_cache_error(void)
{
unsigned int errctl, cerr_i, cerr_d, cerr_dpa;
unsigned int eepc;
eepc = read_32bit_cp0_register(CP0_ERROREPC);
__asm__ __volatile__ (
".set push\n"
"#.set mips64\n"
".set mips4\n"
".word 0x4001D000; move %0, $1; # mfc0 %0, $26, 0\n"
".word 0x4001D800; move %1, $1; # mfc0 %1, $27, 0\n"
".word 0x4001D801; move %2, $1; # mfc0 %2, $27, 1\n"
".word 0x4001D803; move %3, $1; # mfc0 %3, $27, 3\n"
".set pop\n"
: "=r" (errctl), "=r" (cerr_i), "=r" (cerr_d), "=r" (cerr_dpa));
printk("Cache error exception:\n");
printk(" cp0_errorepc == %08x\n", eepc);
printk(" cp0_errctl == %08x\n", errctl);
if (errctl & CP0_ERRCTL_DCACHE) {
printk(" cp0_cerr_d == %08x\n", cerr_d);
printk(" cp0_cerr_dpa == %08x\n", cerr_dpa);
}
if (errctl & CP0_ERRCTL_ICACHE) {
printk(" cp0_cerr_i == %08x\n", cerr_i);
}
panic("Can't handle the cache error!");
}
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1/Makefile,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- Makefile 2001/11/29 17:18:37 1.2
+++ Makefile 2002/01/28 20:31:57 1.3
@@ -5,6 +5,6 @@
L_TARGET = sb1kern.a
-obj-$(CONFIG_SB1_CACHE_ERROR) += cache_err_handler.o
+obj-$(CONFIG_SB1_CACHE_ERROR) += cache_err_handler.o cache_error.o
include $(TOPDIR)/Rules.make
Index: cache_err_handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1/cache_err_handler.S,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- cache_err_handler.S 2002/01/04 18:04:53 1.2
+++ cache_err_handler.S 2002/01/28 20:31:57 1.3
@@ -16,59 +16,70 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
-#include <linux/config.h>
-#include <linux/threads.h>
-
#include <asm/asm.h>
-#include <asm/cacheops.h>
-#include <asm/current.h>
-#include <asm/offset.h>
-#include <asm/processor.h>
#include <asm/regdef.h>
-#include <asm/cachectl.h>
#include <asm/mipsregs.h>
-#include <asm/stackframe.h>
.text
- /* Special Cache Error handler for SB1 for now*/
+ /* Special Cache Error handler for SB1 for now */
LEAF(except_vec2_sb1)
.set noat
- .set mips0
+ .set mips0
/*
- * This is a very bad place to be. Our cache error
- * detection has triggered. If we have write-back data
- * in the cache, we may not be able to recover. As a
- * first-order desperate measure, turn off KSEG0 cacheing.
+ * This is a very bad place to be. Our cache error detection has
+ * triggered. If we have write-back data in the cache, we may not be
+ * able to recover. As a first-order desperate measure, turn off KSEG0
+ * cacheing.
*/
- .set push
- .set mips64
- .set reorder
- # look for signature of spurious CErr
- mfc0 k1,$26,0
- lui k0,0x4000
- bne k0,k1,real_cerr
- mfc0 k1,$27,1
- lui k0,0xffe0
- and k1,k0,k1
- lui k0,0x0200
- bne k0,k1,real_cerr
- # clear/unlock the registers
- mtc0 zero,$26,0
- mtc0 zero,$27,1
- eret
+ .set push
+ #.set mips64
+ .set mips4
+ .set reorder
+ # look for signature of spurious CErr
+ mfc0 k1, $26 # mfc0 k1, $26, 0
+ # check if error was recoverable
+ # XXXKW - count them
+ bltz k1,leave_cerr
+ nop
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
+ # look for signature of spurious CErr
+ lui k0, 0x4000
+ bne k0, k1, real_cerr
+ .word 0x401Bd801 # mfc0 k1, $27, 1
+ lui k0, 0xffe0
+ and k1, k0, k1
+ lui k0, 0x0200
+ bne k0, k1, real_cerr
+ nop
+#else
+ j real_cerr
+ nop
+#endif
+ # XXXKW - count spurious errors
+leave_cerr:
+ # clear/unlock the registers
+ mtc0 zero, $26 # mtc0 zero, $26, 0
+ mtc0 zero, $27 # mtc0 zero, $27, 0
+ .word 0x4080d801 # mtc0 zero, $27, 1
+ .word 0x4080d803 # mtc0 zero, $27, 3
+ eret
- # XXXXPK - this is a real error. set the LEDs and spin for now
real_cerr:
- lui k0,0xb00A
- li k1,'C'
- sb k1,56(k0)
- li k1,'E'
- sb k1,48(k0)
- li k1,'R'
- sb k1,40(k0)
- li k1,'R'
- sb k1,32(k0)
-2:
- b 2b
- .set pop
+ mfc0 k0,CP0_CONFIG
+ li k1,~CONF_CM_CMASK
+ and k0,k0,k1
+ ori k0,k0,CONF_CM_UNCACHED
+ mtc0 k0,CP0_CONFIG
+ /* Give it a few cycles to sink in... */
+ sll zero, zero, 0x1 # ssnop
+ sll zero, zero, 0x1 # ssnop
+ sll zero, zero, 0x1 # ssnop
+ sll zero, zero, 0x1 # ssnop
+ sll zero, zero, 0x1 # ssnop
+ sll zero, zero, 0x1 # ssnop
+
+ j sb1_cache_error
+ nop
+
+ .set pop
END(except_vec2_sb1)
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