[Linux-mips-commits]CVS: linux/arch/mips/sibyte/sb1250 Makefile,1.4,1.5 irq_handler.S,1.4,1.5

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1250
In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips/sibyte/sb1250

Modified Files:
	Makefile irq_handler.S 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1250/Makefile,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- Makefile	2001/11/21 22:07:56	1.4
+++ Makefile	2002/01/28 20:31:57	1.5
@@ -5,10 +5,11 @@
 
 O_TARGET := sb1250.o
 
-obj-y := setup.o irq.o irq_handler.o time.o lib_hssubr.o
+obj-y := setup.o irq.o irq_handler.o time.o
 
-obj-$(CONFIG_PCI) += pci.o
-obj-$(CONFIG_SMP) += smp.o
-obj-$(CONFIG_BCM1250_TBPROF) += bcm1250_tbprof.o
+obj-$(CONFIG_PCI)		+= pci.o
+obj-$(CONFIG_SMP)		+= smp.o
+obj-$(CONFIG_BCM1250_TBPROF)	+= bcm1250_tbprof.o
+obj-$(CONFIG_MIPS32)		+= lib_hssubr.o
 
 include $(TOPDIR)/Rules.make

Index: irq_handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1250/irq_handler.S,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- irq_handler.S	2001/12/02 19:05:30	1.4
+++ irq_handler.S	2002/01/28 20:31:57	1.5
@@ -17,7 +17,7 @@
  */
  
 /*
- *  sb1250_handle_int() is the routine that is actually called when an interrupt
+ * sb1250_handle_int() is the routine that is actually called when an interrupt
  * occurs.  It is installed as the exception vector handler in init_IRQ() in
  * arch/mips/sibyte/sb1250/irq.c
  *
@@ -48,10 +48,11 @@
  */
  
 	.text
-	.set    push
+	.set	push
 	.set	noreorder
 	.set	noat
-	.set    mips64
+	#.set	mips64
+	.set	mips4
 	.align	5
 	NESTED(sb1250_irq_handler, PT_SIZE, sp)
 	SAVE_ALL
@@ -59,34 +60,34 @@
 
 #ifdef CONFIG_SIBYTE_SB1250_PROF
 	/* Set compare to count to silence count/compare timer interrupts */
-	mfc0	 t1, CP0_COUNT
-	mtc0	 t1, CP0_COMPARE /* pause to clear IP[7] bit of cause ? */
+	mfc0	t1, CP0_COUNT
+	mtc0	t1, CP0_COMPARE /* pause to clear IP[7] bit of cause ? */
 #endif
 	/* Read cause */
-	mfc0     s0, CP0_CAUSE
+	mfc0	s0, CP0_CAUSE
 
 #ifdef CONFIG_SIBYTE_SB1250_PROF
 	/* Cpu performance counter interrupt is routed to IP[7] */
-	andi	 t1, s0, CAUSEF_IP7
-	beqz	 t1, 0f
-	 srl	 t1, s0, (CAUSEB_BD-2)  /* Shift BD bit to bit 2 */
-	and	 t1, t1, 0x4	/* mask to get just BD bit */
-	mfc0	 a0, CP0_EPC
-	jal	 sbprof_cpu_intr
-	 addu	 a0, a0, t1	/* a0 = EPC + (BD ? 4 :	0) */
+	andi	t1, s0, CAUSEF_IP7
+	beqz	t1, 0f
+	 srl	t1, s0, (CAUSEB_BD-2)  /* Shift BD bit to bit 2 */
+	and	t1, t1, 0x4		/* mask to get just BD bit */
+	mfc0	a0, CP0_EPC
+	jal	sbprof_cpu_intr
+	 addu	a0, a0, t1		/* a0 = EPC + (BD ? 4 :	0) */
 	j	ret_from_irq
 	 nop				# delay slot
 0:
 #endif
 	/* Timer interrupt is routed to IP[4] */
-	andi     t1, s0, CAUSEF_IP4
-	beqz     t1, 1f
+	andi	t1, s0, CAUSEF_IP4
+	beqz	t1, 1f
 	 nop
-	jal      sb1250_timer_interrupt
-	 move    a0, sp  /* Pass the registers along */
+	jal	sb1250_timer_interrupt
+	 move	a0, sp			/* Pass the registers along */
 	j	ret_from_irq
 	 nop				# delay slot
-1:	
+1:
 
 #ifdef CONFIG_SMP
 	/* Mailbox interrupt is routed to IP[3] */
@@ -108,15 +109,16 @@
 	 * Default...we've hit an IP[2] interrupt, which means we've got to
 	 * check the 1250 interrupt registers to figure out what to do
 	 */
-	la       v0, KSEG1 + A_IMR_CPU0_BASE
-	ld       s0, R_IMR_INTERRUPT_STATUS_BASE(v0)		/* read IP[2] status */
+	la	v0, KSEG1 + A_IMR_CPU0_BASE
+	ld	s0, R_IMR_INTERRUPT_STATUS_BASE(v0)	/* read IP[2] status */
 
-	beqz     s0, 4f         /* No interrupts.  Return */
+	beqz	s0, 4f		/* No interrupts.  Return */
 	 move	a1, sp
 
-3:	dclz     s1, s0         /* Find the next interrupt */
-	dsubu    a0, zero, s1
-	daddiu   a0, a0, 63     
+3:	#dclz	s1, s0		/* Find the next interrupt */
+	.word   0x72118824	# dclz s1, s0
+	dsubu	a0, zero, s1
+	daddiu	a0, a0, 63     
 	jal	 do_IRQ
 	 nop