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[Linux-mips-commits]CVS: linux/include/asm-mips64 asm.h,1.7,1.8 io.h,1.12,1.13 mipsregs.h,1.8,1.9 mmu_context.h,1.3,1.4 page.h,1.5,1.6 pci.h,1.9,1.10 pgtable.h,1.7,1.8 scatterlist.h,1.1,1.2 system.h,1.7,1.8
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From: James S. <jsi...@us...> - 2002-01-28 20:32:08
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Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv7656/include/asm-mips64
Modified Files:
asm.h io.h mipsregs.h mmu_context.h page.h pci.h pgtable.h
scatterlist.h system.h
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.
Index: asm.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/asm.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- asm.h 2001/11/19 17:30:16 1.7
+++ asm.h 2002/01/28 20:32:05 1.8
@@ -105,20 +105,20 @@
TEXT(string)
#define TEXT(msg) \
- .data; \
+ .pushsection .data; \
8: .asciiz msg; \
- .previous;
+ .popsection;
/*
* Build text tables
*/
#define TTABLE(string) \
- .text; \
+ .pushsection .text; \
.word 1f; \
.previous; \
.data; \
1: .asciz string; \
- .previous
+ .popsection
/*
* MIPS IV pref instruction.
Index: io.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/io.h,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- io.h 2002/01/02 19:12:18 1.12
+++ io.h 2002/01/28 20:32:05 1.13
@@ -34,6 +34,10 @@
#include <asm/ip32/io.h>
#endif
+#ifdef CONFIG_SIBYTE_SB1250
+#include <asm/sibyte/sb1250_io.h>
+#endif
+
extern unsigned long bus_to_baddr[256];
/*
@@ -63,6 +67,8 @@
* Change "struct page" to physical address.
*/
#define page_to_phys(page) PHYSADDR(page_address(page))
+
+typedef unsigned long phys_t;
/*
* On MIPS, we have the whole physical address space mapped at all
Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mipsregs.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- mipsregs.h 2001/12/02 19:05:32 1.8
+++ mipsregs.h 2002/01/28 20:32:05 1.9
@@ -383,7 +383,7 @@
* R10000 performance counter definitions.
*
* FIXME: The R10000 performance counter opens a nice way to implement CPU
- * time accounting with a precision of one cycle. I don't have
+ * time accounting with a precission of one cycle. I don't have
* R10000 silicon but just a manual, so ...
*/
@@ -448,7 +448,7 @@
__res;})
#define read_64bit_cp0_register(source) \
-({ int __res; \
+({ unsigned long __res; \
__asm__ __volatile__( \
".set\tmips3\n\t" \
"dmfc0\t%0,"STR(source)"\n\t" \
Index: mmu_context.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mmu_context.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- mmu_context.h 2001/11/19 17:35:09 1.3
+++ mmu_context.h 2002/01/28 20:32:05 1.4
@@ -14,6 +14,7 @@
#include <linux/config.h>
#include <linux/slab.h>
#include <asm/pgalloc.h>
+#include <asm/pgtable.h>
/*
* For the fast tlb miss handlers, we currently keep a per cpu array
@@ -57,6 +58,7 @@
unsigned long asid = ASID_CACHE(cpu);
if (! ((asid += ASID_INC) & ASID_MASK) ) {
+ flush_icache_all();
local_flush_tlb_all(); /* start new asid cycle */
if (!asid) /* fix version if needed */
asid = ASID_FIRST_VERSION;
Index: page.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/page.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- page.h 2002/01/02 17:08:26 1.5
+++ page.h 2002/01/28 20:32:05 1.6
@@ -23,6 +23,13 @@
#define BUG() do { printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); *(int *)0=0; } while (0)
#define PAGE_BUG(page) do { BUG(); } while (0)
+/*
+ * Prototypes for clear_page / copy_page variants with processor dependant
+ * optimizations.
+ */
+void sb1_clear_page(void * page);
+void sb1_copy_page(void * to, void * from);
+
extern void (*_clear_page)(void * page);
extern void (*_copy_page)(void * to, void * from);
@@ -57,8 +64,8 @@
size = (size-1) >> (PAGE_SHIFT-1);
order = -1;
do {
- size >>= 1;
- order++;
+ size >>= 1;
+ order++;
} while (size);
return order;
}
@@ -81,6 +88,9 @@
#define PAGE_OFFSET 0x9800000000000000UL
#endif
#if defined(CONFIG_SGI_IP27)
+#define PAGE_OFFSET 0xa800000000000000UL
+#endif
+#if defined(CONFIG_SIBYTE_SB1250)
#define PAGE_OFFSET 0xa800000000000000UL
#endif
Index: pci.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/pci.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- pci.h 2002/01/02 19:12:18 1.9
+++ pci.h 2002/01/28 20:32:05 1.10
@@ -181,9 +181,7 @@
static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
int nents, int direction)
{
-#ifdef CONFIG_NONCOHERENT_IO
int i;
-#endif
if (direction == PCI_DMA_NONE)
BUG();
@@ -193,7 +191,7 @@
#ifdef CONFIG_NONCOHERENT_IO
dma_cache_wback_inv((unsigned long)sg->address, sg->length);
#endif
- sg->address = (char *)(bus_to_baddr[hwdev->bus->number] | __pa(sg->address));
+ sg->dma_address = (char *)(__pa(sg->address));
}
return nents;
Index: pgtable.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/pgtable.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- pgtable.h 2002/01/02 18:02:57 1.7
+++ pgtable.h 2002/01/28 20:32:05 1.8
@@ -27,13 +27,27 @@
* - flush_cache_range(mm, start, end) flushes a range of pages
* - flush_page_to_ram(page) write back kernel page to ram
*/
+extern void (*_flush_cache_all)(void);
+extern void (*___flush_cache_all)(void);
extern void (*_flush_cache_mm)(struct mm_struct *mm);
extern void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start,
- unsigned long end);
-extern void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page);
+ unsigned long end);
+extern void (*_flush_cache_page)(struct vm_area_struct *vma,
+ unsigned long page);
extern void (*_flush_page_to_ram)(struct page * page);
+extern void (*_flush_icache_range)(unsigned long start, unsigned long end);
+extern void (*_flush_icache_page)(struct vm_area_struct *vma,
+ struct page *page);
+extern void (*_flush_cache_sigtramp)(unsigned long addr);
+extern void (*_flush_icache_all)(void);
-#define flush_cache_all() do { } while(0)
+/* These suck ... */
+extern void (*_flush_cache_l2)(void);
+extern void (*_flush_cache_l1)(void);
+
+
+#define flush_cache_all() _flush_cache_all()
+#define __flush_cache_all() ___flush_cache_all()
#define flush_dcache_page(page) do { } while (0)
#ifndef CONFIG_CPU_R10000
@@ -73,15 +87,13 @@
} while (0)
#endif /* !CONFIG_CPU_R10000 */
-/*
- * The foll cache flushing routines are MIPS specific.
- * flush_cache_l2 is needed only during initialization.
- */
-extern void (*_flush_cache_sigtramp)(unsigned long addr);
-extern void (*_flush_cache_l2)(void);
-extern void (*_flush_cache_l1)(void);
-
#define flush_cache_sigtramp(addr) _flush_cache_sigtramp(addr)
+#ifdef CONFIG_VTAG_ICACHE
+#define flush_icache_all() _flush_icache_all()
+#else
+#define flush_icache_all() do { } while(0)
+#endif
+
#define flush_cache_l2() _flush_cache_l2()
#define flush_cache_l1() _flush_cache_l1()
@@ -529,8 +541,9 @@
extern pgd_t swapper_pg_dir[1024];
extern void paging_init(void);
-extern void (*update_mmu_cache)(struct vm_area_struct *vma,
- unsigned long address, pte_t pte);
+extern void (*_update_mmu_cache)(struct vm_area_struct *vma,
+ unsigned long address, pte_t pte);
+#define update_mmu_cache(vma, address, pte) _update_mmu_cache(vma, address, pte)
/*
* Non-present pages: high 24 bits are offset, next 8 bits type,
Index: scatterlist.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/scatterlist.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- scatterlist.h 2002/01/02 19:12:18 1.1
+++ scatterlist.h 2002/01/28 20:32:05 1.2
@@ -4,17 +4,16 @@
struct scatterlist {
char * address; /* Location data is to be transferred to */
struct page *page;
- unsigned int offset;
unsigned int length;
- __u32 dvma_address;
+ __u32 dma_address;
};
struct mmu_sglist {
char *addr;
char *__dont_touch;
unsigned int len;
- __u32 dvma_addr;
+ __u32 dma_addr;
};
#define ISA_DMA_THRESHOLD (0x00ffffffUL)
Index: system.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/system.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- system.h 2001/12/12 16:19:19 1.7
+++ system.h 2002/01/28 20:32:05 1.8
@@ -56,9 +56,9 @@
"xori\t$1,1\n\t"
".set\tnoreorder\n\t"
"mtc0\t$1,$12\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
+ "sll\t$0, $0, 1\t\t\t# nop\n\t"
+ "sll\t$0, $0, 1\t\t\t# nop\n\t"
+ "sll\t$0, $0, 1\t\t\t# nop\n\t"
".set\tpop\n\t"
".endm");
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