Menu
▾
▴
[Linux-mips-commits]CVS: linux/arch/mips/kernel setup.c,1.48,1.49
|
From: James S. <jsi...@us...> - 2002-01-28 19:17:22
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv7746/kernel
Modified Files:
setup.c
Log Message:
Rename sgi_setup to ip22_setup.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.48
retrieving revision 1.49
diff -u -d -r1.48 -r1.49
--- setup.c 2002/01/19 21:17:35 1.48
+++ setup.c 2002/01/28 19:17:18 1.49
@@ -150,15 +150,15 @@
case CPU_R4700:
case CPU_R5000:
case CPU_NEVADA:
-// case CPU_RM7000:
+ case CPU_RM7000:
case CPU_TX49XX:
cpu_wait = r4k_wait;
printk(" available.\n");
break;
- case CPU_SR7100:
+ case CPU_SR7100:
cpu_wait = sr7100_wait;
printk(" errata work around.\n");
- break;
+ break;
default:
printk(" unavailable.\n");
break;
@@ -216,9 +216,9 @@
/* declaration of the global struct */
struct mips_cpu mips_cpu = {
- processor_id: PRID_IMP_UNKNOWN,
- fpu_id: FPIR_IMP_NONE,
- cputype: CPU_UNKNOWN,
+ processor_id: PRID_IMP_UNKNOWN,
+ fpu_id: FPIR_IMP_NONE,
+ cputype: CPU_UNKNOWN
};
/* Shortcut for assembler access to mips_cpu.options */
@@ -387,6 +387,8 @@
mips_cpu.icache.ways = 2;
mips_cpu.dcache.ways = 2;
break;
+
+
case PRID_IMP_R6000:
mips_cpu.cputype = CPU_R6000;
mips_cpu.isa_level = MIPS_CPU_ISA_II;
@@ -434,7 +436,7 @@
mips_cpu.cputype = CPU_RC32300;
mips_cpu.isa_level = MIPS_CPU_ISA_M32;
mips_cpu.options = R4K_OPTS | MIPS_CPU_DIVEC |
- MIPS_CPU_WATCH;
+ MIPS_CPU_WATCH;
mips_cpu.tlbsize = 16;
mips_cpu.icache.ways = 2;
mips_cpu.dcache.ways = 2;
@@ -549,9 +551,9 @@
mips_cpu.cputype = CPU_SR7100;
mips_cpu.isa_level = MIPS_CPU_ISA_M64;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_4KTLB | MIPS_CPU_FPU |
- MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
- MIPS_CPU_MCHECK;
+ MIPS_CPU_4KTLB | MIPS_CPU_FPU |
+ MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
+ MIPS_CPU_MCHECK;
mips_cpu.scache.ways = 8;
break;
}
@@ -585,13 +587,14 @@
#endif
cpu_report();
+
/*
* Determine the mmu/cache attached to this machine,
* then flush the tlb and caches. On the r4xx0
* variants this also sets CP0_WIRED to zero.
*/
loadmmu();
-
+
/* Disable coprocessors and set FPU for 16 FPRs */
s = read_32bit_cp0_register(CP0_STATUS);
s &= ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_FR);
@@ -720,13 +723,13 @@
void swarm_setup(void);
void hp_setup(void);
void idt_setup(void);
- void casio_be300_setup(void);
+ void casio_be300_setup(void);
unsigned long bootmap_size;
- unsigned long start_pfn, max_pfn, first_usable_pfn;
+ unsigned long start_pfn, max_pfn, max_low_pfn, first_usable_pfn;
#ifdef CONFIG_BLK_DEV_INITRD
- unsigned long* initrd_header;
unsigned long tmp;
+ unsigned long* initrd_header;
#endif
int i;
@@ -751,10 +754,10 @@
baget_setup();
break;
#endif
-#ifdef CONFIG_COBALT_MICRO_SERVER
- case MACH_GROUP_COBALT:
- cobalt_setup();
- break;
+#ifdef CONFIG_MIPS_COBALT
+ case MACH_GROUP_COBALT:
+ cobalt_setup();
+ break;
#endif
#ifdef CONFIG_DECSTATION
case MACH_GROUP_DEC:
@@ -878,16 +881,16 @@
jmr3927_setup();
break;
#endif
-#ifdef CONFIG_PS2
- case MACH_GROUP_EE:
- ps2_setup();
- break;
-#endif
#ifdef CONFIG_SIBYTE_SWARM
case MACH_GROUP_SIBYTE:
swarm_setup();
break;
#endif
+#ifdef CONFIG_PS2
+ case MACH_GROUP_EE:
+ ps2_setup();
+ break;
+#endif
#ifdef CONFIG_HP_LASERJET
case MACH_GROUP_HP_LJ:
hp_setup();
@@ -913,6 +916,9 @@
#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
+#define MAXMEM HIGHMEM_START
+#define MAXMEM_PFN PFN_DOWN(MAXMEM)
+
#ifdef CONFIG_BLK_DEV_INITRD
tmp = (((unsigned long)&_end + PAGE_SIZE-1) & PAGE_MASK) - 8;
if (tmp < (unsigned long)&_end)
@@ -956,9 +962,36 @@
}
}
}
-
- /* Initialize the boot-time allocator. */
- bootmap_size = init_bootmem(first_usable_pfn, max_pfn);
+
+ /*
+ * Determine low and high memory ranges
+ */
+ max_low_pfn = max_pfn;
+ if (max_low_pfn > MAXMEM_PFN) {
+ max_low_pfn = MAXMEM_PFN;
+#ifndef CONFIG_HIGHMEM
+ /* Maximum memory usable is what is directly addressable */
+ printk(KERN_WARNING "Warning only %ldMB will be used.\n",
+ MAXMEM>>20);
+ printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n");
+#endif
+ }
+
+#ifdef CONFIG_HIGHMEM
+ /*
+ * Crude, we really should make a better attempt at detecting
+ * highstart_pfn
+ */
+ highstart_pfn = highend_pfn = max_pfn;
+ if (max_pfn > MAXMEM_PFN) {
+ highstart_pfn = MAXMEM_PFN;
+ printk(KERN_NOTICE "%ldMB HIGHMEM available.\n",
+ (highend_pfn - highstart_pfn) >> (20 - PAGE_SHIFT));
+ }
+#endif
+
+ /* Initialize the boot-time allocator with low memory only. */
+ bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
/*
* Register fully available low RAM pages with the bootmem allocator.
@@ -976,7 +1009,7 @@
* We are rounding up the start address of usable memory:
*/
curr_pfn = PFN_UP(boot_mem_map.map[i].addr);
- if (curr_pfn >= max_pfn)
+ if (curr_pfn >= max_low_pfn)
continue;
if (curr_pfn < start_pfn)
curr_pfn = start_pfn;
@@ -987,17 +1020,28 @@
last_pfn = PFN_DOWN(boot_mem_map.map[i].addr
+ boot_mem_map.map[i].size);
- if (last_pfn > max_pfn)
- last_pfn = max_pfn;
+ if (last_pfn > max_low_pfn)
+ last_pfn = max_low_pfn;
/*
+ * Only register lowmem part of lowmem segment with bootmem.
+ */
+ size = last_pfn - curr_pfn;
+ if (curr_pfn > PFN_DOWN(HIGHMEM_START))
+ continue;
+ if (curr_pfn + size - 1 > PFN_DOWN(HIGHMEM_START))
+ size = PFN_DOWN(HIGHMEM_START) - curr_pfn;
+ if (!size)
+ continue;
+
+ /*
* ... finally, did all the rounding and playing
* around just make the area go away?
*/
if (last_pfn <= curr_pfn)
continue;
- size = last_pfn - curr_pfn;
+ /* Register lowmem ranges */
free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
}
@@ -1093,8 +1137,8 @@
*/
void sr7100_wait(void)
{
- u32 *jump = ((u32 *)&ret_from_irq_sr7100);
-
+u32 *jump = ((u32 *)&ret_from_irq_sr7100);
+
__asm__ __volatile__ (
".set push\n\t"
".set noat\n\t"
|
