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[Linux-mips-commits]CVS: linux/include/asm-mips io.h,1.15,1.16 mipsregs.h,1.15,1.16 page.h,1.5,1.6 pgalloc.h,1.6,1.7 pgtable.h,1.10,1.11
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From: James S. <jsi...@us...> - 2002-01-28 18:48:13
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Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv30246/include/asm-mips
Modified Files:
io.h mipsregs.h page.h pgalloc.h pgtable.h
Log Message:
Support for 64-bit addresses in page tables.
Index: io.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/io.h,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- io.h 2002/01/02 18:10:40 1.15
+++ io.h 2002/01/28 18:48:10 1.16
@@ -12,11 +12,10 @@
#define _ASM_IO_H
#include <linux/config.h>
+#include <linux/pagemap.h>
#include <linux/types.h>
-
#include <asm/addrspace.h>
#include <asm/byteorder.h>
-#include <asm/mipsregs.h>
/*
* Slowdown I/O port space accesses for antique hardware.
@@ -143,12 +142,12 @@
static inline void *ioremap(unsigned long offset, unsigned long size)
{
- return __ioremap(offset, size, CONF_CM_UNCACHED << 9);
+ return __ioremap(offset, size, _CACHE_UNCACHED);
}
static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
{
- return __ioremap(offset, size, CONF_CM_UNCACHED << 9);
+ return __ioremap(offset, size, _CACHE_UNCACHED);
}
extern void iounmap(void *addr);
Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/mipsregs.h,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- mipsregs.h 2002/01/19 21:17:35 1.15
+++ mipsregs.h 2002/01/28 18:48:10 1.16
@@ -466,7 +466,7 @@
* For now use this only with interrupts disabled!
*/
#define read_64bit_cp0_register(source) \
-({ int __res; \
+({ unsigned long __res; \
__asm__ __volatile__( \
".set\tmips3\n\t" \
"dmfc0\t%0,"STR(source)"\n\t" \
@@ -493,26 +493,6 @@
".set\tmips0" \
: : "r" (value))
-#define read_32bit_cp0_registerx(source,sel) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
- ".set\tmips64\n\t" \
- "mfc0\t%0,"STR(source)","STR(sel)"\n\t" \
- ".set\tmips0\n\t" \
- ".set\tpop" \
- : "=r" (__res)); \
- __res;})
-
-#define write_32bit_cp0_registerx(register,sel,value) \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "mtc0\t%0,"STR(register)","STR(sel)"\n\t" \
- ".set\tmips0\n\t" \
- "nop" \
- : : "r" (value));
-
/*
* This should be changed when we get a compiler that support the MIPS32 ISA.
*/
@@ -607,20 +587,6 @@
: : "Jr" (val));
}
-/* CP0_ENTRYLO0 and CP0_ENTRYLO1 registers */
-static inline unsigned long get_entrylo0(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $2\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
#if defined(CONFIG_64BIT_PHYS_ADDR) && !defined(CONFIG_CPU_MIPS32)
/*
@@ -644,6 +610,41 @@
__restore_flags(flags);
}
+static inline void set_entrylo1(unsigned long long val)
+{
+ unsigned long flags;
+
+ __save_and_cli(flags);
+ __asm__ __volatile__(
+ ".set\tmips3\n\t"
+ "dsll\t%L0, %L0, 32\n\t"
+ "dsrl\t%L0, %L0, 32\n\t"
+ "dsll\t%M0, %M0, 32\n\t"
+ "or\t%L0, %L0, %M0\n\t"
+ "dmtc0\t%0, $3\n\t"
+ ".set\tmips0"
+ : : "r" (val));
+ __restore_flags(flags);
+}
+
+static inline unsigned long long get_entrylo0(void)
+{
+ unsigned long flags, val;
+
+ __save_and_cli(flags);
+ __asm__ __volatile__(
+ ".set\tmips0\n\t"
+ "dmfc0 %0, $2\n\t"
+ "dsrl\t%M0, %M0, 32\n\t"
+ "dsll\t%L0, %L0, 32\n\t"
+ "dsrl\t%L0, %L0, 32\n\t"
+ ".set\tmips0"
+ : "=r" (val));
+ __restore_flags(flags);
+
+ return val;
+}
+
static inline unsigned long long get_entrylo1(void)
{
unsigned long flags, val;
@@ -674,30 +675,43 @@
: : "Jr" (val));
}
-static inline unsigned long get_entrylo1(void)
+static inline void set_entrylo1(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $3\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_entrylo0(void)
{
unsigned long val;
__asm__ __volatile__(
".set push\n\t"
".set reorder\n\t"
- "mfc0 %0, $3\n\t"
+ "mfc0 %0, $2\n\t"
".set pop" : "=r" (val));
return val;
}
-#endif
-
-static inline void set_entrylo1(unsigned long val)
+static inline unsigned long get_entrylo1(void)
{
+ unsigned long val;
+
__asm__ __volatile__(
".set push\n\t"
".set reorder\n\t"
- "mtc0 %z0, $3\n\t"
- ".set pop"
- : : "Jr" (val));
+ "mfc0 %0, $3\n\t"
+ ".set pop" : "=r" (val));
+
+ return val;
}
+
+#endif
/* CP0_ENTRYHI register */
static inline unsigned long get_entryhi(void)
Index: page.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/page.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- page.h 2002/01/02 17:08:26 1.5
+++ page.h 2002/01/28 18:48:10 1.6
@@ -116,6 +116,11 @@
#define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
#define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
+/*
+ * Memory above this physical address will be considered highmem.
+ */
+#define HIGHMEM_START (0x20000000)
+
#endif /* defined (__KERNEL__) */
#endif /* __ASM_PAGE_H */
Index: pgalloc.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pgalloc.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- pgalloc.h 2002/01/02 18:10:40 1.6
+++ pgalloc.h 2002/01/28 18:48:10 1.7
@@ -11,6 +11,7 @@
#include <linux/config.h>
#include <linux/mm.h>
+#include <asm/fixmap.h>
/* TLB flushing:
*
@@ -103,8 +104,6 @@
{
free_pages((unsigned long)pgd, PGD_ORDER);
}
-
-extern pte_t *get_pte_slow(pmd_t *pmd, unsigned long address_preadjusted);
extern __inline__ pte_t *get_pte_fast(void)
{
Index: pgtable.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pgtable.h,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- pgtable.h 2002/01/02 18:10:40 1.10
+++ pgtable.h 2002/01/28 18:48:10 1.11
@@ -9,6 +9,7 @@
#ifndef _ASM_PGTABLE_H
#define _ASM_PGTABLE_H
+#include <linux/config.h>
#include <asm/addrspace.h>
#include <asm/page.h>
@@ -16,7 +17,7 @@
#include <linux/linkage.h>
#include <asm/cachectl.h>
-#include <linux/config.h>
+#include <asm/fixmap.h>
/* Cache flushing:
*
@@ -34,12 +35,13 @@
extern void (*___flush_cache_all)(void);
extern void (*_flush_cache_mm)(struct mm_struct *mm);
extern void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start,
- unsigned long end);
-extern void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page);
+ unsigned long end);
+extern void (*_flush_cache_page)(struct vm_area_struct *vma,
+ unsigned long page);
extern void (*_flush_page_to_ram)(struct page * page);
extern void (*_flush_icache_range)(unsigned long start, unsigned long end);
extern void (*_flush_icache_page)(struct vm_area_struct *vma,
- struct page *page);
+ struct page *page);
extern void (*_flush_cache_sigtramp)(unsigned long addr);
extern void (*_flush_icache_all)(void);
@@ -118,12 +120,17 @@
#define PGD_ORDER 0
#endif
-#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
+#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
#define FIRST_USER_PGD_NR 0
#define VMALLOC_START KSEG2
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
-#define VMALLOC_END KSEG3
+
+#if CONFIG_HIGHMEM
+# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
+#else
+# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
+#endif
/* Note that we shift the lower 32bits of each EntryLo[01] entry
* 6 bits to the left. That way we can convert the PFN into the
@@ -246,12 +253,17 @@
#if !defined (_LANGUAGE_ASSEMBLY)
+#ifdef CONFIG_64BIT_PHYS_ADDR
#define pte_ERROR(e) \
- printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
+ printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
+#else
+#define pte_ERROR(e) \
+ printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#endif
#define pmd_ERROR(e) \
- printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
+ printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
#define pgd_ERROR(e) \
- printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
+ printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
extern unsigned long empty_zero_page;
extern unsigned long zero_page_mask;
@@ -336,8 +348,8 @@
static inline void pgd_clear(pgd_t *pgdp) { }
/*
- * Permanent address of a page. On MIPS we never have highmem, so this
- * is simple.
+ * Permanent address of a page. Obviously must never be called on a highmem
+ * page.
*/
#define page_address(page) ((page)->virtual)
#ifdef CONFIG_CPU_VR41XX
@@ -469,6 +481,10 @@
}
#define page_pte(page) page_pte_prot(page, __pgprot(0))
+
+#define __pgd_offset(address) pgd_index(address)
+#define __pmd_offset(address) \
+ (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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