[Linux-mips-commits]CVS: linux/arch/mips/philips/nino Makefile,1.8,1.9 TODO,1.1,1.2 irq.c,1.7,1.8 prom.c,1.6,1.7 setup.c,1.7,1.8

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/philips/nino
In directory usw-pr-cvs1:/tmp/cvs-serv25829

Modified Files:
	Makefile TODO irq.c prom.c setup.c 
Log Message:
Your daily jolt of Nino updates.

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/Makefile,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- Makefile	2001/11/13 17:10:09	1.8
+++ Makefile	2001/11/26 19:24:11	1.9
@@ -11,11 +11,11 @@
 .S.o:
 	$(CC) $(AFLAGS) -c $< -o $@
 
-O_TARGET := nino.o
+O_TARGET	:= nino.o
 
 all: nino.o
 
-obj-y	 := int-handler.o irq.o setup.o prom.o power.o
+obj-y		:= int-handler.o irq.o setup.o prom.o power.o
 
 int-handler.o: int-handler.S
 

Index: TODO
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/TODO,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- TODO	2001/11/13 17:10:09	1.1
+++ TODO	2001/11/26 19:24:11	1.2
@@ -13,5 +13,6 @@
     and see what all the different IO pins are hooked to
 - KGDB
   * get stub working
-- SERIAL
-  * complete rewrite and use only one interrupt instead of two
+- MMU
+  * Use CONFIG_CPU_TX39XX instead of current CONFIG_CPU_R3000 and
+    start using 3912 specific MMU management.

Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/irq.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- irq.c	2001/11/06 20:23:54	1.7
+++ irq.c	2001/11/26 19:24:11	1.8
@@ -13,17 +13,30 @@
 #include <linux/sched.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mipsregs.h>
 #include <asm/tx3912.h>
 
+#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
+
 extern asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
 
 static void enable_irq6(unsigned int irq)
 {
 	if(irq == 0) {
-		IntEnable5 |= INT5_PERIODICINT;
-		IntEnable6 |= INT6_PERIODICINT;
+		outl(inl(TX3912_INT6_ENABLE) |
+			TX3912_INT6_ENABLE_PRIORITYMASK_PERINT,
+			TX3912_INT6_ENABLE);
+		outl(inl(TX3912_INT5_ENABLE) | TX3912_INT5_PERINT,
+			TX3912_INT5_ENABLE);
+	}
+	if(irq == 3) {
+		outl(inl(TX3912_INT6_ENABLE) |
+			TX3912_INT6_ENABLE_PRIORITYMASK_UARTARXINT,
+			TX3912_INT6_ENABLE);
+		outl(inl(TX3912_INT2_ENABLE) | TX3912_INT2_UARTA_RX_BITS,
+			TX3912_INT2_ENABLE);
 	}
 }
 
@@ -37,9 +50,20 @@
 static void disable_irq6(unsigned int irq)
 {
 	if(irq == 0) {
-		IntEnable6 &= ~INT6_PERIODICINT;
-		IntClear5 |= INT5_PERIODICINT;
-		IntClear6 |= INT6_PERIODICINT;
+		outl(inl(TX3912_INT6_ENABLE) &
+			~TX3912_INT6_ENABLE_PRIORITYMASK_PERINT,
+			TX3912_INT6_ENABLE);
+		outl(inl(TX3912_INT5_ENABLE) & ~TX3912_INT5_PERINT,
+			TX3912_INT5_ENABLE);
+		outl(inl(TX3912_INT5_CLEAR) | TX3912_INT5_PERINT,
+			TX3912_INT5_CLEAR);
+	}
+	if(irq == 3) {
+		outl(inl(TX3912_INT6_ENABLE) &
+			~TX3912_INT6_ENABLE_PRIORITYMASK_UARTARXINT,
+			TX3912_INT6_ENABLE);
+		outl(inl(TX3912_INT2_ENABLE) & ~TX3912_INT2_UARTA_RX_BITS,
+			TX3912_INT2_ENABLE);
 	}
 }
 
@@ -67,29 +91,35 @@
 {
 	int irq = -1;
 
-	if(IntStatus6 & INT6_PERIODICINT) {
+	if((inl(TX3912_INT6_STATUS) & TX3912_INT6_STATUS_INTVEC_UARTARXINT) ==
+		TX3912_INT6_STATUS_INTVEC_UARTARXINT) {
+		irq = 3;
+		goto done;
+	}
+	if((inl(TX3912_INT6_STATUS) & TX3912_INT6_STATUS_INTVEC_PERINT) ==
+		TX3912_INT6_STATUS_INTVEC_PERINT) {
 		irq = 0;
 		goto done;
 	}
 
-	/* if irq == -1, then the interrupt has already been cleared */
+	/* if irq == -1, then interrupt was cleared or is invalid */
 	if(irq == -1) {
-		panic("No handler installed for MIPS IRQ6\n");
+		panic("Unhandled High Priority PR31700 Interrupt = 0x%08x\n",
+			inl(TX3912_INT6_STATUS));
 	}
 
 done:
 	do_IRQ(irq, regs);
-
-end:	
-	return;
 }
 
 static void enable_irq4(unsigned int irq)
 {
 	set_cp0_status(STATUSF_IP4);
 	if(irq == 2) {
-		IntClear2 = 0xffffffff;
-		IntEnable2 |= 0x07c00000;
+		outl(inl(TX3912_INT2_CLEAR) | TX3912_INT2_UARTA_TX_BITS,
+			TX3912_INT2_CLEAR);
+		outl(inl(TX3912_INT2_ENABLE) | TX3912_INT2_UARTA_TX_BITS,
+			TX3912_INT2_ENABLE);
 	}
 }
 
@@ -129,31 +159,38 @@
 {
 	int irq = -1;
 
-	if(IntStatus2 & 0x07c00000) {
+	if(inl(TX3912_INT2_STATUS) & TX3912_INT2_UARTA_TX_BITS) {
 		irq = 2;
 		goto done;
 	}
 
-	/* if irq == -1, then the interrupt has already been cleared */
+	/* if irq == -1, then interrupt was cleared or is invalid */
 	if (irq == -1) {
-		panic("No handler installed for MIPS IRQ4\n");
+		printk("PR31700 Interrupt Status Register 1 = 0x%08x\n",
+			inl(TX3912_INT1_STATUS));
+		printk("PR31700 Interrupt Status Register 2 = 0x%08x\n",
+			inl(TX3912_INT2_STATUS));
+		printk("PR31700 Interrupt Status Register 3 = 0x%08x\n",
+			inl(TX3912_INT3_STATUS));
+		printk("PR31700 Interrupt Status Register 4 = 0x%08x\n",
+			inl(TX3912_INT4_STATUS));
+		printk("PR31700 Interrupt Status Register 5 = 0x%08x\n",
+			inl(TX3912_INT5_STATUS));
+		panic("Unhandled Low Priority PR31700 Interrupt\n");
 	}
 
 done:
 	do_IRQ(irq, regs);
-
-end:	
 	return;
 }
 
 void irq_bad(struct pt_regs *regs)
 {
 	/* This should never happen */
-	printk("Stray interrupt, spinning...\n");
 	printk(" CAUSE register = 0x%08lx\n", regs->cp0_cause);
 	printk("STATUS register = 0x%08lx\n", regs->cp0_status);
 	printk("   EPC register = 0x%08lx\n", regs->cp0_epc);
-	while(1);
+	panic("Stray interrupt, spinning...\n");
 }
 
 void __init nino_irq_setup(void)
@@ -166,19 +203,23 @@
 	/* Disable all hardware interrupts */
 	change_cp0_status(ST0_IM, 0x00);
 
-	/* Clear any pending interrupts */
-	IntClear1 = 0xffffffff;
-	IntClear2 = 0xffffffff;
-	IntClear3 = 0xffffffff;
-	IntClear4 = 0xffffffff;
-	IntClear5 = 0xffffffff;
+	/* Clear interrupts */
+	outl(0xffffffff, TX3912_INT1_CLEAR);
+	outl(0xffffffff, TX3912_INT2_CLEAR);
+	outl(0xffffffff, TX3912_INT3_CLEAR);
+	outl(0xffffffff, TX3912_INT4_CLEAR);
+	outl(0xffffffff, TX3912_INT5_CLEAR);
 
-	/* FIXME: disable interrupts 1,3,4 */
-	IntEnable1 = 0x00000000;
-	IntEnable2 = 0xfffff000;
-	IntEnable3 = 0x00000000;
-	IntEnable4 = 0x00000000;
-	IntEnable5 = 0xffffffff;
+	/*
+	 * Disable all PR31700 interrupts. We let the various
+	 * device drivers in the system register themselves
+	 * and set the proper hardware bits.
+	 */
+	outl(0x00000000, TX3912_INT1_ENABLE);
+	outl(0x00000000, TX3912_INT2_ENABLE);
+	outl(0x00000000, TX3912_INT3_ENABLE);
+	outl(0x00000000, TX3912_INT4_ENABLE);
+	outl(0x00000000, TX3912_INT5_ENABLE);
 
 	/* Initialize IRQ vector table */
 	init_generic_irq();
@@ -188,10 +229,8 @@
 		hw_irq_controller *handler = NULL;
 		if (i == 0 || i == 3)
 			handler		= &irq6_type;
-		else if (i == 2)
-			handler		= &irq4_type;
 		else
-			handler		= NULL;
+			handler		= &irq4_type;
 
 		irq_desc[i].status	= IRQ_DISABLED;
 		irq_desc[i].action	= 0;
@@ -203,7 +242,8 @@
 	set_except_vector(0, ninoIRQ);
 
 	/* Enable high priority interrupts */
-	IntEnable6 = (INT6_GLOBALEN | 0xffff);
+	outl(TX3912_INT6_ENABLE_GLOBALEN | TX3912_INT6_ENABLE_HIGH_PRIORITY,
+		TX3912_INT6_ENABLE);
 
 	/* Enable all interrupts */
 	change_cp0_status(ST0_IM, ALLINTS);

Index: prom.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/prom.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- prom.c	2001/11/13 17:10:09	1.6
+++ prom.c	2001/11/26 19:24:11	1.7
@@ -26,8 +26,7 @@
 #endif
 
 /* Do basic initialization */
-void __init prom_init(int argc, char **argv,
-		unsigned long magic, int *prom_vec)
+void __init prom_init(int argc, char **argv, unsigned long magic, int *prom_vec)
 {
 	unsigned long mem_size;
 

Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/setup.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- setup.c	2001/11/13 17:10:09	1.7
+++ setup.c	2001/11/26 19:24:11	1.8
@@ -42,7 +42,21 @@
 
 static void __init nino_board_init()
 {
-	/* Nothing for now */
+	/*
+	 * Set up the master clock module. The value set in
+	 * the Clock Control Register by WindowsCE is 0x00432ba.
+	 * We set a few values here and let the device drivers
+	 * handle the rest.
+	 *
+	 * NOTE: The UART clocks must be enabled here to provide
+	 *       enough time for them to settle.
+	 */
+	outl(0x00000000, TX3912_CLK_CTRL);
+	outl((TX3912_CLK_CTRL_SIBMCLKDIR | TX3912_CLK_CTRL_SIBMCLKDIV_2 |
+		TX3912_CLK_CTRL_ENSIBMCLK | TX3912_CLK_CTRL_CSERSEL |
+		TX3912_CLK_CTRL_CSERDIV_3 | TX3912_CLK_CTRL_ENCSERCLK |
+		TX3912_CLK_CTRL_ENUARTACLK | TX3912_CLK_CTRL_ENUARTBCLK),
+		TX3912_CLK_CTRL);
 }
 
 static __init void nino_time_init(void)
@@ -51,7 +65,7 @@
 	outl(TX3912_SYS_TIMER_VALUE, TX3912_TIMER_PERIOD);
 	outl(TX3912_TIMER_CTRL_ENPERTIMER, TX3912_TIMER_CTRL);
 
-	/* Enable the timer clock line */
+	/* Enable the master timer clock */
 	outl(inl(TX3912_CLK_CTRL) | TX3912_CLK_CTRL_ENTIMERCLK,
 		TX3912_CLK_CTRL);
 
@@ -72,7 +86,7 @@
 	extern void nino_wait(void);
 
 	irq_setup = nino_irq_setup;
-	mips_io_port_base = KSEG1ADDR(0x10c00000);
+	set_io_port_base(KSEG1ADDR(0x10c00000));
 
 	_machine_restart = nino_machine_restart;
 	_machine_halt = nino_machine_halt;